ISSN: 2277-3754

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International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 5, November 2012


277

Abstract I n this paper a new design is proposed improved
weighted modulo 2
n
+1 design (I WMD) based on parallel prefix
adder. The existing all parallel prefix adder sklansky style, Han
Carlson, Kogge Stone and Brent Kung prefix structures are
analyzed then designed weighed modulo 2
n
+1 adder based on
Brent Kung. The Brent Kung required less area and power when
compare with other parallel prefix adders. The new design all
blocks are implemented in TSMC 180nm technology and the
results comparison between the all existing parallel prefix
structure based diminished -1 adder was reported .Our proposed
adders can produce modulo sums within the range {2
n
+1 }.

I ndex Terms Improved Weighted Modulo 2
n
+1 Design
(IWMD), Parallel Prefix Adder, Modulo 2
n
+1, Brent Kung,
VLSI Design.
I. INTRODUCTION
The Residue number system (RNS) is the most important
application in DSP for computation [3]. RNS based
computations can achieve significant speedup over the
binary-system-based computation; they are widely used in
DSP processors, FIR filters, and communication components.
The RNS representation as follows


Where m
i
is the member of the set of the co prime integer
called moduli. The diminished one number system is often
used for modulo operation, where each of the input and output
operant is decreased by 1(example A*=A-1) and the value 0 is
not used or treated separately because it requires an additional
zero indication bit which is omitted here.
The diminished-1 needs only n bit for modulo 2
n
+1
addition, leading to smaller and faster components. However,
this incurs an overhead due to the translators from/to the
binary weighted system. On the other hand, the weighted-1
representation uses (n + 1)-bit operands for computations,
avoiding the overhead of translators, but requires larger area
compared with the diminished-1 representations. So the
circular carry selection scheme was used to improve the
areatime and timepower products and efficiently select the
correct carry-in signals for final modulo addition. The
previous methods all deal with diminished-1 modulo addition
[2]. However, the hardware for decreasing /increasing the
inputs/outputs by 1 is omitted in the literature. In addition, the
value zero is not allowed in diminished-1 modulo 2
n
+1
addition, and hence, the zero-detection circuit is required to
avoid incorrect computation. The Brent Kung tree based
prefix structure uses only less area when compared with the
sklansky style prefix structure [1]. This leads to increased
hardware cost. The proposed unified approach for weighted
and diminished-1 modulo 2
n
+1 addition is based on making
the modulo 2
n
+1 addition of two (n + 1)-bit input numbers A
and B congruent to Y + U + 1, where Y and U are two n-bit
numbers [1]. Thus, any dimished-1 adder can be used to
perform weighted modulo 2
n
+1 addition of Y and U. The
authors first used the translators to decrease the sum of two
n-bit inputs A and B by 1 and then performed the weighted
modulo 2
n
+ 1 addition using diminished-1 adders [1]. In this
design the advantages of both of the previous two modulo
(2
n
+1) adders (diminished-1, weighted-1) are combined to
reduce the area & improve the performance.
Reviewing is carried out for sklansky style, Han Carlson,
Kogge Stone and Brent Kung prefix structure in section II.
The proposed modulo 2
n
+1 addition presented in section III.
Our conclusions are in section IV.
II. PARALLEL PREFIX ADDER
A. Sklansky Prefix Tree
The parallel prefix tree is used to compute generate and
propagate signals. This is often desirable to use an adder with
good timing, area and efficiency tradeoff characteristics. They
generate and propagate signals computation performed with
adjacent blocks. The carry computation method leads to speed
up the overall operation significantly.
The equation for computing the generate and propagate
values of the combined blocks are
G
i,k
= G
i,j+1
+(P
j,j+1
+ G
j,k
)
P
i,k
= P
i,j+1
+ P
j,k

Fig 1: 16-Bit Sklansky Prefix Tree
Pre Improved Weighted Modulo 2
n
+1 Design
Based On Parallel Prefix Adder
Dr.V.Vidya Devi, T.Venishkumar, T.Thomas Leonid
PG Head/Professor, Graduate Student, Assistant Professor
KCG College of Technology, Chennai, Anna University



ISSN: 2277-3754
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International Journal of Engineering and Innovative Technology (IJEIT)
Volume 2, Issue 5, November 2012


278
Many parallel prefix adders are available. The parallel
prefix adders are differing with in design of carry propagation
of logic levels and area tradeoff characteristics.
A Sklansky parallel-prefix adder (Figure 1) was proposed
for conditional sum. Rather than waiting for propagated carry
signal to generate each sum this scheme first generates sum
and carry-out pairs by using both possibilities of carry-in
signal at each bit position. The correct output is then selected
upon the arrival of carry-in signal. And it has a prefix structure
of minimal depth and is therefore among the fastest adder
architectures. Sklansky prefix tree use less logic levels to
compute the carries. In addition, it uses less cells when
compare with Kogge-Stone structure at the cost of higher
fan-out.
The above shows the 16-bit Sklansky prefix tree with
critical path in solid line. The sklansky style prefix structure
uses large area when compared with the Brent-kung tree
parallel prefix structures For a 16-bit Sklansky prefix tree, the
maximum fan-out is 9 (i.e. f = 3). The structure can be viewed
as a compacted version of Brent-kung's, where logic levels are
reduced and fan-out increased. The number of logic levels is
log2n. Each logic level has n=2 cells as can be observed in
Figure 4.6. The area is estimated as (n/2) log2n. When n = 16,
32 cells are required. [www.asic-world.com]
B. Han Carlson Prefix Tree
The Han-Carlson adder combines the Brent-Kung and
Kogge-Stone structures into a hybrid structure and it has a
maximum fan-out of 2 or f = 0. This is more efficient and
Suitable for VLSI implementation.

Fig 2: 16 Bit Han Carlson Prefix Tree
The Han Carlson and Sklansky have same number of cells
but the ham Carlson (Figure 2) needs less time compute the
cells.
C. Kogge Stone Prefix Tree
The next parallel prefix tree is Kogge stone (Figure 3) and
the Kogge stone adder has low depth, high node count it
implies more area and minimal fan out of 1 at each node it
implies faster performance. [www.acsel-lab.com]


Fig 3: 16 bit Kogge Stone prefix tree
D. Brent and Kung Prefix Tree
The next parallel prefix tree is Brent Kung (Figure 4)
often used to compute generate and propagate signals which is
a well-known structure with relatively sparse network. The
BrentKung adder is one of the more advanced designs,
having a gate level depth of O (log2 (n)). The fan-out is
among the minimum as f = 0. So is the wire tracks where t =
0. The cost is the extra L - 1 logic levels.

Fig 4: 16 Bit Brent Kung prefix tree
The critical path is shown in the figure with a thick gray
line. Brent-Kung tree uses only less area when compared with
Sklansky prefix tree.
The Brent-Kung adder is a good balance between area,
power cost and performance. The Brent-Kung parallel-prefix
adder gives a good trade-off between area and speed, lying in
the range of -15% to -30% area reduction at +15% to +30%
delay increase as compared to the faster Sklansky parallel
Prefix adder.
III. PROPOSED MODEL
A. Modulo Calculation
An improved area-efficient weighted modulo 2
n
+1 adder
design using diminished-1 adders with simple correction



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International Journal of Engineering and Innovative Technology (IJEIT)
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279
schemes [1]. This is achieved by subtracting the sum of two
(n + 1)-bit input numbers by the constant 2n + 1 and
producing carry (V) and sum (U) vectors. In addition, we
make the two inputs A and B to be in the range {0, 2
n
}.

Given two (n + 1)-bit inputs,. A = a
n
a
n1
. . . a
0
and B =b
n

b
n1
, . . . , b
0
, where 0 A, B 2n. The weighted modulo 2
n
+1
of A + B can be represented as follows
From this equation the value of modulo 2
n
+1 addition can
be obtained by subtracting 2
n
+1 from the sum of A and B.
The modulo 2
n
+1 addition can then performed using parallel
prefix structure(Brent-Kung) diminished-1 adders by taking
in the sum(U) and carry vectors(V) plus the inverted end
around carry with simple correction schemes..
For Generation v
n-1
, u
n-1
, and fix
(*: conditions when vn-1 = 2)

Table 1 Truth Table [1]
a
n
b
n
a
n-1
b
n-1


u
n-1
v
n-1
FIX
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0
0 1 0
0 1 0
1 1 0
1 1 0
X X X
0 1* 1
X X X
1 1 0
0 1* 1
X X X
X X X
1 1* 1
X X X
X X X
X X X

The V
n-1
,U
n-1
and FIX which is produced by truth table.
Where is X denoted as dont care. The FIX is wired OR with
the carry out of sum of carry (V) and sum (U) to be the
inverted end around carry as a carry in for diminished -1
addition.
In the general block diagram of 2
n
+1 adder the inverter has
been taken as cout as a input. In this end-around adder, cout
needs to be inverted before going to the incremented.

Fig 5: General Block Diagram Of Modulo 2
n
+1

Fig 6: Block Diagram Of Proposed Modulo 2
n
+1 Adder
The modified block diagram for modulo 2
n
+1 addition is
given above. Two most significant bit taken as a input to the
correction scheme. The correction scheme output wired OR
with cout, which is the input of end around block.
These all blocks are implemented in 0.13 m CMOS
technology and the results comparison between the Sklansky
and Brent Kung parallel prefix structure based diminished -1
adder given below.
||A+B|
2
n
+1
|2
n
= { |A+B-(2
n
+1) |
2
n

, if (A+B) > 2n
|A+B-(2
n
+1) |
2
n
+1,
Otherwise
|A+B|
2
n
+1
= { A+B-(2
n
+1)
,
if (A+B) > 2n
A+B , Otherwise
The equation can be stated as
||A+B|
2
n
+1
|2
n
= { |A+B-(2
n
+1) |
2
n
,
if (A+B) > 2n
|A+B-(2
n
+1)|
2
n
+|(2
n
+1)|
2
n
,
Otherwise




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280
IV. SYNTHESIZE RESULT AND COMPARISON
WITH TSMC 180 NM TECHNOLOGY

Fig 7: 16 Bit Sklansky Area with TSMC 180 Nm

Fig 8: 16 Bit Kogge Stone Area with TSMC 180 Nm

Fig 9: 16 Bit Han Carlson Area with TSMC 180 Nm

Fig 10: 16 Bit Brent and Kung Area with TSMC 180 Nm

Table 2. POWER AND AREA SYNTHESIS RESULT FOR VARIOUS
MODULO 2
N
+1 ADDERS
Adder 16 bit Power(mw) Area(m)
Sklansky 305.747 3219.96
Kogge Stone 376.202 3805.40
Han Carlson 305.320 3216.63
Brent Kung 287.476 3000.41

V. CONCLUSION
In conclusion, we have implemented improved weighted
modulo 2
n
+1 design based on parallel prefix adder. In this
paper the Brent Kung parallel prefix structure based
diminished -1 adder to achieve better area and power tradeoff
charactreistics in TSMC 180 nm technology. This will
produce sums that are within the range {0,2
n
}.

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[14] B. Parhami, RNS Representation with Redundant Residues,
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AUTHOR BIOGRAPHY

Dr.V.Vidya devi got her PHd in Electronics and communication,
engineering done her PG from Anna university and graduated from Anna
university Guindy campus in 1986.Presently she is working as a PG
coordinator / Professor in K C G college of technology. Her areas of interest
are digital signal processing, network security and VLSI design.

Mr. T.Venishkumar Got his PG degree from K C G College of
technology and at present working as a assistant Lecturer in Annai Arunai
engineering college, Tamil Nadu. His area of interest is in embedded system
and VLSI design technology

Mr.TThomas Leonid post graduated from Bharath university .Presently
working as a Assistant professor in K C G college of technology, Chennai.
He is guiding the students in embedded system and VLSI technology .His
area of interest are VLSI testing and optimum performance in power and
area reduction in VLSI Design. .