D: Electrical Devices

* Invited paper
SESSION D1: High-Speed and High-Performance
Nitride HEMTs and Modeling
Chair: Kevin Chen and Miroslav Micovic
Monday Afternoon, August 26, 2013
Chesapeake 4-6
1:30 PM *Dl.01
Nano-Crystalline Diamond Coated AlGaN/GaN HEMT
Pulsed I-V and RF Performance, David J. Meyer', Tatyana 1.
Feygelson', Travis J. Anderson', Marko J. Tadjer,,2, Jason A.
Roussos
l
, Brian P. Downeyl, D. S. Kab'jer
1
1
Bradford B. Patel, Mario
G. Anconal, Steven C. I3inari
1
, Karl D. Hobart
l
and Charles R.
Eddy!; INaval Research Laboratory, Washington, District of
Columbia; 2Post doctoral Fellow, ASEE, Washington, District of
Columbia.
While often touted as being a superior choice for high power
performance, GaN transistors also possess the lesser mentioned
burden of having high power dissipation. When used in a
non-switching mode of amplification (i.e. Class A, AB, B, etc.), limits
on the efficiency of a GaN high-electron-mobility transistor (HEMT)
result in large arnounts of power (several W /rrun) being dissipated in
the form of resistive heating, typically localized to the depletion
region near the drain-edge of the gate electrode. The formation of a
hot spot in this high-electric field region of the device degrades
electrical performance, but perhaps more importantly can increase
susceptibility to long-terrn reliability degradation rnechanisrns. As a
method for reducing the junction temperatures of AIGaN/GaN
HEMTs during RF operation, we have explored the use of a
high-thermal conductivity nano-crystalline diamond (NCD) coating.
In split-wafer experiments, we have observed that 1.5 Mm gate-length
HEMTs with a passivation layer of 0.4 rLIn NCD on 50 nrn silicon
nitride (SiNx), fabricated with a "gate-after-diamond" process flow,
electrically outperformed reference HEMTs with either 50 nm or 100
nm SiNx only. DC electrical characterbation revealed that the
NCD-coated HEMTs had approxirnately 20% higher transconductance
and a +2 V shift in threshold voltage (-1.4 V vs. -3.4 V), as compared
to reference HEMTs. Small-signal characterization of NCD-coated
devices determined that fr and f=ax were 6 and 23 GHz, respectively.
Pulsed I-V and gate-lag measurements indicated that NCD-coated
devices experience little to no dc-RF dispersion. Lastly, 4 GHz
load-pull measurements showed that NCD-coated HEMTs exhibited
roughly 1 W /mm higher RF output power density, compared to
reference HEMTs, over a range of drain bias from 20 to 50 V. At VDS
= 50 V in Class AB, the NCD-coated device had Pout = 5.8 W /mm
with 9.6 dI3 gain and 28.8% power-added efficiency.
2:00 PM Dl.02
How the Fringing Capacitance Limits the RF Performance of
High-Speed GaN HEMTs. Bo Song', Berardi Sensale-Rodriguez',
Ronghua Wang
l
, Jia Guo
l
, Michael Schuette
2
, Andrew Ketterson
2
,
Edward Dearn
2
, Paul Saunier
2
, Xiang Gao
3
, Shiping Guo
3
, Patrick
Fay', Debdeep Jena' and Huili G. Xing'; 'Department of Electrical
Engineering, University of Notre Dame, Notre Dame, Indiana;
2 TriQuint Semiconductor, Richardson, Texas; 3IQE RF LLC,
Somerset, New Jersey.
GaN based enhancement-mode (E-mode) high electron mobility
transistors (HEMTs) are attractive for high speed high power
applications [1]. When the gate length is below 100 nm, the RC
parasitic charging delay caused by source/drain resistances and gate
fringing capacitance can account for a large fraction of the total delay
[2]. The parasitic resistance issue has been addressed by employing
barriers such as InAIN and InAIGaN[3] and regrown n+ GaN
contacts[4]. In this paper, the impact of fringing capacitance on the
high frequency perforrnance of T-gate recessed InAlN HEMTs with
ft/fmax of 225/250 GHz [5] is investigated. The fringing capacitance
accounts for more than 40% of the total gate capacitance, which
limits the speed of ultra-scaled devices. Approaches to reduce this
effect are also presented. Graded n+ InGaN/GaN regrown ohmic
contacts are used and E-rnode operation is achieved by gate recess
process. The gate length Lg is ~ nm, of which approximately 23 nm
lies along on the bottom of the recess region, flanked by two
triangular partially-recessed areas. The DC and small signal RF
characteristics are reported in [5J. From delay time analyses, it was
found that the parasitic delay tirne is 0.39 ps, which is rnore than 50%
of the total delay time. Based on the ECP results in [5] and the
equation: Tpar=(Cgs,ext+Cgd,ext)/ gm+Cgd (Rs+Rd)+(Cgs+
Cgd)(Rs+Rd)gds/gm (1) the dominant parasitic delay time is due to
extrinsic fringing capacitances Cgs,ext/Cgd,ext. Sirnulation of
Cgs,ext/Cgd,ext was performed in COMSOL based on the gate
geometry measured from TEM and the 2DEG depletion from TCAD.
Cgs,ext/Cgd,ext were estimated to be ~ 260/162 IF/mm, consistent
with the extracted value of 238/161 fF/rnrn froIll rneasured
s-parameters under the coldFET bias condition. Assuming
Cgs,ext/Cgd,ext under the peak IT bias condition are the same (i.e.
an underestimate of Cext since the 2DEG depletion extensions are
smaller under the peak fT bias), the intrinsic capacitances are then
estirnated by subtracting the sirnulated Cgs,ext/Cgd,ext froIll the
ECP Cgs and Cgd values. Cgs,ext/Cgd,ext account for up to 40% of
the total gate capacitance. The COMSOL simulation results suggest
that Cgs,ext / Cgd,ext can be lowered to 231/150 IF/mm when the
gate stern height increases to 200 nnl. Further reduction to rv 160/101
fF/ nun can be achieved if the dielectric surrounding the gate is
removed (the SiON relative permittivity Er is assumed to be 5).
Cgs,ext / Cgd,ext can be further reduced by removing the T -gate cap.
This analysis suggests that maximbdng intrinsic gm is the key to
further rninirnizing (Cgs,ext + Cgd,ext /grn). Therefore, it is
important to seek approaches that enhance injection velocity in GaN
HEMTs for further improvements in ft and fmax. [l]Y.Yue et al.IEEE
EDL,33,988(2012). [2]B. Sensale-Rodriguez et at. SSE, 80, 67(2013).
[3] R. Wang et at. IEEE EDL, 32, 1125 (2011). [4] J. Guo et at. IEEE
EDL, 33,525 (2012). [5] I3.Song et at. IEEE DRC(2012)
2:15 PM DL03
65 nm T-gate SiN/lnAIN/AIN/GaN MIS-HEMTs with f t x
V
BK
of 9 THz-V. Brian P. Downey', David J. Meyer', D. S.
Kab'jer
l
, Thomas M. Marron
2
, David F. Storm
l
, Ming Pan
3
and
Xiang Gao
3
; lElectronics Science and Technology Division, Naval
Research Laboratory, Washington, District of Columbia; 2 Naval
Surface Warfare Center, Dahlgren, Virginia; 3IQE RF, Somerset, New
Jersey.
Increasing the frequency perforrnance in III-N-based
high-electron-mobility-transistors (HEMTs) requires both vertical and
lateral scaling. While higher frequency performance is expected for
aggressively-scaled devices, increased gate leakage current and
prernature device breakdown that lirnit the ultirnate power potential
of the technology are two potential areas of concern. In this study we
use an ultra-thin (1 - 6 nm) silicon nitride (SiN) gate insulator,
deposited by molecular-beam epitaxy at 575
0
C, to not only suppress
gate leakage current, but also to induce a high electron sheet carrier
density (nsH) in a rnetal-organic chernical vapor deposition grown
InAIN/AIN/GaN heterostructure (InAIN/AIN = 2.3 nm/1 nm) with
initially low nSH. Both nSH and sheet resistance were observed to
scale with the SiN thickness indicating the presence of a positive fixed
charge. MIS-HEMTs with gate lengths (L
G
) down to 65 nm have been
fabricated. For a SiN thickness of 3 nrn and Lc = 65 run, the gate
leakage current was less than 100 nA/mm at V G = -10 V, breakdown
voltage (VBK) was 82 V, extrinsic current gain cutoff frequency (ft )
was 118 GHz, and maximum frequency of oscillation was 208 GHz.
The simultaneously high V BK and ft leads to an extrinsic Johnson
figure of merit (f
t
xVBK) greater than 9 THz-V.
2:30 PM DL04
In - situ SiN
x
Gate Dielectric by MOCVD for
Low-Leakage-Current Ultra-Thin-Barrier AIN/GaN
MISHMETs on Si. Xing Lu, Jun Ma, Zhaojun Liu, Tongde Huang
and Kei May Lau; Department of Electronic and Computer
Engineering, The Hong Kong University of Science and Technology,
Kowloon, Hong Kong.
AIN/GaN heterostructures with ultra-thin barrier offer high 2DEG
concentration and good carrier confinement because of the relatively
large bandgap of AIN and strong polarization effects [1]. However, low
quality thin AIN and poor interfaces can lead to problems such as
large leakage current and surface sensitivity lirniting the device
performance and reliability. To date, several ex - situ deposited
dielectrics such as CVD SiNx [2], ALD Al 20 3 [3] [4] and ALD Hf02
[5] have been explored as gate insulator. Limited work has been
reported using In - situ SiNx on AIN/ GaN structure with successful
suppression of gate leakage [6]. In this study, 7 nrn and 3 nrn
In - situ SiNx were employed as gate dielectric for the
ultra-thin-barrier (1.5 nm) AIN/GaN MISHEMTs on Si substrate.
The In - situ SiN,T is very effective in suppressing the leakage current
and protecting the AlN surface. The In - situ SiNx was deposited
using silane and ammonia immediately after the AIN/GaN
heterostructure growth in the MOCVD chamber at 1145C. AFM and
TEM observations of the sample with 7 nm In - situ SiN
x
showed a
smooth surface morphology (RMS of 2.36 nm across a 5 Mm X 5 Mm
scanned area) and good coverage. Circular-shaped MIS diodes with
200-Mm diameter and MISHEMTs with a 1Mm gate length were
fabricated and characterized. Compared with the 3-nm barrier
AIN/GaN schottky diodes in [3], the 7 nm and 3 nm In - situ SiNx
has effectively reduced the reverse leakage current at -5 V bias by
about 7 and 4 orders of rnagnitude, respectively. The leakage current
density of the MIS diode with 7-nm In - situ SiN
x
was on the order
of 10-
7
A/cm
2
, remarkably lower than that of the similar structures
240
using other dielectrics [2-5]. The trap density of the MIS structures
was extracted to be 1.8xlO"
2
cm-
2
(D
jdi
.,) and 2.2x10" cm-
2
(D hy"') by investigating the frequency dispersion and hysteresis of the
C- V curves, respectively [7]. According to the TLM measurement, the
sheet resistances of the two sarnplcs were around 1300 O/sq (with 7
nm In - situ SiN
x
) and 4200 O/sq (with 3 nm In - situ SiN
x
),
respectively, which were about one order lower than that of the
1.5-nm barrier AIN/GaN HEMT sample without surface passivation
[4]. The improvement is due to reduced AIN relaxation, increased
carrier concentration and surface protection effects of the In - situ
SiNx layer. The fabricated MISHEMTs exhibited a peak
transconductance of 248 rnS/mm and a maximum drain current
density of 730 mA/mm. The gate pulsed I-V measurement showed
negligible current degradation, indicating good surface passivation
effect of the In - situ SiNx layer as well. In conclusion, In - situ
SiNx deposited by MOCVD is a promising candidate as the gate
dielectric for the ultra-thin barrier AIN/GaN MISHEMTs. [1] Y. Cao,
et al., Int. Semiconductor Device Research Symp. 1, pp. 407-408,
(2007). [2J M. Higashiwaki, et aI., IEEE Electron Device Lett., 27, 9,
pp. 719-721, (2006). [3J Tongde Huang, eta!., IEEE Electron Device
Lett., 33, 2, pp. 212-214, (2012). [4J Tongde Huang, et al., IEEE
Electron Device Lett., 33, 8, pp. 1123-1125, (2012). [5J D. A. Deen,
et al., Electron. Lett., 45, pp. 423-424, (2009). [6] E. Cho, et at., J.
Vac. Sci. Technol. 13 27, pp. 2079-2083, (2009). [7J M. Fagerlind, et aI.,
J. Appl. Phys., 108, pp. 014508-6, (2010).
2:45 PM Dl.05
A Novel High Performance AIGaN/GaN Based
Enhancement-Mode Metal-Oxide-Semiconduetor High
Electron Mobility Transistor. Raphael Brown, Abdullah
Al-Khalidi, Douglas MacFarlane, Sanna Taking and Edward Wasige;
School of Engineering, University of Glasgow, Glasgow, United
Kingdorn.
This paper presents a new enhancement-mode (E-mode) Gallinm
Nitride (GaN) based high electron mobility transistor (HEMT)
employing an Aluminium Gallium Nitride (AIGaN) barrier. The
AIGaN barrier layer of AI-content 25% is only 3nrn thick. The device
employs 20nm of silicon dioxide (SiO_2) deposited by plasma
enhanced chemical vapour deposition (PECVD) as the gate dielectric,
and relies on an induced two dimensional electron gas (2DEG) for
operation. Simple gate wrap-around devices were fabricated and
characterised. The devices dClnonstrated positive threshold voltages of
+2V or higher, very Iowan-resistances of < 0.27 mO(cm)2 and very
high drain currents of more than 620 mA/mm. A device employing 20
nm SiO_2 demonstrated a threshold voltage of +2 V, very low
on-resistance of < 0.35 mO(cm)2 and very high maximum drain
current of > 550 rnA/nnn, while a device ernploying 10 rnn SiO_2
demonstrated a threshold voltage of +3 V, very Iowan-resistance of <
0.27 mn(cm)2 and very high maximum drain current of> 620
mA/mm. The achieved results indicate that the proposed device
technology is prornising for realising future power electronic devices.
3:30 PM *Dl.06
Technologies for III-N Heterogeneous Mixed-signal
Electronics. Kevin Chen, Hong Kong University of Science and
Technology, Kowloon, Hong Kong.
Gallium nitride and its related group III-nitride (III-N) materials,
especially in the form of heterostructures, are being established as the
key materials for electronic devices that can deliver superior
perforrnance than their Si or GaAs counterparts in rnission-critical
applications such as high-frequency power amplifiers, high voltage
power switches and rectifiers. Major research and development effort
is being focused on III-N device technologies that can deliver high
performance such as high power density at high frequencies, high
breakdown voltage and low on-resistance. In practical applications,
these high-performance devices need to be controlled and/or
protected by peripheral analog/digital mixed-signal electronics to
achieve system-level controllability, robustness and reliability. While
the near-term solutions with quick design turn-around time would be
based on separate rnixed-signal ICs using the rnainstrearn silicon
technology, heterogeneous integration of the III-N mixed-signal
functional blocks on III-N wafers would ultimately deliver
system-on-chip solution that promise higher performance, improved
reliability and rnore cornpact systerns [1, 2]. An irnportant benefit of
III-N mixed-signal IC technology is that it allows us to take full
advantage of III-N devices' high-temperature operating capability
which can lead to significantly simplified cooling systems, but would
be otherwise compromised if Si IC's are used. III-N heterostructures,
enhanced by strong spontaneous and piezoelectric polarization,
provide the most mature platform for implementing III-N electronic
devices. In this paper, recent development in device technology will be
presented to demonstrate that III-N heterostructures are capable of
delivering a robust platform on which a wide range of peripheral
devices (e.g. depletion-/enhance-rnode FETs, diodes and resistors,
etc.) can be monolithically integrated with high-performance III-N
devices. Device and circuit examples will be discussed to demonstrate
the benefits provided by III-N mixed-signal electronics. [1] W. Chen,
K. Y. Wong, and K. J. Chen, IEEE Electron Device Lett., 30, 430
(2009). [2J K. -Yo Wong, W. Chen, X. Liu, C. Zhou, and K. J. Chen,
Phys. Sta. Sol. (b), 247, No.7, pp. 1732-1734, 2010.
4:00 PM Dl.07
MIT Virtual Source GaNFET - High Voltage (MVSG-HV)
Model: A Physics Based Compact Model for HV-GaN
HEMTs. Ujwal Radhakrishna", Tadahiro Imada
2
,1, Tomas Palacios"
and Dimitri Antoniadis
1
; 1 Computer Science and Electrical
Engineering, MIT, Cambridge, Massachusetts; 2Fujitsu Laboratories
Ltd., Atsugi City, 10-1 Morinosato-Wakarniya, Japan.
Introduction: GaN HEMTs are poised to take the lead in power
conversion markets such as SMPS, DC-DC convertors, power ICs etc.
[1]. To enable meaningful circuit design, it becomes necessary to have
accurate physics-based cornpact device rnodels for this ernerging
technology. Several GaN HEMT compact models are available in
literature [2], but most of these models are not physics-based [3J-[4].
In this work, a physics-based model for HV-GaN HEMTs is proposed.
The model is scalable and captures static and dynamic device
behavior through self-consistent current and charge expressions. In
addition, access regions, which play an important role in determining
the blocking reverse voltage and device linearity, are modeled as
implicit-gated transistors in series with the intrinsic transistor. The
model requires a small number of parameters with straightforward
physical rneanings. The new rnodel is validated against DC-IV and
S-parameter measurements of industry devices. Intrinsic transistor:
The MVSG-HV intrinsic transistor model extends a previous
short-channel GaN FET model [5] that was based on quasi-ballistic
transport to the drift-diffusion transport by considering the
contribution of the drain-end charge in addition to the charge at the
virtual-source by a suitably adapted formulation. Drain-end charge
modulation by pinch-off and velocity saturation is achieved smoothly
as function of gate length, and the resulting current has self-consistent
linear- to saturation-region transition. Terrninal charges are
self-consistently solved by ernploying current continuity and
Ward-Dutton charge partitioning. The MVSG-HV model formulation
resembles the EKV model [6] in the long-channel limit and the
MIT- VS model [5] in the short-channel limit. Access region: The
access regions are rnodeled as transistors sirnilar to the intrinsic
device. The key difference is that there is no physical gate in these
regions and an implicit-gate-overdrive (Vgi - Vti) is linked to the
sheet resistance (Rsh) and mobility (/-,) as (Vgi -Vti) = 1/ (Rsh Cgi
/-,). The implicit-gate capacitance (Cgi) which is a fitting parameter,
is the only additional pararneter needed for rnodeling the access
regions. This transistor model captures depletion of 2DEG in the
source access region at the gate end and depletion in the drain access
region at the drain end as transistor pinch-off. Pinch-off and velocity
saturation in access regions is responsible for their non-linear
behavior, which is the reason for device non-linearity [7J. Both
potential and field continuity is ensured between different regions of
the device using the quasi-2D Poisson solution, Results: The model is
calibrated to experimental devices supplied by Fujitsu Laboratories
Ltd. The access region rnodel is tested by cornparison with ungated
transrnission line rnethod structures (TLMs). The irnplicit-gated
transistor model gives very good match to wide range of TLM lengths
with the same set of parameters, The model scalability is tested by
comparing with transistors of different gate-drain spacing (Lgd). In
addition to DC rneasurernents, gate capacitance derived fronl
S-parameter measurements show good match with the model results.
Conclusions: In this work, a new physics-based compact model for
GaN HEMTs is proposed, The model captures physics in different
regions of the device and is able to replicate both static and dynamic
behavior of experirnental devices. The rnodel is irnplernented in
Verilog-A and is suitable for circuit simulations. References [1J U. K.
Mishra et,al, Proc. of IEEE, 90(6): 1022-1031, Jun. 2002, [2] L,
Dunleavy et. aI, Microwave Mag., IEEE, vol. 11, No.6, pp. 82-96,
Oct. 2010. [3J 1. Angelov et.al, Proc. APM Conf., pp. 279-282, Dec.
2006. [4] W. R. Curtice ct. ai, IEEE-TMTT, vol. 33, pp. 1383-1393,
Dec. 1985 [5J U. Radhakrishna et.al, IEDM, pp. 13.6.1-13.6.4, Dec.
2012, [6] M, Bucher et ai, LEG, EPFL, 1997, [7] K. Shinohara et. aI,
IEDM, pp. 27.2.1-27.2.4, Dec. 2012.
4:15 PM Dl.08
Ultra-Low Leakage AIGaN/GaN Schottky Diodes Based on
3D Anode Structure. Elison Matioli, Bin Lu and Tomas Palacios;
Electrical Engineering and Computer Science, Massachusetts Institute
of Technology, Carnbridge, Massachusetts.
The development of GaN Schottky-barrier diodes (SBDs) allows the
combination of fast switching-speed of majority carrier devices, with
the large breakdown field, high electron-mobility and capability of
high ternperature operation of III-nitride serniconductors. These
devices would enable higher efficiency power switches with much
smaller si7,e compared to Silicon devices. Planar AIGaN/GaN SBDs
241
present large turn-on voltage and on-resistance, since electrons from
the two-dimensional-elect ron-gas (2DEG) in the AIGaN/GaN
hctcrostructurc nccd to ovcrCOInc thc AIGaN/GaN intcrfacc barricr
and flow through the highly resistive AIGaN layer. The AIGaN barrier
also limits the control of the Schottky anode over electrons in the
2DEG, resulting in large reverse leakage current. These are major
limitations of conventional AIGaN/GaN-based SBDs for efficient
powcr circuits. To addrcss thcsc problcIns, wc dcvclopcd a novel SI3D
structure based on a three-dimensional (3D) nanopatterned anode.
The patterned anode consisted of a series of periodically-spaced
pillars aligned parallel to the electron flow. The pillars were defined
by trcnchcs ctchcd in bctwccn thcIn, far dccpcr than thc AIGaN
barricr. Thc purposc of thc pattcrncd anodc is twofold: iInprovc
forward-bias characteristics and reduce reverse leakage current. In
forward-bias, the pillar sidewalls form close-to-ideal GaN Schottky
junctions directly to the 2DEG to improve turn-on characteristics.
Thc Inain function of thc top barricr is to inducc a largc dcnsity of
electrons with high mobility in the 2DEG. To reduce the leakage
current in reverse bias, a section of the patterned anode, between the
Schottky junction and the cathode, was covered with oxide to form a
structured metal-oxide-semiconductor region. This structure provided
an clcctrostatic barricr for elcctrons, offcring a bcttcr gcoInctry to
deplete the electrons in the channel under reverse bias compared to
conventional planar field-plate structures, which drastically reduced
reverse leakage current. In this work, we demonstrate ultra-low
leakage current AIGaN/GaN SBDs based on 3D anode contact. By
optiInizing thc diIncnsions of thc pcriodic trcnchcs, wc dCInonstratc
SBDs with 4 orders of magnitude lower reverse leakage current
compared to planar devices, down to 260 pA/mm (260 nA/cm2), with
a breakdown voltage of 130 V (oxide breakdown) for an
anode-to-cathode distance of 1.5 Mm. These SBDs presented turn-on
voltagc of 0.85 V, ON-resistance of 5.96 [lnlIn and ideality factor of
1.27. We also present the physics behind this device operation as well
as the impact of its different parameters, such as the width of pillars
and length of the electrostatic barrier. By structuring the anode
contact, wc show that thc forward and rcvcrsc- bias charactcristics of
SI3Ds can bc dccouplcd, allowing thcir scparatc optiInization, which
offers a pathway for future low-leakage, fast-switching power SBDs.
This work was partially funded by ONR PECASE program monitored
by Dr. Paul Maki
4:30 PM Dl.09
Normally-off GaN MOS-HEMT with High Threshold Voltage,
No Current Collapse and High-Temperature Stability.
Yuhao Zhang, Min Sun, Sameer .1 . .1oglekar, Daniel Piedra, Tatsuya
FujishiIna and TOInas Palacios; DcpartIncnt of Elcctrical Enginccring
and Computer Science, Massachusetts Institute of Technology,
Cambridge, Massachusetts.
AIGaN/GaN high-electron-mobility transistors (HEMTs) have great
potcntial for thc ncxt gcncration of powcr elcctronics.
Enhancement-mode (E-mode) metal-oxide-semiconductor (MOS)
HEMTs with a threshold voltage (Vth) 3 V are highly desirable for
fail-safe operation. Extensive studies have shown that fluorine plasma
trcatIncnt is an cffcctivc Incthod to achicvc HEMTs with a V th rv IV
[1], but very few reports have demonstrated fluorinated MOS-HEMTs
with high V th, and no studies on their pulse behavior and thermal
stability have been reported. In this work, we demonstrate E-mode
fluorinated MOS-HEMTs with a V th higher than 3 V, no current
collapse and long-term thermal stability at 250 "C. The MOS-HEMTs
in our work have an integrated dual-gate structure [2]. The E-gate
region was formed by CF
4
plasma at an ECR power of 150 Wand an
RF power of 20 W for 150 s, which etched the GaN cap and top
AIGaN. An Ab03 gate oxide with different thickness of 8, 15,
20 and 25 nIn was thcn dcpositcd by atoInic laycr dcposition. Aftcr
gate deposition, the samples were annealed at 400 0 C for 5 min in N 2
ambient. The output characteristics of standard and fluorinated
MOS-HEMTs demonstrated that the fluorine plasma treatment
induces only a small degradation in the on-resistance and maximum
currcnt. Thc transfcr charactcristics of fluorinatcd MOS-HEMTs
reveal a V th higher than 3 V and a gate leakage level of 10-
7
mA/mm up to V9,=10 V. The V th of fluorinated MOS-HEMTs were
found to increase with increasing oxide thickness. This is due to the
cxistcncc of ncgativc fluoridc-induccd bulk chargc in thc oxidc,
revealed by our modeling work. No current collapse was found under
500 ns pulsed current measurement of fluorinated MOS-HEMTs
without any post-gate passivation. Moreover, a smaller V th hysteresis
V) was observed for fluorinated MOS capacitors compared
with standard MaS capacitors (!"'V0.5 V) in thc capacitancc-voltagc
measurements. This is probably due to the fluorine passivation of
oxide/ AIGaN interface states and the fluoride-induced conduction
bending that increases the barrier for electron trapping.
High-temperature measurements reveal that the V th of fluorinated
MOS-HEMTs is unchanged up to at least 250 ac. Moreover, the
device V th is unchanged in continuous operation at 250 DC for 24
hours. In conclusion, E-mode fluorinated MOS-HEMTs were
systematically studied. A high V th (>3 V) increasing with gate oxide
thickness, a very small V th hysteresis, no current collapse and
high-temperature stability (250C) have been presented for
fluorinatcd MOS-HEMTs. This work dCInonstratcs that fluorinc ions
diffused into the gate oxide form a promising technique in fabricating
high-performance E-mode MOS-HEMTs. We acknowledge the partial
support of the DARPA MPC program and the MIT GaN Energy
Initiative. [1] Y. Cai et aI., IEEE Electron. Device Lett. 26, 435
(2005). [2] 13. Lu et aI., IEEE Electron. Device Lett. 31, 990 (2010).
4:45 PM Dl.I0
GaN Varactors with Insulated Electrodes for Microwave
Control ICs. Mikhail Gacvski
1
, Jianyu Dcng
1
, RCInis Gaska
1
,
Michacl Shur
2
, Faisal Jahan
3
and Grigory SiInin
3
; lScnsor Elcctronic
Technology, Inc, Columbia, South Carolina; 2 The Rensselaer
Polytechnic Institute, Troy, New York; 3University of South Carolina,
ColuInbia, South Carolina.
Capacitively coupled contacts (C3) varactors over III-Nitride have
demonstrated state-of-the-art performance in wide frequency range
from 2 to 20 RF losses are below -ldB; RF isolation is better
than -30 dI3. RF and high powcr charactcristics of varactor bascd
switches can be further improved using higher bias voltages (>30V),
however, this leads to substantial increase of leakage current through
the Schottky electrodes. In the present work, C3 varactor with
isolated electrodes was studied. The effect of thin isolation layer on
varactor pcrforrnancc has bccn invcstigatcd. It was shown that
electrode isolation leads to the several order of magnitude decreased
leakage current as compared to Schottky electrodes. RF characteristics
of devices with electrode dielectrics using Al203 and SiNx dielectric
layers with various thicknesses are compared with Schottky type
varactors. Thc studics show that C3 varactors fabricatcd using atoInic
layer deposited Al203 films demonstrate superior RF characteristics.
SESSION DPl: Poster Session: Electrical Devices
Monday Evening, August 26, 2013
6:00 PM
Potomac C/D & 1-6
DPl.Ol Linas Ardaravicius
1
, Oleg Kiprijanovic
1
, Juozapas Liberis
1
,
Emilis Sermuksnis
1
, Arvydas Matulionis
1
, Romualdo A. Ferreyra
2
,
Fan Zhang
2
, Vitaliy Avrutin
2
, UInit Ozgur
2
, HacEs Morkoc
2
and
High-Field Drift Velocity in Camelback Channels For HFETs
Kestutis Jarasiunas
3
; lSemiconductor Physics Institute, Center for
Physical Sciences and Technology, Vilnius, Lithuania; 2Electrical and
COInputcr Enginccring, Virginia COInInonwcalth Univcrsity,
Richmond, Virginia; 3Institute of Applied Research, Vilnius
University, Vilnius, Lithuania.
The effect of electron density on hot-electron transport in an, from
the surface down, AlyGal-yN/ AIN/ AlxGal-xN/GaN camelback
heterostructure [1] with vertically spread quasi two-dimensional
electron density, is studied by use of nanosecond scale voltage pulses
(2 ns). The camelback channel has been formed in nominally undoped
layers of either alloy-containing AlxGal-xN/GaN or alloy-free
GaN/ AIN/GaN structures separated from the barrier layer with the
AIN spacer layer. The highest, among the reported values, electron
drift velocity of 107 cm s:1 at 160 kV cm:l was measured in the
alloy-containing camelback channel with a modest low-field electron
mobility of 1070 cm2/(Vs) and an electron density of 0.8xl013 cm:2
[2]. Although the alloy scattering limits the low-field mobility in the
alloy-containing camelback channel, the observed velocity exceeds
that in a standard single GaN-channel AIN-spacer AIGaN-barrier
heterostructure by % [3], indicating that the high-field transport
is not affcctcd by thc alloy scattcring as cxpcctcd. This largc
high-ficld drift vclocity obscrvcd for a particular elcctron dcnsity is
consistent with the resonance ultrafast decay of hot phonons resolved
in the vicinity of the LO-phonon-plasmon crossover [2]. The
alloy-free GaN/AIN/GaN camelback channel is promising for
iInprovcd low-field transport propcrtics. Whcn thc pristinc elcctron
density exceeds the resonance value, the resonance can be tuned in
with a variable negative bias applied to the gate of a heterostructure
field effect transistor (HFET). The HFET with the pristine 2DEG
density of 1.6xl013 cm:2 in the alloy-free GaN/AIN/GaN camelback
channel demonstrates the optimal frequency performance at a
relatively low gate bias of -1.75 V while single-channel HFETs
typically require higher gate bias (-2.9 V at 1.65xl013 cm:2 [4]).
Among other advantages, the ability to tune into the resonance with a
lower gate bias is potentially useful for reduced gate leakage currents.
1. .1. H. Leach, M. Wu, H. Morkoc, .1. Liberis, E. Sermuksnis, M.
Ramonas, and A. Matulionis, .1. Appl. Phys. 110, 2011 (2011). 2. L.
ArdaraviCius, O. Kiprijanovic, J. Libcris, A. Matulionis, X. Li, F.
Zhang, M. Wu, V. Avrutin, U. Ozgiir, and H. Morkoc, Semicond. Sci.
Technol. 27, 122001 (2012). 3. L. Ardaravicius, M. Ramonas, O.
Kiprijanovic, .1. Liberis, A. Matulionis, L. F. Eastman, .1. R. Shealy,
x. Chen, and Y . .1. Sun, Phys. Status Solidi A, 202, 808 (2005).4. D.
S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, IEEE
242
Electron Device Lett. 32, 1525 (2011).
DPl.02
Tapered Field Plate Employing Photoresist Reflow and
Etching Selectivity Control for AIGaN/GaN HFETs.
Young-Hwan Choi, Bongmook Lee, Edward Van Brunt, Veena Misra
and Alex Q. Huang; Electrical and Cornpntcr Engineering, North
Carolina State University, Raleigh, North Carolina.
In GaN based HFETs, a field plate (FP) structure is commonly used
to reduce the electric field concentration at the gate edge which
results in large leakage current and low breakdown voltage. A FP
which has an inclined shape is expected to effectively reduce the
electric field [1-2]. However, the slant FP [1] has been limited by a FP
length of about 0.3 ,"m and the tapered FP [2] fabricated by wet
etching process were hindered by difficulty in etch rate control. In this
paper, we propose a new tapered field plate fabricated using
photoresist (PR) reflow and etching selectivity (ES) control. A new
tapered field plate (FP) structure for attaining low leakage current
and high breakdown voltage of AIGaN/GaN heterojuction field effect
transistors (HFETs) is proposed and verified experimentally. A low
tapered angle of about 10 degrees was achieved by the new process
employing photoresist (PR) reflow during the hard bake and etching
selectivity (ES) control during the dry etching process. AIGaN/GaN
HFETs with a conventional steep FP, which has an angle of 70
degrees, were fabricated for the cOlnparison with proposed devices
with the tapered FP. The leakage current of the proposed device is
about 2 orders of magnitude less than that of the conventional device.
The proposed device maintains its breakdown voltage (BV) level
regardless of applied power, whereas the conventional device shows a
shift of BV as the applied power increases. These cxpcrirncntal results
indicate that the proposed tapered FP suppresses the electric field
concentration at the gate edge successfully and is an effective
approach to improve the blocking characteristics of GaN based
devices. References: [1] Y. Dora, A, et.al, IEEE Electron Device
Letters, vol. 27, no. 9, pp.713-715, September 2006. [2] Y. H. Choi,
et.al, Material Science Forum, vol. 615-617, pp. 971-974, March 2009
DPl.03
Impact of Variation Silicon Nitride Passivation Thickness on
AIGaN/AIN/GaN and GaN/AIGaN/GaN Device
Performance. H. Jackson
,
,2, J. Petrosky2, R. Hengehold
2
and Z.
Fang
3
; 1 Materials and Manufacturing Directorate, Air Force Research
Laboratory, Wright Patterson AFB, Ohio; 2Department of
Engineering Physics, Air Force Institute of Technology, Wright
Patterson AFB, Ohio; 3Semiconductor Research Center, Wright State
University, Dayton, Ohio.
Silicon nitride passivation (Si
3
N4 ) on AIGaN
GaN heterojunction devices can iInprove perforrnance by reducing
electron traps at the surface. In this study, the effects of passivation
layer thickness were investigated at various thicknesses (0, 20, 50 and
120 nanometers) on bare epilayer AIGaN
GaN structures with either an AIN nucleation layer or a GaN cap.
Hall systern Ineasurernents were used to observe changes in carrier
concentration as a function silicon nitride thickness. Carrier scattering
mechanisms are analyzed both with and without Si
3
N
4
Capacitance
voltage measurements were carried out to give information about the
surface donor states and the Si3N4 charge at the interface. A
monatomic decrease in saturation capacitance with increasing Si3N4
thickness was observed for the Si3 N4 /AIGaN/AIN/GaN structure.
Gate current measurements were done to examine the effect of Si3 N4
on the gate leakage current and thus on device performance.
DPl.04
Comparison of Thermoelectric Properties of GaN and ZnO
Samples. Bahadir Kucukgok
'
, Baozhu Wang
2
, Qinyue He
'
, Andrew
G. Melton
'
, Na Lu
3
and Ian T. Ferguson
'
; 'Department of Electrical
and Computer Engineering, University of North Carolina at
Charlotte, 9201 University City Blvd., Charlotte, NC 28223, USA,
Charlotte, North Carolina; 2College of Information Science and
Engineering, Hebei University of Science and Technology, 70 Yuhua
East Rd., Shijiazhuang, Hebei 050018, China., Hebei, China;
3Department of Engineering Technology, University of North Carolina
at Charlotte, 9201 University City Blvd., Charlotte, NC 28223, USA,
Charlotte, North Carolina.
In this paper, room temperature thermoelectric properties (TE) of
wide bandgap thin filrns, GaN and ZnO, grown by Metal Organic
Vapor Deposition (MOCVD) arc studied. Bulk GaN is also
incorporated with epitaxy films to make comparison. GaN and ZnO
materials have superior electrical performance and chemical stability
at high temperatures and are currently found in many commercial
applications, such as, photovoltaic, TE generators, solid-state lighting,
and gas sensors. Since there are not many semiconductor materials
that can operate effectively at high temperatures, wide bandgap
materials like GaN and ZnO would be promising offer for a traditional
semiconductor solution for high temperatures thermoelectric power
generation. In order to understand their TE properties, we
systernatically cornpared and characterized GaN and ZnO thin filrns.
The focus of this study is to investigate TE properties while varying
doping concentrations. The common observed trends, a decrease in
Seebeck coefficients with the increase of carrier concentration for
epitaxial GaN, bulk GaN, and ZnO, was observed. This phenomenon
is attributed to the inverse proportion between seebeck coefficient and
carrier concentration in the Mott-Jones relation to simple transport
models. The Seebeck coefficients of ZnO samples are found to be
larger than those of epitaxial GaN and bulk GaN samples in the
sirnilar carrier density. Power factor of ZnO and bulk GaN showed
saIne trend whereas epitaxial GaN sarnple exhibited high power factor
of4.72xl0-4 W/mK2.
DPl.05
Modeling and Measurement of Gate Leakage Current in
Metal/ AI
2
0
3
/ GaN/ AIGaN/ GaN Capacitors. Shlomo Mehari I,
E. Yalon
'
, A. Gavrilov
'
, D. Mistele
'
, G. Bahir
'
, M. Eizenberg
2
and
D. Ritter
'
; 'Electrical Engineering, Technion-Israel Institute of
Technology, Haifa, Israel; 2 Materials Science and Engineering,
Technion- Israel Institute of Technology, Haifa, Israel.
Insertion of a dielectric layer between the metal gate of the transistor
and the semiconductor helps reduce gate current. Here, we calculate
the expected gate current due to field ernission through the dielectric
layer, and compare the results to experimental data for both nickel
and titanium gate electrodes on an AI20 3 /HFET structure. The
AIGaN/GaN HFET structure was grown by MOCVD on SiC
substrate by IQE. The layer structure consisted of thin AIN
nucleation layer followed by 1.8 rLIn unintentionally doped GaN, 1 nrn
AIN and 15 nm Alo.25Gao.75N barrier and 3 nm thick GaN cap layer.
The 20 nm thick Al
2
0
3
layer was deposited on the GaN surface by
thermal atomic layer deposition (ALD) using tri-methyl-aluminum
(TMA) and H20 as precursors. Gate electrodes were Ti/Au and
Nil Au, and a Til Al Inetal stack served as the ohrnic contact. Previous
attempts to calculate the gate leakage were based upon the Fowler
Nordheim equation, which requires fitting of two parameters, and is
suitable for metal insulator metal structures, but not for the
cornplicated band diagraIn of the actual device. The questions we wish
to answer are a. whether the leakage current is deterrnined by the
field emisson through the AI
2
0
3
layer, or whether trap assisted
tunneling dominates, and b. how the GaN cap layer, surface charges,
and surface states affect the leakage current. An exact calculation
should include tunneling froIll localized states in the GaN quanturn
well that is formed between the dielectric layer and the AIGaN
barrier, and tunneling from extended states above the quantum well.
At this point, we have only considered extended states tunneling, and
used the lower limit of integration, Ernin , in the Tsu-Esaki expression
as a fitting pararneter [1]. Good fit to the rneasured data was obtained
for Em;n values slightly lower than the AIGaN conduction band. The
band diagram was obtained by simulation using ATLAS SILVACO
software, assuming an ideal structure with fixed donor charge at the
surface [2]. The surface fixed charge density was obtained by fitting
the experiInental and sirnulated threshold voltage for accuInulation of
the electrons in the 2DEG. Although more work is required to obtain
an exact calculation of the tunneling current, we believe our results
already indicate that gate leakage is only due to field emission through
the Ah03 layer. [1] R. Tsu and L. Esaki, Appl. Phys. Lett., 22, 562
(1973). [2] J. P. Ibbetson, P. T. Fini, K. D. Ness, S. P. DenBaars, J. S.
Speck, and U. K. Mishra Appl. Phys. Lett., 77, 250 (2000).
DPl.06
Ohmic Conduction in Metal/Graphene/ AIGaN/GaN
Structure. Pil Sung Park
'
, Kongara M. Reddy 2, Digbijoy N. Nath
'
,
Zhichao Yang
l
, Nitin P. Padture
3
and Siddharth Rajanl,2; lElectrical
and Computer Engineering, The Ohio State University, Columbus,
Ohio; 2Material Science and Engineering, The Ohio State University,
Columbus, Ohio; 3School of Engineering, Brown University,
Providence, Rhode Island.
We report a new method for making Ohmic contact to 2-D electron
gas (2DEG) in AIGaN/GaN high electron-mobility transistors
(HEMTs) using Cr/Graphene layer. We find that while Cr or
graphene separately behave as Schottky contact on AIGaN, rnetal
(Cr)/graphene on AIGaN/GaN structure showed Ohmic behavior with
a resistivity of 2 mn-cm2. Ohmic contacts to AIGaN/GaN
heterostructures require highly tailored multi-layer metallization
followed by a high temperature annealing process due to the large
barrier height associated with the metal/AIGaN/GaN interface. Such
Ohmic contacts limit reproducibility, reliability and scalability of
GaN-based transistor devices. In addition, the high-temperature
annealing steps preclude the use of some advanced fabrication
approaches, such as gate-first, self-aligned processing. While Ohrnic
contact re-growth and ion-irnplantation provide an alternative, these
approaches also add to the complexity of the processing.
Cr/graphene/AIGaN/GaN junction diodes were fabricated on an
243
AIO.28GaO.72N/GaN structure. Single layer graphene was synthesized
on Cu foil using chemical-vapor-deposition (CVD) and transferred to
an AIGaN/GaN wafer prior to the processing. Cr was deposited OIl
top of the graphene to create a Cr/Graphene/AIGaN/GaN structure.
For comparison, Cr/AIGaN/GaN diodes were also co-processed on the
same wafer by removing graphene layer using 02 plasma.
Cr / AIGaN/ GaN diodes had typical rectifying Schottky characteristics
as expected. In the case of Cr/Graphene/AIGaN/GaN, the I-V
characteristics were found to be Ohmic. The absence of a threshold
voltage for current in forward- and reverse-bias conditions indicates
that electrons can flow in either direction without being blocked by
hctcrojunction or electrostatic barriers. The absence of electrostatic
barrier can be explained through a zero field in the AIGaN due to
surface Femi level pinning by the Cr/graphene. However, the height
and thickness of the AIGaN barrier are expected to block both
tunneling and thermionic emission. Weak temperature dependence
observed in the range 77 to 300 K precludes thcrrnionic crnission or
trap-assisted hopping as possible carrier-transport mechanisms, and
the current density is higher than theoretical estimates of tunneling.
We therefore propose that percolation transport through Ga-rich
regions of the random AIGaN barrier is responsible for the Ohmic
nature of this contact. This new usc of graphene offers a reliable
method for making Ohmic contacts to AIGaN/GaN heterostructures,
circumventing complex additional processing steps involving high
temperatures. These results could have important implications for the
fabrication and manufacturing of AIGaN/GaN-based microelectronic
and optoelectronic devices/sensors of the future. We acknowledge
support from NSF ECCS-0925529.
DPl.07
Comparison of the Physical, Chemical, and Electrical
Properties of ALD AI 2 0
3
on c- and m-Plane GaN.
Darning Wei
1
, Tashfin Hossain
1
, Neeraj Nepa1
2
, Nelson Y. Garces
2
,
Jennifer K. Hite
2
, Harry M. Meyer
3
, Charles R. Eddy 2 and James H.
Edgar
1
; lChemical Engineering, Kansas State University, Manhattan,
Kansas; 2Electronics Science and Technology Division, Naval Research
Laboratory, Washington D.C., District of Colurnbia; 3Material Science
and Technology Division, Oak Ridge National Laboratory, Oak Ridge,
Tennessee.
GaN is employed for power electronics because of its ability to operate
at high ternperatures, high frequencies, and high power. For instance,
when used in conjunction with AIGaN, high frequencies can be
achieved in high electron mobility transistors (HEMTs) by the
carriers found in the spontaneously formed two dimensional electron
gas (2DEG) at the AIGaN/GaN interface in the c-plane. These
devices have a negative threshold voltage (norrnally-on transistor).
For power applications, normally-off transistors are preferred for
fail-safe operations and to minimize energy consumption. As such,
m-plane AIGaN/GaN heterostructures are promising to make the
E-mode (normally-off) transistors due to the lack of a high-density,
polarization induced 2DEG , but the perforrnance of this Tn-plane
heterostructure remains largely unexplored. Research is needed to
optimize the device. This study compares the physical, chemical and
electrical properties of Al 2 0
3
thin films deposited on gallium polar c-
and nonpolar Tn-plane GaN substrates by atornic layer deposition
(ALD). Correlations were sought between the filrn structure,
composition, and electrical properties. The thickness of the films were
19.2nm on the Si witness sample determined by spectroscopic
Ellipsometry. The gate dielectric was slightly aluminum-rich
(Al:O=1:1.3) as rneasured froHI x-ray photoelectron spectroscopy
(XPS) depth profile, and the interface carbon concentration was lower
for alumina deposited on c-plane GaN than that of on m-GaN.
Similar surface morphology was observed, but a smoother surface was
produced on the c-plane GaN as determined by atomic force
microscopy (AFM). Circular capacitors (50-300 lun diameter) with
Ni/Au (20/100 nm) metal contacts on top of the oxide were created
by standard photolithography and e-beam evaporation methods to
form metal oxide semiconductor capacitors (MOSCAPs). The alumina
deposited on c-plane GaN showed less hysteresis (0.038V) than
m-plane GaN (0.61V) in capacitance-voltage (CV) characteristics,
which are consistent with the better quality of this dielectric as
evidenced by negligible carbon contamination and smooth oxide
surface. These results demonstrate the promising potential of ALD
Ab03 on c-plane GaN, but further optimization of ALD is required
to realize the best properties of A12 0
3
on Tn-plane.
DPl.08
AIGaN/GaN-on-Si Rectifier with a Combined Anode of
Recessed and Non-Recessed Schottky Contacts.
Narncheol Jeon
1
, Hojin Ryu
1
, Woojin Choi
1
, Ho-Young Cha
2
and
Kwang-Seok Seo
l
; lDepartment of Electrical Engineering and
Computer Science, Seoul National University, Seoul, Korea, Republic
of; 2 School of Electronic and Electrical Engineering, Hongik
University, Seoul, Korea, Republic of.
A novel AIGaN/GaN-on-Si rectifier with a combined anode of recessed
and non-recessed Schottky contacts has been proposed to improve the
forward characteristics without reverse breakdown voltage
degradation. The epitaxial wafer structure used for experirnent
consisted of a 4-nm un-doped-GaN capping layer, a 20-nm
undoped-AIO.23GaO.77N barrier, a 1-nm AIN spacer, a 1.7-ltm
undoped-GaN buffer, and an undoped GaN/AIN transition layers on
an N-type Si (111) substrate. Ohmic contact was first formed by
Si/Ti/ AI/Mo/Au (=5/20/80/35/50 mn) and mesa isolation was
followed. Next, anode region was fully recessed under the 2DEG
channel to define a recessed Schottky contact. An additional
non-recessed Schottky metal was evaporated. Finally, a 200-nm-thick
SiNx filrn was deposited at 250 0 C for surface passivation. The
forward turn-on voltage of the non-recessed and recessed Schottky
barrier diodes with an anode-to-cathode distance of 15 J.tm were 1.33
and 0.55 V defined at the current density of 10 mA/mm, respectively.
In comparison with a non-recessed diode, forward current density of a
recessed diode was increased frorn 38 rnA/rnrn to 225 rnA/rnrn at 1.5
V. Low turn-on voltage and high forward current in a recessed diode
are due to the improved ideality factor and lowered Schottky barrier
height. The ideality factors of 1.65 and 1.29 and Schottky barrier
heights of 0.91 eV and 0.67 eV are extracted for non-recessed and
recessed diodes. However, there arc sorne drawbacks in recessed
diodes. First, the on-resistance of recessed diodes is higher than
non-recessed diodes, because most of the currents are flowing through
the interface between 2DEG and Schottky metal. Second, recessed
diodes show large leakage current compared with non-recessed diodes.
In this paper, we propose a Schottky barrier diode with a cornbined
anode which has a benefit of low turn-on voltage and low leakage
current without sacrificing the on-resistance. The turn-on voltage of a
proposed diode was 0.54 V which is almost identical with a recessed
diode. Forward current density of a proposed diode was increased
frorn 502 rnA/Hnn to 615 rnA/rnrn at 3 V cornpared with a recessed
diode. The specific on-resistance at 2.5 V of non-recessed, recessed,
and proposed diodes were 1.8, 2.8, 1.9 mn-cm2, respectively. Because
the electrons can also flow into the non-recessed Schottky regions in a
proposed diode at the forward bias over the turn-on voltage of the
non-recessed Schottky contact, specific on-resistance can be reduced.
The typical anode leakage current at -100 V of non-recessed, recessed,
and proposed diodes were 4.4, 39.2, and 5.5 ItA/mm, respectively.
Reverse breakdown voltages of the diodes with non-recessed, recessed,
and cornbined anode were 718, 802, 760 V, respectively. Capacitance
at 0 V of non-recessed, recessed, and proposed diodes were 64, 3, and
14 pF/mm, respectively.
DPl.09
Trap States in AIGaN/GaN Based PolFETs by C-V
Characterizations. Fang YuLong, Feng Zhihong, Yin Jiayun, Sheng
Baicheng, Wang Yuangang and Cai Shujun; Science and Technology
on ASIC Laboratory, Hebei Semiconductor Research Institute,
Shijiazhuang, China.
As one of the main concerns in semiconductors, especially for the
immature material system like III-nitrides and the heterostructures
based, the trapping effects in AIGaN/GaN HFETs have been
intensively studied. However, for the graded AIGaN/GaN PolFET
herterostructures, the extensive research of trap behaviors is still
lacking. This paper will focus on the evaluations of trap effects in
PolFETs by the frequency dependent C- V measurements, and the
results are compared with those from the AIGaN/GaN HFETs based
on the abrupt junctions. The rnaterial structure of PolFET sarnple
consists of a 2ltm unintentionally doped (UID) GaN, followed by a 70
nm channel from GaN graded to AIO.35GaO.65N. A conventional
HFET material was also prepared for comparison, and the structure
consists of a 20nm AIO.28GaO.72N layer on the same 2ltm UID GaN
beneath as the PolFET sarnple. The parallel capacitance and
conductance of the capacitors were measured as a function of
frequency at different bias voltages, as in figure1. For the HFET
sample, a peak value of the Dit, about 2.21E+12 cm-2eV-1, appears
in the vicinity of the pinch-off voltage, while there is no obvious Dit
peak in the PolFET across the graded layer, shown in figure2. For the
HFET sample, a Dit peak in the AIGaN/GaN heterojunction mainly
results from the fragile abrupt hetero-interface, while for the PoIFET,
the abrupt heterostructure and fragile interface is absent, hence no
obvious trap aggregation. The tirne constant of the trap state versus
the bias voltage evaluated for these two samples is shown in figure3.
Similarly with the trap behaviors in HFETs, the PolFET sample
demonstrates an exponential Tit-bias dependency across the graded
AIGaN layer, indicating interface characteristics. The result is that
the tirne constants in PolFET decreased gradually frorn about 2.7E-4
s at bias of -12V to about 1.4E-5 s at -4V, and the gradient is about
3.2E-5 sV-1, while the change in HFET is much sharper, from about
9.95E-4 s at bias of -4.3V to about 2.4E-5 at -3.8V,with a gradient of
1.6E-3 sV-1. The gradual change of time constants versus the bias in
PolFET partly reflects the sparseness of trap geornetry distributions,
while the traps accumulation is particularly serious in the
AIGaN/GaN abrupt junction interface of HFET.
244
DPl.I0
Characterization and Control of MOS Interface States in
GaN-based MOS-HEMTs Using AI2 0
3
Gate Insulator.
Yujin Hori
1
, Zenji Yatabe
1
and Tamotsli Hashizurne
1
,2; lRCIQE,
Hokkaido University, Sapporo, Hokkaido, Japan; 2JST-CREST,
Tokyo, Japan.
Ab03 is a promising gate insulator for GaN-based MOS-HEMTs. To
obtain operational stability and reliability in MOS-HEMTs, a low
electronic state density at the MOS interface is necessary. However, it
is difficult to evaluate state densities at the oxide/semiconductor
interface of the MOS-HEMTs having two or more interfaces. In this
paper, we have characterized MOS interface states and electrical
properties of AI2 0
3
/AIGaN/GaN MOS-HEMTs. We started the
fabrication process with the deposition of SiN as a surface protection
layer. Ti/ AI/Ti/ Au source and drain electrodes were deposited on the
AIGaN surface, followed by annealing at 800C. After etching the
SiN layer in a UHF solution, we applied an N2 0-radical trcatrncnt to
the AIGaN surface. With this process, an AlGa-oxide layer with a
thickness of 1 nm or less was formed on the AIGaN surface. A
10-nm-thick Al
2
0
3
gate insulator was then deposited by atomic layer
deposition using H2 0 and trimethylaluminum as precursors. Finally, a
gate electrode (Ni/ Au) was deposited. To evaluate the Ab 03/ AIGaN
interface states, we applied two types of Capacitance- Voltage (C- V)
methods: the photo-assisted C-V measurement for the near-midgap
states and frequency dependent C- V characteristics in the frequency
range from to for the shallow states. For the sample
without the surface trcatrncnt, the photo-assisted C- V results showed
relatively high-density interface states with a minimum density of 2 X
10
'2
cm-
2
eV-
l
around the midgap. In addition, the state density
near the conduction-band edge was estimated to be 1 - 2 X 10
13
cm-
2
eV-
l
from the frequency-dispersion in C-V data. For the
N 2 0-radical treated MOS-HEMTs, on the other hand, we confirrned
the reduction of the interface states. This is probably due to the
oxidation of the AIGaN surface. IDS - V GS measurements of the
MOS-HEMTs were also performed. For the MOS-HEMT without the
surface treatrnent, a pronounced decrease of transconductance was
observed at high gate bias range. When the gate bias is positive,
electron transfer from the AIGaN/GaN interface to the MOS interface
occurs, resulting in the channel formation at the MOS interface. In
this case. the relatively high-density MOS interface states caused the
degradation of electron rnobility, leading to the decrease of
transconductance. In comparison, the improvement of transfer
characteristics of the N 2O-radical treated MOS-HEMT in the positive
gate bias range is probably due to the reduction of MOS interface
states as confirmed in C- V analysis. The results presented indicate
that the N2 0-radical treatrnent seerns to be an effective process to
reduce the MaS interface states and improve the electrical properties
of Ab03/AIGaN/GaN MOS-HEMTs.
DPl.ll
Sublllicron-Footprint Therlllal Oxidized Ti02 Based
AIGaN/GaN MOSHEMT with Ultralow Leakage Current and
High Cutoff Frequency. Di Meng
'
, Shuxun Lin
'
, Cheng P. Wen
'
,
Maojun Wang
'
, Jinyan Wang
'
, Yilong Hao
'
, Yaohui Zhang
2
, Kei M.
Lau
3
and Wengang Wu
l
; lInstitute of Microelectronics, Peking
University, Beijing, China; 2Institute of Nano-tech and Nano-bionics,
Chinese Acaderny of Sciences, Suzhou, China; 3Departrnent of
Electrical and Electronic Engineering, HKUST, Hong Kong, China.
AIGaN/GaN metal oxide semiconductor high electron mobility
transistors (MOSHEMT) with thick (>20 nm), high-K (Ti02),
submicron-footprint (0.4 !Lm) gate dielectric are found to exhibit two
orders of magnitude in lower gate leakage current 1 nA/mm up to
+3 V applied gate bias), higher 1MAX (709 mA/mm), and higher
drain breakdown voltage, compared with Schottky barrier (SB)
HEMTs of the saIne geoInetry. The InaxiInurn extrinsic
transconductance of both the MOSHEMTs, and the SBHEMTs with
2x80 !Lm gate fingers, is measured to be 149 mS/mm. Addition of the
submicron-footprint gate oxide layer only results in a small reduction
of the current gain cutoff frequency (21 vs. 25 derived from
S-paraIneter test data) because of the high perrnittivity of the gate
dielectric. This high performance submicron-footprint high-K Ti02
MOSHEMT is highly promising for microwave power amplifier
applications in communication and radar systems.
DPl.12
Selective Deposition of Dialllond in SiC Therlllal Vias for
GaN Power HEMTs. Karl D. Hobart
'
, Eugene A. Imhoff
'
, Tatyana
I. Feygelson
'
, Marko .1. Tadjer
2

l
, Travis .1. Anderson
'
. Joshua D.
Caldwell
1
, Andrew D. Koehler
'
, Bradford 13. Pate', S.
Sandhu
3
, Vincent Gambin
3
, Gregory Lewis
3
, Ioulia Smorchkova
3
Mark Goorsky4 and Jeff McKay4; 'Naval Research Laboratory, '
Washington, District of Columbia; 2 American Society for Engineering
Education, Washington, District of Colurnbia; 3Nort hrop GrurnInan
Aerospace Systerns, Redondo Beach, California; 4University of
California Los Angeles, Los Angeles, California.
There is presently great interest in pushing the power limits of GaN
HEMTs. The high current density and high voltage capability result
in highly thermally-limited performance. High thermal conductivity
diamond substrates have been considered as an approach to lift the
power limits and many efforts are underway [e.g., 1, 2]. Other more
scalable approaches have sought to integrate diamond on the topside
and have shown reduced channel ternperature [3]. In this work we
sought to develop a highly scalable backside diamond thermal via
approach. The key advantage of diamond thermal vias is that the
stress due to the large thermal expansion mismatch associated with
diarnond and other serniconductors of interest can be rnanaged Inore
effectively than for large area diaInond substrates. Specifically, we
developed a selective diamond deposition process that largely
eliminated wafer bow. The diamond thermal vias were integrated into
GaN-on-SiC substrates by first etching backside vias through the SiC
wafer. The wafer was coated with nanodiaInond particles and a rv 1
urn diamond nucleation layer was grown conformally on the wafer
backside and in the vias by microwave plasma (MW) enhanced CVD
at 750 C [4, 5]. With a series of hard mask depositions and CMP
steps the planar diamond layer on the wafer backside
was selectively reInoved leaving diaInond in the vias only. This
reduced the bow from several hundred microns to less than 50
micrometers. A second thick diamond deposition also by MWCVD
demonstrated the selective process was highly effective at confining
the diamond growth to within the vias thereby eliminating additional
wafer bow. No degradation of the GaN and associated 2DEG was
observed as characteri:z;ed by non-contact Lehighton sheet resistance
measurements. A highly scalable and selective backside diamond
thermal via approach has been demonstrated. The process is
compatible with GaN HEMT processes and brings the diamond
therrnal via within close proxiInity to the channel region but also
increases the total surface area of device substrate-diamond thermal
contact without changing the substrate bow. Overall, the approach
offers a strong reduction in operating temperatures and possibility for
very high power operation.
DPl.13
Dialllond-Coated High Density Vias for Silicon Substrate-Side
Therlllal Managelllent of GaN HEMTs. Marko Tadjer
'
, Karl
Hobart
2
, Tatyana Feygelson
2
, Travis Anderson
2
, Andrew Koehler
2
,
Loretta Shirey2, Bradford Pate
2
and Charles Eddy, J r. 2; 1 AInerican
Society for Engineering Education, Washington, District of Columbia;
2Naval Research Laboratory, Washington, District of Columbia.
Thermal concerns in III-Nitride power switches cannot be sufficiently
rnitigated by high therrnal conductivity substrates due to the large
thermal boundary resistance at the interface between the nitride thin
film and the substrate. Efficient thermal management through the
substrate in a GaN/Si or GaN/SiC HEMT requires several
considerations. Recognbing that the thermal path is only needed in
the iInInediate vicinity of the heat source in the device, we have
approached the problem by developing a high density, high aspect
ratio through-Si via (TSV) process and subsequently growing high
thermal conductivity CVD nanocrystalline diamond (NCD) along the
via sidewalls. In three dirnensions, a plasIna-assisted deposition/etch
process can be Inodeled as a steady-state probleIn with a
deposition/etch rate defined by the precursor diffusion rate in a
lithographically-defined geometry. We utilized multi-step
inductively-coupled plasma (ICP) and microwave plasma-enhanced
CVD process optirnization to control TSV shape and the subsequent
NCD sidewall coating profile. TSVs were etched in samples of (111) Si
using a Si0
2
mask in a cryogenic Iep dry etch process (-100 aC,
100/5 seem SF6 /02 , 1000/9 W ICP/RIE, -56 V DC bias). The etch
rate was highly dependent on via diameter (5-230 !Lm) and exposed Si
area (from <5% to >95%). However, depth/diameter aspect ratios of
up to 18 were routinely obtained with up to 1 hr etch time. Upon
seeding with 5-25 nm diameter nanodiamond seed solution, NCD films
with 2-3 pm thickness were grown by microwave plasma enhanced
CVD at 750C [4]. Hexagonally-packed circular TSVs helped
rnaxiInize diarnond packing volurne and rninirnize diaInond growth
time. Applied to thermal management of GaN-based transistors, the
proposed method has the advantage of providing a substrate-side
thermal management solution that avoids critical process steps such
as blanket substrate removal. The proposed approach could
potentially keep the substrate within bow specifications while also
freeing the device side of the wafer for scaled processing.
Acknowledgment - M.J.T. acknowledges support from the American
Society for Engineering Education NRL Postdoctoral Fellowship
prograIn. The authors are grateful to Dr. Eugene Irnhoff, Dr. Doewon
Park, Mr. Milt Rebbert and the NSI cleanrooIn staff for processing
support. Research at NRL was supported by the Office of Naval
Research. [1] O. A. Williams, Diamond & Related Materials 20 (2011)
621-640. [2] .1. E. Butler and A. V. Sumant. Chem. Yap. Deposition
2008, 14, 145-160. [3] E. Bozorg-Grayeli et aI., Appl. Phys. Lett. 102,
111907 (2013). [4] K. D. Hobart et aI., International Conference on
Diamond and Carbon Materials, Granada, Spain, 2012.
245
DPl.14
Fabrication of and Study on Multi-Gate-Finger AIGaN/GaN
Power Devices with Si3N4 as Bridge. Defeng Lin
,
,2, Xiaoliang
Wang
1
,2,3, Hongling Xiao
1
,2, Chuli Feng
1
,2, Cuimei Wang
1
,2, Lijuan
Jiang
,
,2, Hong Chen
'
,2, Haibo Yin
'
,2 and He Kang
,
,2; 'Key Lab of
Semiconductor Materials Science, Institute of Semiconductors,
Institute of Semiconductors Chinese Academy of Sciences, Beijing,
China; 2I3cijing Key Laboratory of Low DirIlcnsional Scrniconductor
Materials and Devices, Beijing, China; 3 I SCAS-XJTU Joint
Laboratory of Functional Materials and Devices for Informatics,
Beijing, China.
Power scrniconductor devices have been developed for high power
switching operations in motor control, factory automation, power
supplies, dc-de converters and other switching circuit systems.
AIGaN/GaN high electron mobility transistors (HEMTs) are
prornising candidates for power electronics applications due to their
potentials for fast-switching with low-loss, high breakdown voltage
(BV), high operating temperature, good radiation hardness, etc.
Recently, several hundred volt-AIGaN/GaN power-HEMTs have been
reported, but the drain current of the devices is as small as several
tens of rnilliarnpcrc. We report the fabrication of rnulti-fingcr power
devices on the AIGaN/GaN hetero-epitaxial materials by employing
insulating bridge structure using Si3N4 dielectric layer. The material
structure was grown by metalorganic chemical vapor deposition
(MOCVD) on c-plane (0001) sapphire substrate, and the Si3N4 films
were deposited by Plasrna Enhanced Chcrnical Vapor Deposition
(PECVD) as the surface passivation and insulator films of the bridge.
The DC output characteristic of the power device was measured by
the Agilent B2902A, and the maximum drain current is 1.42A when
the gate voltage is OV, and the gate width of the device Wg= SOO/Lm,
the finger index II = 50. The specific on-resistance of the device is
40.1 mn.cm2. With the gate width increasing, the gate reverse
leakage of the multi-finger increases gradually. However, the current
density of the multi-finger device does not increase with the gate
width linearly. Other rncasurcrncnts arc under progress.
DPl.15
AIGaN/GaN HEMTs with RF-Sputtered AIN Heat Sink.
Abdullah Al-Khalidi
'
, Douglas Macfarlane
'
, James Grant
'
, David
Hutson
2
, Katherine Kirk
2
and Edward Wasigc\ lSchool of
Engineering, University of Glasgow, Glasgow, United Kingdom;
2School of Engineering, University of the West of Scotland, Paisley,
United Kingdom.
Gallium Nitride (GaN) based High Electron Mobility Transistors
(HEMTs) have superior properties compared to other III-V devices as
they exhibit higher sheet carrier concentrations and therefore higher
current densities. They also exhibit higher breakdown voltages. This
translates into a higher total output power as well as an irnprovcd
efficiency. As a result of the higher total output power, self-heating is
a major issue and can be observed by pulsing the device at the cold
bias point (VDS =OV, VCs= OV). From pulsed measurements it was
determined that a 2 X 200.uffi wide device exhibits a maximum current
degradation of approxilnately 200lnA/lnln due to self-heating. FrOITl
DC measurements, the current drops from 405mA/mm to 335mA/mm
after one second of bias time due to self-heating. The sample/device
surface temperature was determined using an infrared thermal
imaging camera to be 2SoC without bias and 3SoC under high bias
(VDS = +5V, IDS = 135mA). Clearly, techniques for improvcd
thermal management are required to fully harness the potential of this
material system. In this paper, we will report on the transistor
performance after a blanket deposition of RF sputtered aluminium
nitride (AIN) of three different thicknesses of 500nln, 1J-LIn and 3p,ln
and show its effectiveness in reducing self-heating.
DPl.16
8.1W/rnrn AIGaN/GaN HEMT Power Device with over 40%
PAE for Ku-Band Application. TingTing Yuan, Xiaojuan Chen,
Weijun Luo, Lei Pang and XinYu Liu; Institute of Microelectronics,
Chinese Academy of Science, Beijing, China.
This paper report S.lW AIGaN/GaN HEMT 1mm-gate-width unit
cell power device at Ku-band frequency. The fabricated device has a
gate length of 0.2um with total gate width of 1mm, adopting
gate-connected field-plate of 0.3um. At a drain voltage of 30V, pulsed
saturated output power of 39.1dBm (S.l W) with linear gain of 10.SdB
and peak PAE of 41.1% at 14GHz is obtaincd. This is the bcst output
power performance of AIGaN/GaN HEMT 1mm-gatc-width unit cell
power device for Ku-band application to the best of our knowledge.
DPl.17
Increase in Breakdown Voltage of AIGaN/GaN HEMTs with
a High-k Dielectric Layer. Hideyuki Hanawa and Kazushige Horio;
Shibaura Institute of Technology, Saitama, Japan.
It is well known that the introduction of filed plate enhances the
breakdown voltage in AlGaN/GaN HEMTs [1]. This is because the
electric field at the drain edge of the gate is reduced. However, the
field plate increases the parasitic capacitance, leading to the
degradation of high frequency performance. As another way to
improve the breakdown voltage, the introduction of high-k passivation
layer can be considered. Then, in this work, we have analy:tied I-V
characteristics of AIGaN/GaN HEMTs as functions of relativc
permittivity of the passivation layer ET and its thickness d, and found
that the off-state breakdown voltage Vbr increases as nand d
increase. We consider an AIGaN/GaN HEMT on a semi-insulating
GaN buffcr layer [2]. The gate length LG and thc gatc-to-drain
distance LGD arc typically 0.3 and 1.5 J-LIn, respectively. The
thickness of passivation layer d is typically 0.1 /Lm. In a buffer layer,
we consider a deep donor and a deep acceptor [3], and the
deep-acceptor density is set to 1017 cm-3 [2]. First, we calculate
ID-VD curves and IG-VD curves at VG = - 8 V, with Er as a
parameter. As Er increases, the breakdown voltage, at which ID and
IG increase suddenly, increases. This is because as Er increases, the
electric field at the drain edge of the gate decreases. This occurs
because in the insulator the applied voltage tends to drop uniformly
in general, and hence when the insulator is attached to the
semiconductor, the voltage drop along the semiconductor becomes
smoother at the drain edge of the gate if the permittivity of the
insulator is higher and the electric flux lines concentrate more in it.
Vbr increases 40 V at n = 4.2 to 275 V at n = 20. Here, it should be
noted that when fT 30, ID becolnes greater than 1InA/lnln before a
sudden increase in ID, and IG is rather low. This is understood that
for relatively short LGD, holes generated by impact ionization
between gate and drain flow into the buffer layer and the conductivity
modulation occurs, resulting in a very high buffer leakage current.
Then, Vbr tends to saturate beyond Er = 30 in this case. However,
Vbr should become higher when LGD becomes longer, because the
high electric field region extends more toward the drain. Next, we
calculate ID- VD curves and IG- VD curves as a parameter of the
passivation layer thickness d when Er = 20. It is shown that Vbr
increases as d increases because the electric field at the drain edge of
the gate is weakened as d increases. Therefore, increasing d has the
same effects as increasing Er. By the way, the high-k layer is used as a
gate insulator in GaN-based MISHEMTs. For example, Hf02 (n
20), La203 (Er 27) and LaLu03 (n 2S) ctc. are studied [4]. [1] S.
Karmalkar and U. K. Mishra, IEEE Trans. Electron Devices, 48, 1515
(2001). [2] H. Onodera and K. Horio, Semicond. Sci. Technol., 27,
OS5016 (2012). [3] K. Horio et aI., J. Appl. Phys., 9S, 124502 (2005).
[4] S. Yang et aI., IEEE Electron Device Lett., 33, 979 (2012).
DPl.18
Sidewall Effects on Fin-Gate AIGaN/GaN MOS
Channel-HEMT. Shinya Takashima
'
,2, Zhongda Li
'
and T. P.
Chow
'
; 'Rensselaer Polytechnic Institute, Troy, New York; 2Fuji
Electric Co., Ltd., Hino, Tokyo, Japan.
AIGaN/GaN high electron mobility transistors (HEMTs) have been
recently attracting great interests. AMOS channel-HEMT
(MOSC-HEMT) combines GaN MOS-gated channel with HEMT,
which gives the advantages of nonnally-off operation and low specific
on-resistance. In MOSC-HEMT, the downscaling of MOS channel is
necessary to improve the specific on-resistance due to the lower
electron mobility of GaN MOS channel than that of the 2DEG in the
HEMT channel. However, undesirable short channel effects appear
with decreasing MOS channel length, which Inust be prevented. A
fin-gate structure is one of the promising candidates to suppress short
channel effects and to obtain high performance devices [1-3]. This
paper presents the performance dependence on channel length, fin
width, and temperature on MOSC-HEMTs with and without the
fin-gate structure. Whereas in conventional MOSC-HEMT, the
threshold voltage (Vth) decreases and the drain induced barrier
lowering (DIBL) effects become more severe with decreasing channel
length, in MOSC-HEMTs with fin-gate structure
(Fin-MOSC-HEMTs), the threshold voltage remains nearly constant
against channel length and DIBL effects arc suppressed. The channel
sheet resistance and device transconductance for Fin-MOSC-HEMTs
are superior to those of conventional MOSC-HEMTs, when they are
normali:tied by effective gate width, indicating contribution from
sidewalls to channel conduction. Though the short channel effects are
suppressed by the fin-gate structure, the threshold voltage decreases
from positive to negative value by adding a fin-gate onto long channel
transistors. The threshold voltage also shows monotonic decrease with
decreasing fin width. These results can be understood by considering
the operation Inode of fin-gate sidewall channel, and the sidewalls of
our fin structure work as depletion Inode channel. The telnperature
dependence of threshold voltage shows clearly different behaviors
between the MOSC-HEMT and the Fin-MOSC-HEMT. In the
conventional MOSC-HEMT, the threshold voltage shows a complex
telnperature dependence [4J By contrast, in the Fin-MOSC-HEMT, it
is less temperature dependent and only decreases slightly. The small
temperature dependence of threshold voltage can be explained by the
246
lack of polarization charge on fin-gate sidewalls [5]. This difference
demonstrates that the Vth on Fin-MOSC-HEMT is not determined by
the recessed MOS channel at the top of the fin but MOS channel OIl
the sidewalls. In summary, we investigated the fin-gate structure and
its sidewall effect on AIGaN/GaN MOSC-HEMTs. The results
demonstrated sidewall-dominated characteristics on
Fin-MOSC-HEMTs. [1] X. Huang et aI., IEDM Tech. Dig., 1999, Pl'.
67-70. [2] K. Ohi and T. Hashizurne, Jpn. J. Appl. Phys., 48 (2009)
081002. [3] B. Lu et aI., IEEE Electron Device Lett., 33 (2012) 360.
[4] J. Zhang et aI., in Proc. Lester Eastman Conference on High
Performance Devices, 2012. [5] K. Matocha et aI., Appl. Phys. Lett.,
90 (2007) 123511.
DPl.19
Simulated Thermionic Engine Performance Using III-Nitride,
Negative Electron Affinity Collector. Joshua R. Smith, Sensors
and Electron Devices, United States Arrny Research Laboratory,
Adelphi, Maryland.
Most attention to improving vacuum thermionic energy conversion
device (TEC) technology has been on improving electron emission
with little attention to collector optirnization. Many rnatcrials such as
scandates, BaO, and cesiated materials already exhibit relatively high
electron emission at moderate temperatures. An open problem with
vacuum TEes is current self-limiting due to the negative space charge
effect. This effect can limit the output power and efficiency of a TEC
to an irnpractically low level. A TEC featuring a negative electron
affinity (NEA) emitter material has been reported in the literature to
theoretically mitigate the negative space chrage effect. In this present
work, a model was developed to characterize the output
characteristics of a TEC where the collector features NEA. Under
certain conditions, III-nitride rnaterials such as GaN, AlGaN, and AIN
can acquire a NEA. According to the model, there are certain
conditions for which the space charge limitation can be reduced or
eliminated. Devices featuring such nitride materials as the collector
electrode are sirnulated and conditions for which the device achieves
20% efficiency and 1kW output power are calculated. The rnodel is
based on the solution of the Vlaslov-Poisson system, which has been
successfully used to model the space charge limited electron transport
through a parallel-plate vacuum thermionic device in the past. The
rnodel was irnplernented as a library in the python prograrnrning
language and the numpy/scipy scientific programming stack.
DP1.20
Effects of High Temperature Etching on GaN Using by CI2
PlaSllla. Hiroko Iguchi
l
, Ryosuke Kornetani
2
, Michael Liu
2
, Kenji
Nakashirna
l
, Takahiro Kozawa
l
, Kenji Ishikawa
2
, Makoto Sekine
2
and
Masaru Hori
2
. "Toyota Central R&D Labs Inc Nagakute Aichi
Japan; Nanotechnology Reseach Nagoya Univ., '
Nagoya, Aichi, Japan.
Galliurn nitride (GaN) related rnaterials are attracted attention for
the application of high voltage and high power devices. Since a GaN is
very stable chemically, dry etching processes are generally used to
fabricate the device with mesa structures such as a recessed gate
structure for norrnally-off operation. However the dry etching
processes introduce inevitably darnages such as point defects, which
degrade electrical properties. In previous reports, the thermal
processes after the etching are effective to recover the degraded
electrical properties [1]. Moreover, they reported that etch rates
increased as ternperature for etching increased [2J. The radio frequency
(RF) power is essential for etching, however high power would create
inescapable damages. Therefore, we proposed the high temperature
(HT) etching, which enabled us to achieve similar etch rates for at
room temperature by reducing the RF power. Namely, the HT-etching
rnay suppress the defects forrnation due to the in-situ restoration
effect during etching processes and the low RF power. In this study,
we have proven the effect of the HT-etching up to 600oC. The samples
were prepared as follow. By using the metal-organic chemical vapor
deposition system, a 2lLm-thick Si-doped GaN layer with a
concentration of 2x1017 crn-3 on a 3J-un-thick unintentionally-doped
GaN layer was deposited on sapphire substrates. These samples were
etched in the C12. The etch pressure and the RF power were set to be
10Pa and 60W, respectively. After the etching at temperatures from
300 to 600oC, we observed the surface of the samples by atomic force
rnicroscope. Hexagonal pits due to the defect selective etching were
observed in the sample etched at 600oC. In contrast, few pits were
observed in the samples etched at 5000C or less. To assess the
formation of point defects, we photoluminescence (PL)
properties of the sarnples. As the etch ternperature increased, the
yellow lurninescence intensity (IYL) around 2.2eV in the PL spectra
decreased. The IYL/IBL (band-edge luminescence intensity) ratios of
the samples were 0.013 for 3000C and 0.008 for 500oC. This result
indicate that the HT-etching suppress the formation of the Ga
vacancies (VGa) related defects because VGa related defects are
responsible for the IYL [3]. It's speculated that the damages recover
partially during the HT-etching. At the high temperatures, the etch
rates were 294nm/min for 3000C and 535nm/min for 600oC. Thus a
similar etch rate for at the low temperature could provide with the
lower RF power of 20W at 500oC. Its IYL/II3L ratio was the low
value of 0.006. Consequently, we have revealed that the HT-etching
enables to reduce the defects creation during etching on the effects of
not only the in-situ restoration effect but also the lowering of the RF
power. [1] X. A. Cao, et aI., Appl. Phys. Lett. 75 (1999) 2569. [2]
R.J.Shul, et aI., Appl. Phys. Lett. 66 (1995) 1761 [3] M.A.Reshchikov,
et aI., J. Appl. Phys. 97 (2005) 061301
DP1.21
Gallium Nitride MOS Capacitors with Low D
i
, for High
Power Devices. Ahrned Chakroun, Jihane I3oughaleb, Abdelkader
Souifi, Vincent Aime7., Hassan Maher, Richard Ares and Abdelatif
Jaouad; Institute for Interdisciplinary Innovations in Technology
(3IT), Laboratoire Nanotechnologies et Nanosystemes - UMI-LN2
3463 CNRS/UdeS/INSA Lyon/ECL/CPE lyon/UJF/3IT, 3000
Boulevard de l'Universite, Sherbrooke, JIK OA5, QC, CANADA,
Sherbrooke, Quebec, Canada.
In this work, we report on the development of an effective GaN
surface passivation process by optirnizing the surface chernical
pre-treatment prior to the PECVD-SiO
x
deposition. It is
demonstrated that the electronic properties of the GaN/SiOx
interface are drastically affected by the surface preparation
conditions. Among the used chemicals, we found that KOH/HCI leads
to the best GaN/SiO
x
interface quality. MOS capacitors fabricated
using this pre-treatment have shown a capacitance-voltage (C-V)
characteristics, with an excellent surface potential modulation, small
flat band voltage shift, low hysteresis, and no significant frequency
dispersion. Using this passivation technique, a surface state density as
low as 2 x 10
10
eV-
l
crn-
2
was achieved. Robustness and
reproducibility of this passivation process was successfully
demonstrated on GaN layers grown with different techniques and
having different thickness and carrier concentration. A demonstration
of the effectiveness of our GaN passivation process is actually on
going on GaN MOS-HEMT transistors.
DP1.22
Study on the Thermal and Optical Properties of
Alternating-Current Light-Emitting Diodes Driven on
Different Frequencies. Zhang Jihong", Lin Yue",2, Lu Yijun", Zhu
Lihong
l
, Gao Yulin
l
and Chen Zhong
l
; lXiamen University, Xiamen,
China; 2Fujian Institute of Research on the Structure of Matter,
Chinese Academy of Sciences, Fuzhou, Fujian, China.
In this paper we rnainly focus on the effect of driving frequencies upon
the thermal and optical properties of alternating current
light-emitting diodes (AC-LEDs). By the simulation on the electrics
equivalent circuit, the thermal impedance of the heat flow path in a
typical LED is investigated in detail. An infrared (IR) thermography
(Research-N2) served as the junction ternperature rnonitor and its
results reveal that the junction temperature oscillation would be
significantly mitigated by means of increasing the driving frequency.
On 50 the frequency of the power supply in most of countries, the
junction ternperature is suffering severe fluctuation, with its peak
value up to 73.5C, valley down to 55.2C. However, with increasing
frequency, the difference in temperature is diminishing, as is almost
unique on 1000 Hz. These experimental results are well consistent
with those gained from the circuit simulation. In addition to the
therrnal properties, we investigated the spectrurn as well. The rnean
electroluminescence (EL) spectra on those frequency points mentioned
above are captured by a spectrometer (Ocean Optics). With
increasing frequency, the intensity is increasing and the center of mass
wavelength shows strong blue-shift initially then slight red-shift.
Although the detailed rnechanisrns of these phenornena are rather
complex, the blue-shift can be primarily attributed to the thermal
effect and the red-shift mainly to the output power shift of the AC
source on high frequency. In conclusion, it is better to power AC-LEDs
by the sources with higher frequency, not only to eliminate the flicker
effect, but also to rnitigate the harrn junction ternperature oscillation.
DP1.23
Elimination of Gate Leakage in GaN HFET by Placing
Spacers on Mesa Sidewall. Peng Liu", Chuncheng Xie
2
, Feng
Zhang
2
, Jianguo Chen
2
and Dongmin Chen"; 1 School of Innovation
and Entrepreneurship, Peking University, I3eijing, I3eijing, China;
2Founder Microelectronics International Co., Ltd., Shenzhen,
Guangdong, China.
In GaN HFET fabrication, the active region is cornrnonly forrned by
etching a rnesa structure. However, this rnethod will result in gate
leakage occurred on the points where the gate metal is contact with
the 2DEG on the mesa sidewalls. The authors fabricate spacers on the
mesa sidewalls by etching Si02, acting as an insulator between the
gate rnetal and the 2DEG to elirninate gate leakage. The reported
device in this paper is a metal-insulator-semiconductor (MIS) HFET,
247
where the gate insulator is a thin Si3N4 layer deposited by LPCVD.
The spacer is formed by depositing a thick Si02 layer by PECVD and
then etching cornplctcly the Si02 layer. The source, drain and gate
electrodes are formed by sputtering metal films and then patterning
by plasma etch. From the measurement, it is found that (1) the gate
leakage is several nA at VGS=-15V, and (2) the gate leakage is
independent of gate width, suggesting the good dielectric properties of
LPCVD Si3N4 and effective elimination of gate leakage by the
spacers. The other benefit of employing spacers is that, when
patterning the source, drain and gate electrodes by plasma etch, the
metal deposited on the bottom corner of spacer is more easily to be
etched cornplctcly due to the spacer slope. Without spacers, the over
etching tirHe should be longer due to the 90 degree included angle
between mesa sidewall and the substrate plane, which will inevitably
result in an over etching on the gate insulator in MIS structure, or
AIGaN barrier in HEMT structure. Compared with the fabrication
process of MIS gate structure reported in literatures, the technique
introduced in this paper will decrease one photo mask, because the
mask to define the gate insulator is not needed anymore. This will
reduce the manufacturing cost.
DP1.24
Effect of Dielectric Deposition and Annealing on
AI203/AIGaN/GaN Interface States. Jiechen Wu and Dwight
Streit; University of California, Los Angeles, Los Angeles, California.
We present here cxpcrirIlcntal results and analysis of post-deposition
annealing effects on AI203/AIGaN/GaN
metal/insulator / semiconductor heterostructures. Conventional
AIGaN/GaN Schottky-gate high electron mobility transistors suffer
from problems such as high gate leakage and current collapse. Due to
the rnatcrial properties of high dielectric constant, large bandgap and
high breakdown field, Al203 thin films grown by atomic layer
deposition have been used as gate dielectric materials to suppress gate
leakage and passivate surface states. The dielectric/semiconductor
interface then bccolncs a critical issue since good gate control of the
transistor depends OIl the interfacial properties. We have studied and
characterized the A1203/ AIGaN interface and the post annealing
effects on interface states to better understand the relative
importance of these issues. In this work we fabricated
metal/dielectric/AIGaN/ GaN MISH diodes and characterized the
A1203/ AIGaN interface with different post-deposition annealing
conditions. Ti/ AI/Ni/ Au (20/120/40/50 nm) metal stacks were
evaporated and annealed at 800C to form ohmic contacts. The AI203
layer was deposited by atomic layer deposition. Trimethylaluminum
and water vapor were used as the Al and 0 sources for the Al203
films. The samples then underwent post deposition annealing at 400
DC, 500C and 600 c for 1 minute in nitrogen atmosphere,
respectively. Ni/Au (20/50 nm) was used as gate contact on the
dielectric layer. Non-annealing AI203/AIGaN/GaN structure was also
fabricated for cornparison. Electrical characterization, including
current-voltage (I-V) measurements, shows that the all MISH
structure samples have superior suppression of gate leakage current
compared to conventional schottky gate AIGaN/GaN structure.
Capacitance-voltage characterization of the AI203/AIGaN/GaN
structures are also reported with three stages of the voltage sweeping
range. We compared the C-V characteristics of annealed samples and
non-annealed samples. It showed that the annealed samples exhibit
significant changes of threshold voltage, indicating a great reduction
of fixed charges at A1203/ AIGaN interface. Multiple frequency C- V
profile also suggested that the trap density of annealed samples are
much lower than non-annealed samples. Temperature dependent C- V
was performed to study deeper level states in annealed samples. C-V
curves with negative shift were clearly observed and used to estimate
the A1203/ AIGaN interface state density at upper bam!.
DP1.25
Dependence of ALD-AI2 0 3/InAIN Interface Properties on
Fabrication Process. Takuma Nakano, Masahito Chiba and
Masarnichi Akazawa; RCIQE, Hokkaido University, Sapporo, Japan.
Recently, a marked progress of the cut-off frequency of InAIN/GaN
HEMTs has been achieved by using a gate insulator. However,
understanding and the control method of the insulator /InAIN
interfaces have not been rnatured. Here, it is shown that the
fabrication process affects the AI
2
0
3
/InAIN interface properties, even
though the interface is formed by ALD. Three MOS diodes referred to
as samples A-C, with the ALD-AJ,03 (18 nm)/n-Ino.17Alo.S3N (160
nm, n = 2 X 10"
8
cm-3) interfaces and the Ni/ Au circular electrodes
in the center of the Ti/ AI/Ti/ Au annular ohmic contacts, were
fabricated on sapphire substrates and cornpared. The Al 2 0
3
layer was
fonned by ALD at 350C using H 2 0 and TMA, while ohrnic contact
annealing was performed at 850C for 1min in nitrogen. For sample
A, the AI2 0 3/InAIN interface was formed after capless-annealing for
ohmic contacts. Right after capless-annealing, XPS results indicated a
favorable change in the rnain cornponent of the native oxide fronl
Al-O-H bonding to AI-O-Al bonding. However, an increase in the 0 Is
intensity indicated a slight oxidation due to the contamination inside
the furnace during annealing. The 1 MHz capacitance-voltage (C- V)
curve exhibited a srnall capacitance change with the low break-down
voltage. The capacitances were too small for evaluating the
interface-state density (Dit ) because the corresponding surface Fermi
level locations were deep inside the band gap. For sample B, at first,
the AJ,03/InAIN interface was formed after removing the native
oxide by the buffered hydrofluoric acid (BHF) treatrnent. Then ohrnic
contact annealing was performed using the Al
2
0
3
layer as a cap layer.
Though the MOS diode showed a small capacitance change in the C-V
curve again, the capacitances were larger than those of sample A. D it
was evaluated to be in the 10
13
crn-
2
eV-
1
range. It was highly likely
that the polycrystalline state of the annealed Al 2 0
3
layer affected the
electrical properties. For sample C, ohmic contact annealing using a
SiN
x
cap layer and the subsequent BHF treatment were performed
prior to the AJ,03/InAIN interface formation. This sample showed a
rnuch irnproved C- V curve with a large capacitance change. D
it
was
evaluated to be in the range of 10" to 10"
2
cm-
2
eV-
1
These results
indicated that the ALD-AI
2
0
3
/InAIN interface should be formed
carefully with the removal and prevention of the native oxide, despite
the thermal and chemical stabilities of InAIN, and that the SiNx layer
was suitable for the surface protection during ohrnic contact
annealing. The origin of the interface states will be discussed.
DP1.26
Reduction of Schottky Gate Leakage Current in AIGaN/GaN
HEMTs Using an AIN Back-Barrier. Xin Kong, Ke Wei, Guoguo
Liu, Sen Huang, Xinyu Liu and Jinhan Zhang; Microwave Devices and
Integrated Circuits Department, Institute of Microelectronics, Chinese
Academy of Sciences, Beijing, Beiijing, China.
Excellent power handling capabilities and high-frequency response
have made AIGaN/GaN high electron mobility transistors (HEMTs)
promising candidates for the next-generation RF/microwave power
amplifiers. However, these devices still suffer from large reverse gate
leakage currents, which result in the degradation of breakdown
voltage, gate control capability and noise performance, as well as the
reduction of device lifetime. A lot of efforts have been performed to
overcome this problem, including optimizing the processing
techniques, improving the material quality and adopting different gate
insulators. In this work, a thin AIN filrn ('"'-'2 run) was intentionally
inserted between the GaN channel and buffer layers to establish a
high potential barrier therein. The selection of AIN instead of AIGaN
or InGaN should be mainly attributed to its wider bandgap and
maturer growth technology. The heterostructure with an AIN
back-barrier presented cornparable electron sheet density, carrier
mobility and sheet resistance to that in the reference structure
according to the Hall measurements at room temperature. The
standard submicrometer gate fabrication procedures were applied to
both sarnples and the final rneasurernents were carried out focusing on
a 0.16 X 75-l-un device. Taking the uniforrnity of wafer into account,
the data of gate leakage current were obtained in devices from
different regions. The gate leakage currents of the AIN back-barrier
HEMTs were found to be reduced by about two orders of magnitude
at Vg = -20 V relative to the standard HEMTs, and no notable
decline in the DC current-voltage characteristics was observed. The
gate leakage currents in AIGaN/GaN HEMTs have been considered to
consist of two components, namely the vertical tunneling and lateral
tunneling currents. The high potential barrier induced by the AIN
layer could prevent the leakage electrons fronl injecting into the
buffer, and thus effectively suppressed the vertical leakage component.
It should be noted that the growth of AIN back-barrier should be
highly cared, otherwise more dislocations and micropipes could be
introduced and additional leakage pathways would be produced.
DP1.27
AIGaN/GaN HEMT Based Liquid Sensor. Weijun Luo,
Xiaojuan Chen, Lei Pang, Tingting Yuan and Xinyu Liu; Institute of
Microelectronics, Chinese Acaderny of Sciences, I3eijing, China.
The characteristics of AIGaN/GaN HEMT liquid sensors are reported.
The sensor consisted of a 1um gate length and 100um gate width are
designed and fabricated by optical lithography process. Ni/Au and
Ti/ AI/Ni/ Au metals are used as Schottky contact and Ohimc contact,
respectively. The performances of the AIGaN/GaN HEMT sensors
exposed to different polar liquids are investigated. Under Vgs=+lV
Vds=10V, the maximum drain-source current Ids of the sensor are
58.073, 56.31 and 53.239mA in air, ethanol and acetone, respectively.
The change of rnaxirnurn drain-source current DIds of the sensors are
1.763mA with a percentage of 3.04% in ethanol, while the
corresponding value are 4.844mA 8.34% in acetone. The maximum
transconductonce of the sensor is 150.285mS/mm@-1.5V in air,
148.695mS/mm@-1.8V in ethanol and 143.79mS/mm@-1.9V in
acetone. Cornpared with the value in air, the percentage of the
maximum transconductance degradation are 1.06% in ethanol and
4.32% in acetone. Besides, the performances of the AIGaN/GaN
HEMT sensors exposed to different concentration of acetone are also
248
tested. Analytical together with experiment data analysis are carried
out to investigate the sensing mechanism of the AIGaN/GaN HEMT
liquid sensors. When the sensors were exposed to the polar liquids,
the molecules of the polar liquids interact with the surface states by
their dipole moments. Then the surface potential of the AIGaN as
well as the q,Beff can be changed, which results in the change of the
I-V, transfer and transconductance characteristics of the AIGaN/GaN
HEMT sensors. It is proved that the Inore polar and the higher
concentration of the polar liquids, the more change of the electrical
parameters of the sensors. The results reinforce the notion that
AIGaN/GaN HEMT are very promising for a wide variety of sensor
applications in horncland security, rncdical, cnvironlncntal rIlonitoring,
food safety, etc.
DP1.28
Improved High-Temperature Stability of 2DEG Channel in
AIGaN/GaN Heterostructures by PEALD-Grown AIN Thin
FilITl Passivation. Sen Huang!, Ke Wei!, Xinyu Liu
I
, Guoguo Liu
I
,
Bo Shen
3
and Kevin J. Chen
2
; 1 Department of Microwave Devices and
Integrated Circuits, Institute of Microelectronics of Chinese Academy
of Sciences, Beijing, China; 2Department of Electronic and Computer
Engineering, Hong Kong University of Science and Technology, Hong
Kong, China; 3School of Physics, Peking University, Beijing, China.
The high carrier density and high mobility of the 2DEG channel yield
low ON-resistance in AIGaN/GaN power HEMTs. Especially, the
2DEG density can be adversely affected by the trapping/detrapping of
the slow states on the polarized AIGaN barrier layer surface, leading
to current collapse in GaN-based RF power amplifiers and power
switches. To improve the stability of the 2DEG density, in addition to
the commonly used SiNx passivation, a novel passivation concept was
demonstrated recently using epitaxial AIN thin film grown by
plasma-enhanced atomic layer deposition (ALD) (PEALD). The
mechanism of this AIN passivation is to compensate the traps with
positive polarization charges in AIN. Low dynamic ON-resistance,
high breakdown voltage and low OFF-state leakage are attainable
sirnultaneously. Since high junction/arnbient ternperatures are
cornrnon for the operation of high-power devices/circuits, it is of great
importance to investigate the thermal stability of the PEALD-AIN
passivated AIGaN/GaN heterostructures. While the electron mobility
naturally decreases with increasing temperature due to stronger
phonon scattering, the 2DEG density's ternperature dependence is
predominantly determined by the thermal stability of the surface. In
this work, we report a comprehensive study on the stability of
AIGaN/GaN-on-Si heterostructures passivated with PEALD-AIN at
high temperatures (up to 500 oC), primarily by
ternperature-dependent Hall effect rneasurernent. Cornpared to an
un-passivated AIGaN/GaN sample, AIGaN/GaN heterostructure with
a 4-nm PEALD-AIN passivation exhibits good 2DEG transport
behavior and stability at moderately high temperature (e.g. 275 oC),
even though the passivation layer is partially oxidized. However,
serious oxidation of the 4-nrn AIN passivation layer and the AIN/GaN
interface occurs as the temperature exceeds 400 oC, and leads to a
reduction of 2.47 X 1012 cm-2 in the 2DEG density at room
temperature. A modified AIN passivation structure with A1203/ AIN
(10/4 mn) stack exhibits significantly enhanced 2DEG density and
high-ternperature stability up to 500 oC. The irnproved therrnal
stability is attributed to suppressed AIN/GaN interface oxidation as
confirmed by X-ray photoelectron spectroscopy. The 2DEG mobility
for all the three samples, whether AIN or A1203/ AIN passivated,
exhibits good irnrnunity to surface oxidation.
DP1.29
Impact of Intrinsic Stress in Diamond Capping Layers on the
Electrical Behavior of AIGaN/GaN HEMTs. Ashu Wang
1
,
Marko .1. Tadjer
1
.
2
, Travis .1. Anderson
2
, Roland Baranyai
3
, James
W. Porneroy3, Tatyana I. Feygelson
2
, Karl D. Hobart
2
, Bradford B.
Pate
2
, Fernando Calle
1
and Martin Kuba1l
3
; 1I SOM and Dpto.
Ingenieria Electr6nica, ETSI Telecomunicaci6n, Universidad
Politecnica de Madrid, Madrid, Spain; 2Naval Research Laboratory,
Washington DC, Maryland; 3Center for Device Thermography and
Reliability (CDTR), University of I3ristol, I3ristol, United Kingdom.
For films deposited at high temperatures, such as nanocrystalline
diamond (NCD) used as a heat spreader capped on AIGaN/GaN
HEMTs [1], a significant intrinsic stress will result from the large
therrnal expansion coefficient rnisrnatch with the III-Nitride
heterostructure. In order to analY7.e how this intrinsic stress in the
capped NCD layer impacts on the device electrical behavior, we
developed an electro-thermo-mechanical model [2] to couple the
2DEG density with the stress in the device. Based on this rnodel,
finite elernent rnethod (COMSOL) was used as the nurnerical
calculations, which were verified by the experimental data from
Raman spectroscopy and I-V characterization. Assuming the surface
potential was unchanged by the additional stress induced by the NCD
cap, change of the AIGaN/GaN interfacial piezoelectric polarization
charge mainly causes the 2DEG other than the AIGaN surface charge
to compensate it, which presents a potential to improve the device
performance by stress engineering. Integration of the 2DEG density
frorn source to drain contact revealed a redistribution of sheet density
with total sheet charge concentration remaining unchanged. Tensile
stress from the NCD cap would lead to additional tensile stress and
thus an increase in 2DEG density under the gate. As a result,
additional compressive stress will develop and lead to decreased
2DEG in the regions between the gate and source as well as gate and
drain contact. Using this verified model, extended simulations were
performed for general cap layer. Combined with the reported results
[3], tensile stress in the cap layer would improve the device electrical
behavior, but aggravate the rnechanical degradation; conversely,
cornpressive stress in the cap layer would rnitigate the rnechanical
degradation, but reduce the electrical behavior. References: [1] M . .1.
Tadjer, et aI., IEEE Electron Device Lett., 33, 23 (2012). [2] A. Wang
et aI., IEEE Trans. Electron Devices, submitted (2013). [3] M. G.
Ancona et aI., .1. Appl. Phys., Ill, 074504 (2012).
DP1.30
Admittance Spectroscopy of Deep Donors in 200nm-Thick
Ino.16Alo.84N/GaN and Partial Carrier Freeze-Out.
Marcel A. pyl, Lorenzo Lugani
l
, Yoshitaka Taniyasu
l
,2,
Jean_Francois CarlinI and Nicolas Grandjean
l
; Iphysics, EPFL,
Lausanne, Swit7.erland; 2 NTT Basic Research Lab., NTT
Corporation, Atsugi, Japan.
Nominally-undoped 200 nm-thick Ino.16Alo.s4N/n+-GaN samples
were grown by rnetal-organic vapor phase epitaxy. Thick InAIN layers
are suitable as cladding layers -in lasers, wave-guides- and for
capacitive characterization methods. Ni/Au Schottky diodes (area A)
were characterized by temperature-dependent current-voltage in the
90-400 K range. Above 190 K, the forward current at bias <:: 1.2 V
originates fronl tunneling, rnost likely defect-assisted. The saturation
current J s (T), tunneling energy Eo and series resistance R
s
(T) were
extracted. The capacitance-voltage (C-V) measurements at a
frequency f of 1 MHz were carried out in the same T -range. Fitting
the ErEOA/C(V) curves -below 200 nrn- provides both the "usual"
depletion width and a ternperature-dependent thickness which, in the
high-frequency limit (i.e. w much larger than en(T), see below), is the
sum of the Debye screening length and of the width of the
intermediate region [1]. The measured capacitance C= is low for T<::
200 K and weakly dependent on reverse bias, typical of carrier
freeze-out. At higher T, a smoothed capacitance "step" occurs which
shifts with the angular frequency w. Isothermal frequency-dispersion
curves C=(w), conductance G=(w) and (G=/w)(w) were recorded in
the range 210-320 K by sweeping f (5 x 10
3
Hz <:: f <:: 5 x 10
6
Hz).
The Arrhenius plot e
n
/T
2
was deduced fronl the position W
max
at the
peak of (G/w)(w) , where en(T) is the thermal emission rate of the
involved level and G the corrected conductance for the effect of R s .
The extraction of en (T) follows the analysis of admittance
spectroscopy for a dominant deep donor level [2]. Assuming no
therrnally-activated capture cross-section u, the energy depth of the
deep donor D2 would be Ec-ED2= 0.29 eV and 0"2==6.2 x 10-
15
cm
2
. Its concentration N
D2
is about 1.7 x 10
18
cm-
3
from C-V data
on both sides of the "step" (NDnet rising from 9 x 10
17
to 2.6 x 10
18
cm-
3
, using Er =10 for Ino.16Alo.84N). A minor donor level Dl is
observed below 150 K, with signature E
c
-ED1 = 0.13 eV and
0"1==3.5 x 10-
14
cm
2
. N D1 is more difficult to quantify, but
significantly srnaller than N D2 according to the relative peak heights
G(Tmax)' Finally, several evidences of partial carrier free7,e-out will
be presented at the conference. We plan to extend our measurements
above 400 K, to investigate thinner InAIN layers, nearly
lattice-rnatched to GaN, and to clarify the origin of the observed
donor levels. [1]. M.P. Verkhovodov et al. Semicond. Sci. Technol. 8,
1842 (1993). [2]. S. Duenas et al. .1. Appl. Phys. 69, 4300 (1991).
DP1.31
Enhanced OFF-State Breakdown Voltage in AIGaN/GaN
HEMTs on Si with Low-k Benzocyclobutane (BCB)
Encapsulation. M . .1. Anand, Ng Geok lng, Subramaniam
Arulkumaran, Kumud Ranjan, S. Vicknesh and Kian Siong Ang;
School of EEE, Nanyang Technological University, Singapore,
Singapore.
AIGaN/GaN High-Electron-Mobility Transistor (HEMT) has emerged
to be one of the most attractive device technologies for both
high-power and high-frequency applications [1]. For rnonolithic
integrated circuits, final encapsulation is required to provide
protection for the entire circuit and thus enhance their reliability.
Thick dielectric materials such as plasma enhanced chemical vapour
deposited Si02, Si3N4, spin-on-glass (SaG), Benzocyclobutane
(BCB), Polyirnide have been ernployed for encapsulation purpose
[2,3]. However, high dielectric constant materials are not suitable for
circuits operating at high frequency as the resulting high parasitic
capacitances will degrade the device performance. Among the many
types of encapulation materials, BCB offers several advantages such
as (i) low dielectric constant ~ 2 . 6 5 which will results in lower
249
parasitic capacitance, (ii) high glass transition temperature (>3500C),
(iii) very low moisture absorption and (iv) high degree of
planarization [4]. Wang et al has reported I3CI3 that can be effectively
used as a replacement for Si3N4 for surface passivation [5]. However,
for Integrated Circuit (IC) fabrication, one typically uses a thin layer
of dielectric layer such as Si3N4 and/or Si02 for device passivation
follow by a thicker layer of encapsulation layer for final passivation
and planarization. This is because Si3N4 and Si02 arc found to be
very effective for device passivation [6J. However, one cannot just use
a thick Si3N4 layer for passivation cum encapsulation as it will cause
heavy stress to the AIGaN/GaN HEMTs [7]. To date, there are no
reports OIl the irnpact of GaN HEMT pcrforrnancc llsing Si3N4
passivation plus nen encapsulation. In this work we report the
influence of BCB encapsulation on Si3N4 passivated AIGaN/GaN
HEMTs on Si substrate with two-fingers and multi-fingers. With
reference to AIGaN/GaN HEMTs without BCB, no significant
pcrforrnancc change has been observed in the nen encapsulated
HEMTs. About an order of magnitude lower drain leakage current has
been observed in BCB encapsulated AIGaN/GaN HEMTs. The
devices with BCB exhibited 90% improvement in BVgd which is due
to the decrease of the two terminal gate leakage current. Similar
percentage of BVgd cnhanccrncnt has also been observed with the
increase of gate-drain spacing (LGD). Table I shows the DC
parameters (IDmax, gmmax, Vth), IT and fmax for the devices with
and without BCB encapsulation. These results show that there is no
significant impact of these DC and microwave parameters from the
thick ncn cncapulation layer. No significant change has been
observed in both two finger and multi-finger AIGaN/GaN HEMTs
device performance which suggests that the BCB encapsulation does
not damage the air-bridge structures of the multi-finger devices and it
also does not introduce significant impact to its electrical
perforrnance. In conclusion, ncn encapsulated AIGaN/GaN HEMTs
exhibited enhanced BVgd without compromising the DC and
microwave performances. Hence, BCB encapsulation is believed to be
a viable solution to protect AIGaN/GaN HEMTs and its integrated
circuits. 1) U. K. Mishra et aI., Proc. of the IEEE, 90 (2002) 1022. 2)
R. F. Kopf et aI, J. Electron. Mater. 27 (1998) 954. 3) M. Sudow et
aI., IEEE Trans. Microwave Theory, 56(2008) 1827. 4) Y. So et ai,
2004 Electron. Pack. Tech. Conf., (2004) 473. 5) W. Wang et ai, IEEE
EDL 25, (2004) 763. 6) S. Arulkumaran et aI., APL 84 (2004) 613. 7)
H. W. Van Zeij et aI., Proc. Int. Conf. Solid-State and Integ. Circuit
Technol., (1998) 98. 8) S. Arulkumaran et aI., APL 88, (2006) 023502.
DP1.32
Effects of Neutron and Electron Irradiation on Electrical
Properties of GaN-based HEMT Structures A.Y. Polyakov
1
,
Nikolay n Srnirnov
l
, Anatoliy V Govorkov
l
, Elena A Kozhukhova
l
,
Stephen J Pearton
2
, Fan Ren
3
, Wayne J Johnson
4
, Wantae Lim
5
and
Nikolay G Kolin
6
; lInstitute of Rare Metals, Moscow, Russian
Federation; 2Department Materials Science Engineering, University of
Florida, Gainesville, Florida; 3Department of Chemical Engineering,
University of Florida, Gainesville, Florida; 4Kopin Corporation,
Taunton Massachusetts' 5GaN Power Research Group Samsung
LED, Korea, of; 6Karpov Institute of' Physical
Chemistry, Obninsk, Russian Federation.
AIGaN/AIN/GaN, AIGaN/GaN, InAIN/GaN HEMT structures on
sapphire and AIGaN/GaN HEMT structures on Si were irradiated at
room temperature with fast reactor neutrons and 10 MeV electrons.
Room temperature 2DEG concentration and mobility and room
ternperature and low ternperature C- V characteristics were rneasured.
It was found that the major effect was a decrease of mobility that
occurred at much lower fluences for AIGaN/AIN/GaN structures with
Al concentration in the barrier higher than 40
SESSION D2: Characterization of Nitride Electronic
Devices
Chair: Martin Kuball and David Meyer
Tuesday Morning, August 27, 2013
Chesapeake 4-6
8:30 AM D2.01
On the Origin of Surface Trapping Effects in AIGaN/GaN
HEMTs. Feng Gao and Tomas Palacios; EECS, MIT, Cambridge,
Massachusetts.
GaN-based high electron mobility transistors (HEMTs) are very
promising candidates for the next generation of high power and high
frequency electronics. However, trapping effects have been one of the
most important barriers in the development of the GaN semiconductor
since its infant tirne. In recent years, significant research efforts have
been focused on understanding and suppressing trapping effects in
AIGaN/GaN HEMTs [1]. Many of these effects have been linked to
surface traps and they have been mitigated by using passivation
layers, such as silicon nitride [2]. The physical origin of these surface
traps is however not clear yet. In this work, we propose that surface
trapping effects in AIGaN/GaN HEMTs are mainly caused by
water-related electron traps on the device surface. Both theoretical
and experirnental evidence is provided. Firstly, we show that adsorbed
water on the III-N surface cannot be fully removed by vacuum
pumping at room temperature (RT). In fact, it is well known in Si02
surface chemistry that hydrogen-bonded water monolayers cannot be
removed by just pumping in vacuum at RT. Thermal annealing in
vacuurn above 200 0 C are needed [3]. We thus carry out in-situ X-ray
photoelectron spectroscopy (XPS) analysis on the AIGaN surface
before and after the vacuum annealing. The sample was initially
by XPS at RT, then annealed at 300C for an hour, cooled
down to RT and subsequently analyzed by XPS again without
breaking the vacuurn. The signature of the adsorbed water - hydroxyl
group (OH-) is significantly reduced on the AIGaN surface after the
vacuum annealing at 300 0 C. Secondly, we conduct in-situ pulsed I-V
measurements on unpassivated AIGaN/GaN HEMTs annealed at
different ternperatures in vacuurn to directly link the desorption
process to the trapping transients, such as current collapse and
dynamic on-resistance. By annealing in vacuum above 250C and
subsequent in-situ pulsed I-V measurements at RT, we find that the
current collapse and the dynamic on-resistance of unpassivated
AIGaN/GaN HEMTs arc significantly suppressed. Moreover, this
behavior is reversible, which means that as soon as the AIGaN surface
is exposed back to ambient air and re-adsorbs water molecules from
moisture, the trapping transients come back to their initial levels.
Thirdly, we show that the water molecules from ambient air can also
be adsorbed on SiN passivation surface and cause trapping transients
dependent on the thickness of the SiN layer. In addition, Teflon
passivation, as a hydrophobic material, has been found to excellently
suppress the trapping transients in AIGaN/GaN HEMTs [4]. Last but
not least, to explain the nature of the water-related surface trapping
effects, we also propose an clectrochernical rnodel to describe how the
H20/H2 reduction-oxidation-reactions (redox) couple on the surface
of AIGaN/GaN HEMTs in ambient air. In conclusion, water molecules
in ambient air was identified as the origin of the surface trapping
effects and we believe it plays a key role in the dynarnic on-resistance
and drain current collapse of AIGaN/GaN HEMTs.
Acknowledgement: This project has been partially supported by the
Office of Naval Research (DRIFT MURI project, monitored by Dr.
Paul Maki). We also thank Prof. Harry L. Tuller for his lab
instrurnents and Prof. Carl V. Thornpson for his fruitful suggestions.
[1] S. C. Binari, et aI., Proc. IEEE, vol. 90, no. 6, pp. 1048-1058, 2002.
[2] B. M. Green, et aI., IEEE Electron Device Lett., vol. 21, no. 6, pp.
268-270, 2000. [3] L. T. Zhuravlev, Colloids Surf. A, vol. 173, no. 1-3,
pp. 1-38,2000. [4] F. Gao, et aI., IEEE Electron Dev. Lett., vol. 33,
no. 10, pp. 1378-1380, 2012.
8:45 AM D2.02
Spatially-Resolved Spectroscopic Measurements of Eo - 0.57
eV Buffer Traps in AIGaN/GaN High Electron Mobility
Transistors. Drew Cardwell
l
, Anup Sasikurnar
2
, Aaron R. Arehart
2
,
Stephen W. Kaun
3
, Jing Lu
3
, Jim S. Speck
3
, Stacia Keller
3
, Umesh
K. Mishra
3
, Steven A. Ringel
2
and Jon P. Pelz
1
; Iphysics, The Ohio
State University, Columbus, Ohio; 2Department of Electrical and
Cornputer Engineering, The Ohio State University, Colurnbus, Ohio;
3Materials & Electrical and Computer Engineering Departments,
University of California, Santa Barbara, California.
GaN-based high electron mobility transistors (HEMTs) offer high
frequency, high power perforrnance, but their perforrnance and
reliability are still limited by electrically-active defects. Knowledge of
the spatial distribution of specific traps and their impact on device
performance is important for understanding degradation in
AIGaN/GaN HEMTs. Recent macro-scale trap spectroscopy
rneasurernents on Ga-face HEMTs grown by rnetalorganic chernical
vapor deposition (MOCVD) have shown a trap with energy 0.57 eV
below the conduction band (E,. - 0.57 eV), which causes
knee-walkout in pulsed I-V measurements, correlates with RF-stress
induced degradation, and is located in the drain access region [1].
Macro-scale trap spectroscopy techniques, which detect changes in
transistor output characteristics, can be sensitive to all trapped
charge near the two dimensional electron gas (2DEG) channel, making
it difficult to distinguish between traps above the 2DEG (in the
AIGaN barrier or at the surface) and traps below the 2DEG (in the
GaN buffer). Previously, scanning Kelvin probe microscopy
measurements of nm-scale surface potential transients (SPTs) have
shown trapped electrons located above the 2DEG in the drain access
region within several hundred nanometers of the gate edge [2, 3].
These rneasurernents, however, were not spectroscopic, and therefore
could not identify particular traps or distinguish between different
trap emission mechanisms. In this work, we perform simultaneous
measurements of resistance transients (TITs) and SPTs as a function
of temperature on a set of MOCVD AIGaN/GaN HEMTs. Surface
potential transients were rneasured above the AIGaN barrier in the
drain access region and off the edge of the AIGaN barrier over exposed
GaN. By comparing RTs with SPTs, we find that the Eo - 0.57 eV
traps are located in the GaN buffer and not in the AIGaN barrier or
250
at the surface in the drain access region. Additionally, measurements
on devices with different distances, d, between the 2DEG channel and
the Fe-doped layer of the GaN buffer show that the impact of the E,
- 0.57 eV trap on RT amplitudes increases as d decreases, also
suggesting that the E, - 0,57 eV trap is located in the buffer and is
related to the incorporation of Fe, though its physical origin remains
unclear and is a topic of further study. A comparison of measured RTs
and sirnulations of the electric fields, suggest that filling of the E
c
-
0.57 eV trap occurs when leaked electrons, likely originating from the
gate, can be forced down into the GaN buffer by vertical electric fields
in the GaN buffer. [1] A.R. Arehart, A. Sasikumar et aI., Solid State
Electronics, 80, 19 (2013). [2] G. Koley et aI., IEEE Trans. On
Electron Dev., 50, 886 (2003). [3] D.W. Cardwell et aI., Appl. Phys.
Lett, 100, 193507 (2012). Work supported by the ONR (P. Maki)
including support from the Design-for-Reliability Initiative for Future
Technologies (DRIFT) MURI.
9:00 AM D2.03
Interface Charge and Electron Transport in GaN-Based
MIS-HEMTs. Ting-Hsiang Hung, Sriram Krishnamoorthy, Digbijoy
N. Nath, Pi! Sung Park and Siddharth Rajan; Electrical & Computer
Engineering, The Ohio State University, Colurnbus, Ohio.
Metal-insulator-semiconductor high electron mobility transistors
(MISHEMTs) based on the III-Nitride system can efficiently suppress
gate leakage enabling lower gate-channel spacing for high frequency
transistors, and low off-state leakage for power switching devices.
Recent workl-3 revealed a high density of fixed charges of the order of
1 J-tC/cm2 at the interface of atomic layer deposited (ALD) dielectrics
on GaN and AIN. The dielectric/semiconductor interface charges act
as rernote irnpurity scattering center that can significantly lower the
mobility of 2DEG4.. In this work, we investigate experimentally and
theoretically, the effect of interfacial charges on transport by varying
the charge density (through post-metallization anneal, PMA) and
interface-2DEG distance. A commercially obtained HEMT (29 nm
AlO.3GaO.7N/l nm AIN/GaN) grown on Si substrate (NTT Inc) was
used in this study. To investigate the effect of interface-channel
distance, the AlO.3GaO.7N layer was recessed to different thicknesses
using ICP-RIE. 15nm ALD Al203 was deposited as gate dielectric,
followed by a Ni/ Au/Ni gate. PMA was done under 5% H2 ambient
froITI 400C to 500C. We rneasured drift rnobility using a cornbination
of gated TLM and C- V measurements. In each case, the experimental
mobility was compared to theoretical mobility, and remote impurity,
phonon, surface roughness and dislocation scattering were considered.
The mobility of non-recessed MISHEMT matched the theoretical
prediction, with a mobility of 1600 cm2V-ls-l at low 2DEG density
regime (2xl012 cm-2). For the 16 nm AIGaN cap layer MISHEMT,
the mobility at low 2DEG density was lower than the unrecessed (30
nm cap) sample, and was found to be 1000 cm2V-ls-l which is due to
rernote irnpurity. The rnobility drop in deeper recessed MISHEMT
(13nrn, 6nrn and 5nrn AIGaN cap) is even rnore substantial (below 500
cm2V-ls-l) at low 2DEG density. This experimental results show the
effect of remote impurity scattering is larger than we expected from
the theory. After PMA, interface charges decrease, and as expected
froITI theory the rnobility increases at low 2DEG density for all cases,
and saturates at higher temperature PMA, which provides an evidence
of the interface charges reduction. The positive direction of threshold
voltage shift from C- V measurement with different PMA temperature
also shows the interface charges decrease. In conclusion, we have
shown experirnental evidence of the effect of dielectric/serniconductor
interface charges on electron transport, and that these interface
charges can be engineered by PMA. This study provides important
information for high frequency and power devices based on
dielectric/III-nitride semiconductor interfaces. (This work was funded
by the ONR DEFINE MURI NOOOI4-10-1-0937) 1 M. Esposto, et aI.,
Appl. Phys. Lett., 99, 133503 (2011) 2 J. Son, et aI., Appl. Phys. Lett.
101, 102905 (2012). 3 S. Ganguly, et aI., Appl. Phys. Lett., 99, 193504,
(2011) 4 T.-H. Hung, et aI., Appl. Phys. Lett., 99, 162104 (2011)
9:15 AM D2.04
Identification of a Mid-Gap State Driven Degradation
Mechanism in Operational AIGaN/GaN HEMTs Using
Constant Drain Current Deep Level Thermal and Optical
Spectroscopies. Anup Sasikurnar
1
, Aaron R. Arehart
l
, Brian
Poling
2
, Eric Heller
3
, Glen D. Via
4
and Steven A. Ringel
1
; lElectrical
and Computer Engineering, The Ohio State University, Columbus,
Ohio; 2Wyle , Dayton, Ohio; 3Materials and Manufacturing
Directorate, Air Force Research Laboratory, Wright-Patterson Air
Force Base, Ohio; 4Sensors Directorate, Air Force Research
Laboratory, Wright-Patterson Air Force I3ase, Ohio.
Trap spectroscopy was performed on operational S-band HEMTs
before and after RF accelerated life testing (ALT) and a RF output
power (Pout) degradation mechanism was identified that is triggered
by formation of mid-gap states This aging
mechanism is different from that identified in X-band HEMTs from
previous studies where Pout degradation was linked primarily to
formation of an Ec-0.57eV trap. Not only was the Ec-0.57eV
unimportant in the degradation in these HEMTs, it was hardly
detected pre-ALT possibly because of the low gate leakage Ie (10-8
A/mm). Trace quantities of the Ec-0.57 eV were however detected
post-ALT when the gate leakage showed large increase
suggesting that high Ie (>10-
7
A/mm) may be required for its
detection and participation in degradation. The trap characterization
was performed using constant current deep level transient loptical
spectroscopy (CID-DLTS/DLOS). The CID-DLTS methods rely on
therrnal-stirnulation of electrons to probe levels within Ecrv1eV. The
optical-stimulation based CID-DLOS uses sub-bandgap
monochromatic light to probe levels in the rest of Ee. The
CID-DLTS/DLOS is performed in two modes, namely:
drain-controlled (probes drain-access traps) and gate-controlled
(probes under-gate traps) rnodes. The HEMTs here were subjected to
ALT with baseplate temperature Tbp=150C, Pin=21dBm, quiescent
V Ds=40V, f=3.5GHz until a Pout drop was observed at
Tbp=60C after h. No change in V
T
was observed post-ALT.
The absence of VT-shift rules out forrnation of under-gate traps, and
so gate-controlled mode results are not presented. A rv8% increase in
static ON-resistance RON was observed post-ALT. Suspecting
drain-access traps, drain-controlled CID-DLTS/DLOS was performed
pre and post-ALT. Before stressing, the drain-controlled CID-DLTS
revealed just one trap of energy Ec-0.75eV. What is striking is the
absence of the Ec-0.57eV signature which has been widely detected
by different groups in multiple X-band GaN HEMTs. Post-ALT, the
Ec-0.57eV trap appears as a small shoulder while the Ec-0.75eV
6RD shows a slight increase. The appearance of the E
c
-0.57eV trap
post-ALT correlates with a large increase in gate leakage (by
That said, this mild increase in the Ec-0.57eV cannot explain
the IdB Pout drop. Suspecting deeper traps, drain-controlled
CID-DLOS was performed and a significant increase in 6RD was
observed especially from states between eV. The role of
these rnid-gap levels is differentiated froITI the CID-DLTS-detected
traps using lighted-IV measurements. Shining 1.2eV light had little
effect on the RON suggesting that the Ec-0.57 and Ec-0.75eV traps
were not significant in this HEMT. However shining 3eV light had a
strong irnpact on the RON which recovered to the sarne low resistance
case pre and post-ALT. This suggests that the rnid-gap trap
formation is the most likely source of Pout degradation in these
HEMTs. Details of the methods and full analysis will be presented.
9:30 AM D2.05
Improved Current Stability in Multi-Mesa-Channel
AIGaN/GaN Transistors. Joel T. Asubar
,
,2, Kota Ohi
'
, Kenya
Nishiguchi
'
and Tamotsu Hashbume
,
,2; 'RCIQE, Hokkaido
University, Sapporo, Japan; 2J ST -CREST, Tokyo, Japan.
In spite of their promise, the widespread adoption of GaN-based
transistors is still hampered by stability issues particularly by the
well-known current collapse. In our laboratory, we have been using the
device structure-based approach to circurnvent these stability issues.
Using a top-down technique, we have been developing the
multi-mesa-channel (MMC) AIGaN/GaN HEMT, which is fabricated
in a way so that periodic parallel mesa-shaped channels separated by
trenches would be the end product. In this work, a metal-organic
chemical vapor deposition (MOCVD)-grown AIGaN/GaN
hetero-structure on sapphire substrate was used as the starting wafer.
First, a Si02 mask was patterned on the AIGaN/GaN structure by
electron beam lithography and wet etching. Reactive ion-beam etching
(RIBE) was then carried out to form the periodic trench. After that,
ohmic electrodes were formed by depositing Ti/Al/Ti/Au metal stack
followed by rapid thermal annealing at 800C for 1 min. Next, Ni/Au
electrodes were deposited to form the Schottky gates. Finally, a 20 nm
thick Al 2 0
3
was deposited by atomic layer deposition (ALD) as a
passivation layer. The MMC device exhibited good subthreshold
characteristics with a typical subthreshold swing of 76 rnVIdee and
drain-induced barrier-lowering (DIBL) in the 10 mV/V range. The
unique structure of the MMC HEMT facilitates channel modulation
through the mesa-side walls. Calculations of the 2D potential
distribution around the channel region revealed that decreasing W top
strengthens the potential modulation through the undoped GaN layer.
Because of this surrounding field effect, the gate has strong control
over the channel potential, resulting into the reduced DIBL. We have
also performed pulsed I-V measurements under two quiescent bias
conditions, Q, = (VDS_ba,e, YeS_base) = (OV, OV) and Q2 =
(VDS_ba'c, Ves_ba,c) = (20V, -6V) to investigate the dynamic
behavior of the MMC device. The quiescent point Q2 was so chosen to
induce current collapse on the devices. The planar device exhibited
severe current dispersion between the two quiescent bias points Ql
and Q2. In cornparison, the MMC device showed insignificant current
reduction from Q1 to Q2' It is widely believed that current collapse is
due to increase in access resistance as a result of surface charging
induced by the bias stress. The MMC device appears to be insensitive
to changes in access resistance induced by the bias stress and thus
irnrnune to current collapse. On the basis of the above results, it is
likely that the unique structure of the MMC device, particularly its
251
periodic mesa-shaped nano-channels, allows highly stable operation
and immunity against current collapse. These properties make the
MMC device an attractive prospect for low-loss high stability power
applications.
9:45 AM D2,06
Direct Observation of the Relationship between Gate Edge
Failure Sites and Threading Dislocations on AIGaN/GaN
HEMTs. Miguel Montes Bajol, G. Naresh-Kumar
2
, Carol
Trager-Cowan
2
, Michael J. Uren
1
and Martin Kuball
1
; 1 Center for
Device Thermography and Reliability (CDTR), H. H. Wills Physics
Laboratory, University of Bristol, Bristol, England, United Kingdom;
2DcpartrIlcnt of Physics, SUPA, University of Strathclydc, Glasgow,
Scotland, United Kingdorn.
The gate current (Ig) of AIGaN/GaN high electron mobility
transistors (HEMTs) is known to degrade when the gate contact is
reverse biased. Such a degradation of Ig correlates to the appearance
of electroluminescence (EL) hot spots and the formation of pits on the
semiconductor surface, indicating the location of the Ig leakage paths
[1-4]. The presence of point defects [2] and threading dislocations
(TDs) [5] in the semiconductor is thought to have an impact on this
degradation, but no direct evidence for it has been provided so far.
The relationship between TDs and failure sites in AIGaN/GaN
HEMTs is studied here by correlating surface pits and TDs using
atomic force microscopy (AFM) and electron channelling contrast
imaging (ECCI). The results highlight that some of the failure spots
are related to TDs in the AIGaN/GaN HEMTs, drawing attention to
the need to manage TDs impact on AIGaN/GaN HEMT reliability.
AIGaN/GaN HEMTs grown on SiC, were stressed at Vgs = -15 V and
Vds = 30-50 V. Stress resulted in the usual step-like increase of Ig
and the associated emergence of EL spots near the gate edge. The
associated surface pits were subsequently located with AFM after the
chemical removal of the contacts and passivation. ECC images of the
surface pits identified by AFM were then acquired. ECCI enables the
identification of TDs, which are revealed as features with a distinct
black-white (13- W) contrast whose orientation reflects the strain
distribution due to the presence of a TD [6J. In particular, the 13-W
direction of edge TDs either remains the same or rotate by 180
degrees on changing the channelling conditions due to the
tensile-compressive strain distribution across the edge dislocation,
enabling the use of ECCI to distinguish surface pits associated with
TDs from surface pits without TDs underneath For a TD-associated
stress pit, two contributions to the contrast are observed in the ECC
image: that due to the strain distribution of the TD and the strain
distribution/topography due to the pit itself. The behaviour of the
13-W contrast froul a nurnber of failure spots under different
channelling conditions was analysed. It was found that some of the
device failure spots behave consistently with the presence of an edge
dislocation. These results highlight the importance of TDs on the
reliability of AIGaN/GaN HEMTs. [1] R . .1. Trew et al. IEEE Microw.
Mag. 10, 116 (2009) [2] M. Meneghini et al. Appl. Phys Lett. 100,
033505 (2012) [3] M. Montes Baja et al. Appl. Phys. Lett. 101, 033508
(2012) [4] J. Joh et al. Microelectron. Reliab. 51, 201 (2011) [5] M.
Tapajna et al. Appl. Phys. Lett. 99, 223501 (2011) [6] G.
Naresh-Kumar et al. Phys. Rev. Lett. 108, 135503 (2012)
10:30 AM D2.07
Distribution of Built-in Electric Field in AlGaN/GaN
Transistor Heterostructures: The Role of Surface States.
Marta Gladysiewicz
1
, Robert Kudrawiec
l
, Jan Misiewicz
l
, Grzegorz
Cywinski
2
, Pawel Prystawko
2
and Czeslaw Skierbiszewski
2
; lInstitute
of Physics, Wroclaw University of Technology, Wroclaw, Poland;
2Institute of High Pressure Physics, Polish Academy of Science,
Warsaw, Poland.
Large piezoelectric and spontaneous polarization in hexagonal
III-nitrides leads to very strong built-in electric field in AIGaN/GaN
heterostructures when they are grown along the polar direction. It is
well known that the electric field distribution in such heterostructures
and the concentration of two dimensional electron gas depend on
content and thickness of AIGaN layer. However, these quantities also
depend on the boundary conditions [1] that is very often neglected. It
means that the Schrodinger and Poisson equations have to be solved
with the real boundary conditions for this material systems.
Unfortunately such conditions not always are obvious and known, but
they can be quite precisely deterInined if theoretical calculations are
compared and matched with measurements of electric field in
AIGaN/GaN heterostructures [1]. This field can be measured using
electromodulation spectroscopy (electroreftectance or
photoreflectance). In this work the electric field distribution was
studied theoretically and experimentally for AIGaN/GaN
heterostructures with various thickness of AIGaN layer, different
thickness of GaN(cap) layer, with and without AIN layer, and
different surface passivation by dielectric layers like SiN. The samples
were grown by rnolecular beaIn epitaxy and Inetalorganic vapor phase
epitaxy on c-plane sapphire substrates. Optical transitions related to
absorption in GaN(cap) and AIGaN layer were clearly observed in
electromodulation spectra. The built-in electric field in AIGaN layer
was deterInined froIll the analysis of AIGaN-related Franz-Keldysh
oscillation. In this experimental investigation it was clearly observed
that the built-in electric field in AIGaN layer decreases with the
increase of AIGaN layer thickness and increases with the increase in
thickness of GaN(cap) layer. In addition, it was found that the
incorporation of thin AIN layer (0.8-1.5nIn) into this heterostructure
at the AIGaN/GaN interface very significantly reduces the built-in
electric field in AIGaN layer. The founded changes in built-in electric
field are in very good agreement with theoretical predictions obtained
fronl solving Schrodinger and Poisson equations with the saUle surface
boundary condition, i.e., the pinning of FerIni level ",0.5 eV below the
conduction band. In addition, it was observed that surface passivation
is able to change this condition very significantly. [1] M. Gladysiewicz
et aI., Appl. Phys. Lett. 98, 231902 (2011).
10:45 AM D2.08
Leakage-Current Reduction and Improved On-State
Performance of Au-Free AlGaN/GaN-on-Si Schottky Diode
by Embedding the Edge Terminations in the Anode Region.
Jie Hu
l
,2, Silvia Lenci
l
, Steve Stoffels
l
, Brice De Jaeger
1
, Guido
Groeseneken
2
,3 and Stefaan Decoutere
1
; IpMST, imec, Heverlee,
Belgium; 2 ESAT-MICAS, Katholieke Universiteit Leuven, Heverlee,
Belgium; 3DRE, imec, Heverlee, Belgium.
AIGaN/GaN-on-Si Schottky diodes are attractive for high-power
applications owing to the properties of fast-switching speed and large
breakdown field strength. To achieve low static power losses for the
diode, a low reverse current and low forward voltage drop are
required, furtherInore the diodes should have a high breakdown
voltage. Schottky junction terminations are known to suppress the
leakage current[l], and Schottky diode recess was reported to reduce
on-state voltage[2]. In this work we have optimized, simultaneously,
the reverse leakage current and forward voltage drop of Au-free
AIGaN/GaN Schottky I3arrier Diodes (SI3Ds) on Si by investigating
the diode topology and different anode recess conditions. Au-free
AIGaN/GaN SBDs have been processed on GaN-on-Si (8 inch) wafers
with a metal stack of TiN/Ti/AI/Ti/TiN as the Schottky metal. We
fabricated and cOInpared several diode topologies on the saIlle wafer,
namely External Edge Termination-SI3Ds (EET-SI3Ds) with an edge
termination located beside the Schottky contact at a distance LSDG,
compact Gated Edge Termination-SBDs (GET-SBDs), and
conventional SBDs. In the case that recess was applied, the 17 nm
thick AIGaN barrier was recessed to 5 mn (using a I3C13 RIE process)
in (part of) the anode region for both EET-SBD and GET-SBD
architectures. We have found that, by reducing the dimension of
LSDG, the leakage current in EET-SBD can be reduced, and more
importantly a drop of four orders in magnitude (as compared to the
conventional SBDs) can be achieved by eInbedding the edge
termination inside the anode trench as in the GET-SBD architecture.
The reduction can be achieved without adversely affecting the on-state
characteristics. The forward voltage (i.e. at lAC =O.IA/mm) of the
GET- SBD architecture can be significantly improved from 1.5 V to
1.2 V by recessing the anode, while at the saUle tiIne reducing the
spread on the leakage current. For all diode topologies, a breakdown
voltage over 600V was achieved for an LAC (spacing between Anode
and Cathode) of 10 !"m. In conclusion, low forward voltage VF = 1.2
V and low leakage current ILeakage = 1 !"A/mm at VAC of -600 V for
Au-free AIGaN/GaN SI3Ds have been achieved by embedding edge
terminations in recessed anode trench. [1] Z. He, "Gated AIGaN/GaN
heterojunction schottky device", United States Patent Application
Publication, No. US 2011/0133251, (2011). [2] .I.-G. Lee, B.-R. Park,
C.-H. Cho, K.-S. Sea, and H.-Y. Cha, "Low Turn-On Voltage
AIGaN/GaN-on-Si Rectifier With Gated Ohmic Anode", IEEE
Electron Device Lett. , vol. 34, no. 2, pp. 214-216, Feb. 2013.
11:00 AM D2.09
Plasma Treatments to Block Parasitic Isolation Leakage in
InAI(Ga)N HEMTs. Ronghua Wang
1
, Guowang Li
1
, Oleg
Laboutin
2
, Yu Ca0
2
, Wayne Johnson
2
, Debdeep Jena
1
and Huili G.
Xing
1
; lElectrical Engineering, University of Notre Dame, Notre
Dame, Indiana; 2 IQE KC LLC, Taunton, Massachusetts.
Device background leakage due to poor isolation can cause prernature
breakdown and additional noise in transistors, which is detrimental
for high-power and low-noise applications. In this work, we report a
scheme employing F -containing plasma treatments to successfully
block leakage paths induced during mesa etch. The
InO.13AIO.83GaO.04N ~ 1 nm)/AIN (1 nm)/GaN HEMT structure
was grown on SiC substrate by MOCVD. The measured 2DEG
density after ohmic annealing slightly drops as a function of annealing
temperature; while the buffer leakage current increases. The fact that
devices with non-alloyed ohInics show Inore than three orders of
Inagnitude lower leakage current suggests that the therInal process is
most likely responsible for the parasitic isolation leakage current.
Comparative studies of mesa-first and ohmic-first device processing
252
with alloyed ohmics were carried out to investigate the origin of the
parasitic leakage current. It turns out that the mesa-first processing
associated high buffer leakage current can be suppressed by either an
additional CF4 plasma treatment following ohmic annealing or a
fabrication sequence change to the ohmic-first processing.
Experimental results suggest that the ohmic annealing generated
defective surface plays a dominant role in parasitic conduction in the
etched rncsa area under low field 0.3 MVJerrI); dry etching induced
defects, exacerbated by high temperature ohmic annealing, are
responsible for the premature buffer breakdown, and the CF4 plasma
treatment can effectively passivate the defective surface and improve
the buffer breakdown filed to 0.5 MV/cm.
11:15 AM D2.IO
Static and Transient Characteristics of GaN Power HFETs
with Low-Conducting Coating. Mikhail Gaevski', Jianyu Deng',
Alex Dobrinskyl, Rcrnis Gaska1, Michael Shllr
2
and Grigory Sirnin
3
;
ISensor Electronic Technology Inc., Columbia, South Carolina;
2Rensselaer Polytechnic Institute,logy Inc., Troy, New York;
3University of South Carolina, Columbia, South Carolina.
A low-conducting layer (LCL) coating on the surface of III-N HFETs
dramatically improves the electric field uniformity and increases the
breakdown voltage. In this paper, we report on the results of the
analytical model, 2D simulations, and experimental characterization
of the power III-Nitride HFETs with different LCLs. Our results show
that, in a static regime, the LCL over the gate-to-drain spacing
enables a quasi-linear potential profile and, as a consequence, induces
a quasi-uniform charge depletion in the 2D-channel. In a transient
regime, the LCL and HFET channel separated by a barrier layer
behave as a nonlinear resistive - capacitive translnission line. The
characteristic impedance and propagation constant of this
transmission line define the key characteristics of the switching mode
of operation. The interface charges between the LCL and the barrier
strongly affect the space charge distribution in the HFET channel and,
therefore, the breakdown voltage and HFET switching characteristics.
11:30 AM D2.11
Investigation of Individual Leakage Current Path in n-GaN
by Conductive-Atomic Force Microscope. BUInho Kiln
l
, Dae
Young Moon
2
, Kisu .100
3
, Sung Hyun Park
4
, Sewoung Oh
4
, Gun-Do
Lee
4
, Youngkuk Lee
5
, Yasushi Nanishi
2
,6, Youngboo Moon
l
, Yongjo
Park
l
and Euijoon Yoon
l
,2,4; lEnergy Semiconductor Research
Center, Advanced Institute of convergence Technology, Suwon,
Gyeonggi-do, Korea, Republic of; 2W CU Hybrid Material Prograln,
Department of Materials Science and Engineering, Gwanak-gu, Seoul,
Korea, Republic of; 3Department of Nano Science and Technology,
Graduate School of Convergence Science and Technology, Suwon,
Gyeonggi-do, Korea, Republic of; 4Departlnent of Materials Science
and Engineering, Seoul National University, Gwanak-gu, Seoul, Korea,
Republic of; 5 Korea Research Institute of Chemical Technology,
Yuseong-gu, Daejon, Korea, Republic of; 6Department of Photonics,
Ritsumeikan University, Kusatsu, Japan.
In recent years, GaN has been an important material for optical and
electrical devices [1, 2]. It is well known that leakage current is still
one of the critical factors limiting the performance and reliability of
GaN-based light-emitting diodes and electrical devices. Brazel et al.
[3] have observed threshold voltage decreased at threading
dislocations with screw component (pure screw and mixed) in GaN
grown by MOCVD. However Shiojima et al. [4] suggested that mixed
dislocations did not affect I-V characteristics in Schottky contact
between platinum and n-GaN grown by MOCVD. It was also reported
that only pure screw dislocations arc responsible to reverse-bias
leakage current in GaN grown by MBE [5, 6]. In previous reports, the
origin of leakage current path was proposed. However, the precise
electrical characterization of individual leakage current path has not
been reported yet. In our study, we investigated leakage current paths
in n-GaN by using conductive-atolnic force Inicroscope (C-AFM),
focusing on conducting behavior of individual leakage current path in
n-GaN. The experiments were performed on silicon doped n-GaN film
~ 5xIOI8 cm-3, 3-um thick) on undoped GaN buffer layer (2-um
thick) on c-plane sapphire grown by MOCVD. We confirmed that
there were three kinds of leakage current path: large pit, pure screw
dislocation, and step edge by using C-AFM. We measured local I-V
curve to analyze the individual leakage characteristics. To investigate
the origin of leakage current path, defect selective etching analysis
and translnission electron Inicroscope (TEM) were perforrned. We
confirmed that the large pits acting as conductive channel were
open-core screw dislocation by using defect selective etching and TEM
analysis. REFERENCES [1] H. Morkoc, Nitride Semiconductors and
Devices (Springer, Heidelberg, 1999) [2] S. Nakamura and G. Fasol,
The Blue Laser Diode (Springer, Berlin, 1997) [3] EG Brazel, MA
Chin, and V. Narayanamurti, Appl. Phys. Lett. 74, 2367 (1999) [4]
JWP Hsu, MJ Manfra, RJ Molnar, B. Heying, and JS Speck, Appl.
Phys. Lett. 81, 79 (2002) [5] BS Simpkins, ET Yu, P. Waltereit, and
JS Speck, J. Appl. Phys. 94, 1448 (2003) [6] K. Shiojima, T.
Suemitsu, and M. Ogura, Appl. Phys. Lett. 78, 3636 (2001)
11:45 AM D2.I2
SysteITlatic DeterITlination of Interface States and Charge
Trapping PhenoITlenon in AlGaN/GaN MOS-HEMT Gate
Stacks. Derek W. Johnson', Iman Rezanezhad-Gatabi', Jung-Hwan
WOOl, Kyoung-Keun Lee
2
,1, Edwin L. Piner
2
and H. Rusty Harris
l
;
lElectrical and Computer Engineering, Texas A&M University,
College Station, Texas; 2Departlnent of Materials Science,
Engineering, and Commerciali:z;ation, Texas State University, San
Marcos, Texas.
A systelnatic analysis of charge trapping at interfaces in AIGaN/GaN
MOS-HEMT devices is presented in this paper. In order to
understand the charge trapping on such a complicated structure,
differential understanding of interface state characterization is
performed on Schottky-gated HEMT devices with no gate dielectric,
and the result is correlated to the understanding of the saIne
heterostructure with a high k dielectric inserted. For the
Schottky-gated HEMT devices, successively thinned AIGaN using
plasma etching is performed and the response of expected deep traps
is examined. It is found that the surface etch-related defects do not
significantly contribute to the conductance spectroscopy, and that
2DEG interaction with traps is very similar to a Nicollian-Brews
model whereby the frequency-dependent capture/emission of charge
from the 2DEG occurs in the AIGaN near the interface [1]. Next, this
result is differentially correlated with the same heterostructure with
Atomic Layer Deposited (ALD) Hf02 high-ti: dielectric. It is found
that two distinct frequency-dependent conductance phenomena can be
isolated, and these are attributed to (1) near-2DEG AIGaN/GaN
interface trapping and (2) conduction-edge dielectric/ AIGaN charge
traps. A modified Nicollian-Brews model is presented that completes
the understanding of conductance spectroscopy deterrnination of
interface states. Finally, the Hf02/ AIGaN traps are found to be
persistent, with long capture time constant. Similar gate stacks
integrated into an MOS-HEMT transistor with Au-free contact
technology indicates that this Inajor charge trapping produces a shift
in threshold voltage to enhancelnent Inode operation. This trapping
and operational shift is similar in nature to recent reports on
enhancement mode memory-like operation of GaN HEMTs [2,3].
Analysis of the Hf02 interaction with AIGaN shows a clear interface
forrnation, consistent with literature [3], and that the interface has
Ga-ON (Ga 1+) bonds that can trap charge. [4,5] [1] E. H. Nicollian
and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and
Technology, Wiley Classics Library ed. Hoboken, New Jersey: John
Wiley & Sons, Inc., 2003. [2] D. W. Johnson, et aI., "Threshold
Voltage Shift due to Charge Trapping in Dielectric-Gated
AIGaN/GaN High Electron Mobility Transistors Examined in Au-Free
Technology," IEEE Transactions on Electron Devices, Submitted for
Publication. [3] Lee, 13, et ai, Phys. Status Solidi C, 9: 868-870
(2012). [3] M. R. Coan, et aI., "Band offset measurements of the
GaN/dielectric interfaces," Journal of Applied Physics, vol. 112, 2012.
[4] R. D. Long, et aI., "Temperature-dependent capacitance-voltage
analysis of defects in Al203 gate dielectric stacks on GaN," Applied
Physics Letters, vol. 101, 2012. [5] P. Kordos, et aI., "Trapping effects
in Al203/ AlGaN/ GaN Inetal-oxide-selniconductor heterostructure
field-effect transistor investigated by telnperature dependent
conductance measurements," Applied Physics Letters, vol. 96, pp.
013505-013505-3, 2010.
SESSION D3: Substrates and Epitaxial Integration for
Nitride Electronic Devices
Chair: Farid Medjdoub and Siddharth Rajan
Tuesday Afternoon, August 27, 2013
Chesapeake 4-6
1:30 PM D3.0I
AIGaN/GaN HEMTs Transferred froITl Sapphire Substrates
to Copper Plates Using Layered BN as a Released Layer.
Masanobu Hiroki, Kazuhide Kumakura, Yasuyuki Kobayashi, Tetsuya
Akasaka, Hideki Yalnalnoto and Toshiki Makilnoto; NTT Basic
Research Laboratories, NTT Corporation, Atsugi, Kanagawa, Japan.
GaN-based HEMTs are attractive for high-power device applications.
Layer structures of GaN-based devices are grown on various substrates
because affordable substrates lattice-Inatched to GaN arc unavailable.
Sapphire is widely used for the growth of high-quality nitride layers.
However, the performance of HEMTs on a sapphire substrate is
degraded by self-heating during their high-power operation owing to
low thermal conductivity of the substrates. Transferring the HEMTs
froln sapphire substrates to foreign substrates having higher therrnal
conductivity may overcome this problem. Recently, we have developed
a novel process for the release of GaN-based devices from the host
substrate and demonstrated that a thusly transferred LED preserves
its original perforrnance [1]. In the process, an extrelnely thin and
cleavable BN layer is inserted between the substrate and thin-filrn
253
device. In this study, we mechanically transferred AIGaN/GaN
HEMTs to a copper plate in a similar way to LEDs and investigated
their dc characteristics. We grew Alo.36Gao.74N(20 nm)/GaN(1.5
!-tm)/AIN(300 nm)/BN layers on sapphire substrates by MOVPE.
Hall-effect measurements yielded a sheet carrier density (N s) of 1.1 X
10
'3
cm-2 and an electron mobility of 700 cm
2
/Vs. First, we
performed mesa isolation by ICP etching. Next, we formed annealed
Ti/ AI/Ti/ Au source and drain electrodes and Ni/ Au gate electrodes
with the length of 1.5 !-tm. The HEMTs were subsequently released
froHI the sapphire substrates and indillln rnetal was electroplated OIl
the backside. Finally, we bonded the HEMTs to copper plates by
thermal fusion bonding. We measured the dc characteristics of the
HEMTs before the release from the sapphire substrates and after the
transfer to the copper plates. The transconductance was 80 InS/rurn,
and good pinch-off characteristics were obtained. No degradation due
to the mechanical transfer was observed in the I D- V DS and transfer
characteristics. A negative threshold voltage shift of -1.5 V and an
increase in drain current from 0.4 to 0.5 A/mm at V GS = 2 V for the
transferred HEMT indicate an increase in N s. This increase of N s
likely occurs because the epitaxial layer becomes strain-relaxed by the
transfer. The GaN layer grown on a sapphire substrate is under
in-plane compressive strain due to the difference in their thermal
expansion coefficients. The in-plane lattice constant of the GaN layer
rnight be restored to its inherent value after the transfer, leading to
an increase in tensile strain in AIGaN. As a result, strain-induced
piezoelectric polarization charge should increase at the AIGaN/GaN
interface. In summary, the first successful operation of mechanically
transferred AIGaN/GaN HEMTs indicates that our approach is
prornising for further irIlproving the perforrnance of the GaN- based
HEMTs towards high-power applications. [1] Y. Kobayashi eta!.,
Nature 484 (2012) 223.
1:45 PM D3.02
A1GaN/GaN HEMT Grown on Bulk AnlInonotherInal GaN
Substrate. Piotr Kruszewski
l
,2, Pawel Prystawko
l
,2, Irmantas
Kasalynas
3
, Jer:tiy Plesiewc:ti
2
, Robert Dwilinski
4
, Marcin Zajac
4
,
Robert Kucharski
4
and Michal Leszczynski 1.2; 'Institute of High
Pressure Physics, PAS, Warsaw, Poland; 2 TopGaN Sp. z 0.0., Warsaw,
Poland; 3Center for Physical Science and Technology, Vilnius,
Lithuania; 4Ammono S.A., Warsaw, Poland.
In this study, we dernonstrate first working HEMT transistor of
AIGaN/GaN structure grown on bulk p-type GaN
substrate obtained by ammonothermal method [1]. Such
Ammono-GaN substrate is characterized by an ultra high purity and
dislocation density as low as 10
4
cm-2 [2]. The AIGaN and GaN
layers grown by MOVPE (Metalorganic Vapour Phase Epitaxy)
method reproduce this low dislocation density ensuring
simultaneously high uniformity and smoothness of AIGaN/GaN
interface such essential for high electron mobility in the HEMT's
channel. First, prior to HEMT device fabrication, the electron gas
channel properties of such grown HEMT structure were exarnined by
means of Hall effect studies. A temperature dependent measurements
have clearly shown that no parallel conduction in analyzed HEMT
structure exists. Two dimensional electron gas (2DEG) mobility
obtained from Hall experiments was in range of 1500 cm
2
/Vs (300K)
and 8000 cm
2
/Vs (77K) for electron concentration of 8xl0
'2
cm-
2
.
The transistors were fabricated of as grown 2DEG AIGaN/GaN by
dry rnesa etching. The test structures on the 1 inch p-type GaN wafer
were processed using standard photolithography with the gate si'e of
10x50!-tm
2
. For such fabricated HEMT, normal DC transistor
operation is observed with the pinch-off voltage of about -2.9V.
Moreover, transistor performance normalization to 50/-Lm gate width
provided the largest drain current up to 150rnA/rnrIl at Ucs=2V, and
maximum extrinsic transconductance up to 50mS/mm at U Ds=6V
and UGs=IV. Acknowledgements: This work was supported by the
PolHEMT Project under the Applied Research Programme of the
National Centre for Research and DeveloprIlent, Contract no.
PI3S1/A3/9/2012 and NANOTEC Project "Nanostructured materials
and RF-MEMS RFIC/MMIC technologies for highly adaptive and
reliable RF systems", Contract no. 288531. References: [1] R.
Dwilinski et a!., J. Crystal Growth 310, 3911 (2008). [2] R. Kucharski
et a!., Semic. Sci. Technology 27, 024007 (2012).
2:00 PM D3.03
High Electron Mobility Transistor Grown on Composite
Si/Polycrystalline Diamond Substrates by MOCVD.
Quanzhong Jiang
l
, Duncan W. Allsoppl, Chris R. Bowen
l
, Wang N.
Wang
l
, Lugani Lorenzo
2
, Jean-francois Carlin
2
, Nicolas Grandjean
2
,
Mohammed Alomari
3
, Erhard Kohn
3
, Lajos Toth
4
, Bela Pecz
4
,
Rudolf Srnanek
5
, Alexander Satka
5
, Jaroslav Kovac
5
and Martin
Kuban
6
: 'Electronic Engineering, University of Bath, Bath, United
Kingdom: 2EPFL, Inst. Quantum Electronics and Photonics,
Lausanne, Switzerland; 3 Dept . of Electron Devices & Circuits,
University of Ulm, Ulm, Germany; 4Institute of Electronics and
Photonics, FEI STU, Bratislava, Slovakia; 5Institute for Tech. Phys.
And Mat. Sci. (MFA), MFA, Budapest, Hungary: 6School of Physics,
University of Bristol, Bristol, United Kingdom.
AIGaN/GaN and InAIN/GaN high-electron mobility transistors
(HEMTs) may operate at a high source-drain current (Isd) and a high
electric field for high-frequency and high-power applications and
therefore, require an efficient dissipation of heat for a stable
operation. So, integration of HEMTs on polycrystalline diamond, one
of the best therrnal conductors, would be one of the best options. This
paper reports properties of III-Nitride HEMTs grown on composite
silicon/polycrystalline diamond (Si/PD) substrates and their thermal
performance. The composite Si/PD substrates were formed by
depositing by CVD a 60 ,un thick PD layer on the 3 lun thick Si(111)
device layer of a custorIl silicon-on-insulator substrate, then selectively
removing the Si handle. Compared with Si(111), composite Si/PD
substrates are much stiffer at typical MOCVD growth temperatures
with the effect that after III-Nitride growth the substrate
curvature is largely unaffected by cornpressive stresses generated in
the GaN when grown on an AIN nucleation layer. As a result, the GaN
layers on Si/PD substrates have been shown to have a smaller critical
crack-free thickness compared to those grown on Si(111) substrates to
present a challenge in growing a HEMT buffer layer of comparable
quality to those grown for HEMTs on SiC or Si(I11) substrates.
Owing to the presence of the thin Si layer, the technique used to
generate compressive stress in the thin GaN buffer layers grown on
composite Si/PD substrates was similar to that employed for growing
thicker buffer layers on standard Si(111) substrates. The InAIN/GaN
HEMTs grown on the Si/PD substrate have advantages over
AIGaN/GaN hetero-junctions as an AIGaN layer would have to have a
much higher tensile stress due to the lattice mismatch with GaN, in
addition to the mismatch in the coefficient of thermal expansion of
nitrides and diamond. A sheet resistance of 710 ohm/square were
rIleasured froIll a hetero-structure consisting of InAlN
(5nm) / AIN(lnm) /GaN(200nm) / AIN(60nm) /Si(3!-tm) /PD(60!-tm).
Such a sheet resistance is higher than that of HEMTs grown on
Si(111) substrates, probably as a result of the GaN buffer layer being
insufficiently thick for a significant reduction in the dislocation
density to have occurred. However, the HEMTs exhibited a saturated
current density (IDSmax) of approximately 1 A/mm, and a pinch-off
voltage of -4 V. Although the devices could be pinched off with no
excessive gate leakage, the on/off ratio of the HEMTs was in the order
of 10,000, which indicates a buffer leakage of rv5 Il,A/rnrn and a need
to improve the quality of III-Nitride layers on Si/PD wafers. Despite a
thermal resistance (measured by Raman thermography) broadly
comparable to that of HEMTs-on-SiC, the devices are fully functional
with scope for optimization of the composite Si/PD substrates to
irnprove their heat extracting property.
2:15 PM D3,04
Wafer-Scale GaN HEMT Performance Enhancement by
Epitaxial Transfer onto Diamond Jonathan Felbinger
'
; J.
Blevins
l
, K. Chabak1, G. Jessen
l
, J. Gillespie
l
, R. Fitch
l
, A.
Crespo', K. Sutherlin
'
, B. Poling
3
, S. Tetlak
3
, R. Gilbert
3
, T.
Cooper
3
, R. Baranyai
4
, J. W. Pomeroy" M. Kuban
4
, J. J. Maurer
2
,
Avram Bar-Cohen
5
, Glen David Vial; 1 Air Force Research
Laboratory, Dayton, Ohio; 2 Booz Allen Harnilton, Arlington, Virginia;
3 Wyle Labs, Dayton, Ohio; 4Bristol University, Bristol, United
Kingdom; 5Defense Advanced Research Projects Agency, Arlington,
Virginia.
A wafer-scale cornparison of HEMTs fabricated on GaN/Si and
HEMTs fabricated in parallel on epitaxial layers transferred from a
sister wafer onto a diamond substrate will be presented. This work
was performed at the Air Force Research Laboratory (Dayton, OH) in
collaboration with the DARPA NJTT prograrIl. Diarnond offers the
highest roorn-ternperature therrnal conductivity of any bulk rnaterial.
In addition to its superior thermal properties, diamond offers good
electrical resistivity, a relatively low dielectric constant, and a high
degree of corrosion resistance and chemical inertness. Here, for the
first tirne, we present electrical and therrnal data collected at the
wafer scale demonstrating the improvement reali:z;ed by epitaxial
transfer to a high-thermal-conductivity substrate. This advances
previous demonstrations that have characterized the RF performance
of GaN-on-diamond [1], the full-wafer transfer [2] and characterization
[3] of GaN-on-diarnond, and a piece-scale electrical corIlparison
between GaN-on-diamond and native GaN-on-Si [4]. The epitaxial
layer design features a GaN cap, 20 nm AIGaN barrier, and !-tm
GaN buffer and transition layers grown atop a Si substrate. During
the epitaxial transfer process, the Si substrate is etched away, as are
the highly-disordered nucleation layer and dislocation-rich transition
layers. These layers serve as an impediment to efficient conductive
spreading of heat from the channel "hot spot" through the backside of
the substrate. Identical structures were fabricated using the AFRL
0.15 !-tm HEMT process. The submicron gates were formed by electron
bearn lithography, the dose was cornpensated for the difference in
material stack, and the mushroom-gate footprint was confirmed by
FIB/SEM analysis to be nominally 0.15 !-tm. Contact resistance for
the baseline and GaN-on-diamond devices were below 0.5 !1*mm and
254
sheet resistance was ......,425 n/sq, consistent with expectations. Overall,
the low-field device performance is very comparable with a slight
increase in the wafcr-scale avcrage of saturated drain current (froIn
0.70 A/mm to 0.81 A/mm) and transconductance (from 213mS/mm
to 238 mS/mm) resulting from the epitaxial transfer process and
consistent with the results reported in [4]. The thermally-induced
mobility-mediated reduction in drain current as drain bias increases
beyond the knee is strongly evident for thc devices on thc native Si
substrate. Large-signal results measured using on-wafer load-pull
indicate increased gain and PAE, consistent with lower operating
temperature. On-wafer temperature measurements were made using
IR and Inicro-RaInan techniques, both of which confirrn the decreased
therrnal resistance resulting froITl cpitaxial transfer. [1] Q.E. Diduck et
aI., 10.1049/eI.2009.1122 [2] D. Francis et aI.,
10.1016/j.diamond.2009.08.017 [3] K.D. Chabak et aI.,
10.1109/LED.2009.2036574 [4] J.G. Felbinger et aI.,
"AIGaN/GaN-on-Diamond HEMT Recent Progress", WOCSDICE,
M6Jaga, Spain, pp. 22-24, 17-20 May 2009.
2:30 PM D3.05
Characteristics of Monolithically Integrated LEDjPower
MOS Channel HEMT Pair in GaN with Selective Epi
Removal Approach. Zhongda Li
'
, John Waldron
,
,2, Theeradetch
Detchprohm
'
, Christian Wet7,el
'
, Robert F. Karlicek
'
and Paul
Chow
'
; 'Rensselaer Polytechnic Institute, Troy, New York; 2Silicon
Power Corporation, Clifton Park, New York.
We report thc first deInonstration of Inonolithically intcgrated LEDs
and power MOS Channel-HEMTs (MOSC-HEMTs) in GaN. High
power GaN-based LEDs used in lighting applications requires
dedicated electronic driver circuits for AC-DC power conversion,
current sourcing, and dimming [1]. Monolithic integration of
GaN-based LEDs and the high perforrnance GaN power switching
transistors, such as MOSFETs, HEMTs, and MOSC-HEMTs can
reduce the cost and the size of solid state lighting systems, improve
system reliability, and serve as a technology platform for the
development of light-emitting power ICs (LEPICs) in smart lighting
applications [2]. The GaN LED and GaN MOSC-HEMT are
monolithically integrated using the selective epi removal (SER)
process approach [3]. The starting HEMT epitaxial material was
obtained from a commercial vendor with customized epi layers on
sapphire substratc, and LED epi was grown in-house on top of thc
HEMT epi using metalorganic vapor phase epitaxy (MOVPE). The
integrated LED and MOSC-HEMT structure was fabricated by first
removing selected regions of the LED structure to expose the GaN
HEMT epi structure using Cl based ICP-RIE. Subsequent fabrication
processes of the LED and MOSC-HEMT were carried out with
multiple shared steps. Finally the interconnecting metal layer
connected the GaN LED cathode to the MOSC-HEMT drain forming
a series configuration. The optical image of our fabricated
monolithically integrated serially connected GaN LED/HEMT pair
has bcen obtained. The output ID-VD charactcristics of the GaN
MOSC-HEMT with channel length of 300 nm and channel width of
800 !-tm shows output current above 100 mA under a gate voltage of
16 V. The I-V and the light output intensity was measured on a single
800 l.tm square GaN LED. Then the monolithically integrated GaN
LED/HEMT pairs in serially-connccted configuration have bcen
tested. GaN LED emits bright blue light, when it is driven directly by
the integrated GaN MOSC-HEMT. The LED current and the light
output intensity was measured as a function of the supply voltage and
the HEMT gate voltage, showing that the LED light output has been
successfully modulated by the gate voltage of the MOSC-HEMT with
good linearity. In summary, we have reported the first demonstration
of monolithically integrated LEDs and power MOS Channel-HEMTs
(MOSC-HEMTs) in GaN, showing a full gate voltage modulation of
the light output power. This deInonstratcs cOInpatibility of group-III
nitride LED and HEMT processes. Acknowledgment: This work was
supported primarily by the Engineering Research Centers Program
(ERC) of the National Science Foundation under NSF Cooperative
Agreement No. EEC-0812056 and in part by New York State under
NYSTAR contract C090145. This work was performed in part at the
Cornell NanoScale Facility which is supported by NSF (Grant
ECS-0335765). References: [1] H. Chiu et aI., IEEE Trans. Ind.
Electron. 57, 735 (2010). [2] R.F. Karlicek, IEEE Photonics Soc.
Summer Topical Meeting Series, Seattle, WA, 2012, p. 147. [3] .1.
Waldron et aI., IWN'12, Sapporo, Japan, 2012.
2:45 PM D3.06
Diamond Raman Micro-Thermometer for Accurate
Time-Resolved Device Surface Temperature Measurement on
AIGaNjGaN HEMTs. Roland 13aranyai, James Pomeroy and
Martin Kuball; University of Bristol, Bristol, United Kingdom.
Accurate channel temperature assessment is critically important for
the evaluation of accelerated device lifetiInc testing of A1GaN/GaN
HEMTs in both DC and pulsed applications. Raman thermography
has previously been developed to enable the measurement of
temperature in semiconductor devices, achieving a high spatial (0.5
!-tm) and temporal (ns) resolution. The peak channel temperature
ncar the gate contact of a HEMT can be extrapolated froIII the
measurement with the aid of calibrated thermal models. However,
some device geometries prevent easy access to the semiconductor in
some areas, e.g. field plates, unless the measurement can be performed
through a transparent substrate, such as SiC, for unpackaged devices.
We report on a novcl Inicro-RaInan thcrrnography bascd approach to
overcome this restriction, by utili7:ing diamond particles as
micro-thermometers for the measurement of surface temperatures, e.g.
the gate contacts of a HEMT. We demonstrate that diamond
Inicroparticles with a diaIneter of 1 Inicron or less can be used to
Inonitor surface tCInperature via diaInond RaInan scattcring. DiaInond
microparticles were dispersed on the AIGaN/GaN HEMT surface. The
temporal evolution of device surface temperatures was measured in
pulsed-operated ungated and gated (field plated) AIGaN/GaN HEMT
dcvices using this technique. Surface teInperaturcs Ineasured on the
ungated device using micro-particles were found to be in good
agreement with conventional Raman temperature measurements of
the underlying GaN - taking the temperature gradient in the GaN
layer into account -, demonstrating the validity of the new thermal
IncasureInent approach. Thc surfacc tCInperature data Ineasured via
the diamond micro-thermometer on gate electrodes - close to the
hottest region of the device - provide valuable additional information
for peak channel temperature evaluation.
3:30 PM D3.07
Flash MOS-HFET Operational Stability for Power Converter
Circuits. Casey Kirkpatrick, Bongmook Lee, Narayanan Ramanan
and Veena Misra; Electrical Engineering, North Carolina State
University, Ralcigh, North Carolina.
The Flash MOS-HFET is a device structure designed to achieved
enhancement mode operation for high threshold voltage (> 2V)
insulated gate GaN MOS-HFET devices. The Flash MOS-HFET gate
stack is designed siInilar to Flash IneInory dcvices with a thin
tunneling dielectric followed by a charge storage layer, and then a
thick control dielectric followed by a metal gate electrode. This
approach has been demonstrated to achieve high VT e-mode
operation for GaN MOS-HFET devices without degradation of device
pcrforrnance (gIn, Inobility, etc. ) 1-3.While this approach is proInising
for e-mode GaN devices, there is a key challenge with this device
design. Due to threshold shift from stored charge, if significant charge
is lost from the charge storage layer, the threshold voltage will shift in
the negative direction. If too much charge is lost over time, the device
will bc rendcred depletion Inode requiring another gate pulse to
recharge the charge storage layer. This loss of charge over time has
been reported under static conditions (VG=O, VD=O, VS=O) 1-3 and
is accelerated at increased operation temperature. Previous Flash
MOS-HFET reports provide paths to iInproveInent to rcducc or
eliIninate charge loss over tiInc including increasing the thickness of
the gate stack or optimization of dielectric materials and annealing
temperature. While these methods can lead to improvement, it is
important to consider the application of this novel device when
considering threshold voltage stability. Flash MOS-HFET devices will
be employed in power electronic circuits with a gate driver
continuously applying pulses to control current flow. This gate driver
pulse has potential to contribute small portions of charge to the
charge storage layer during device operation. This work will
characterize the thrcshold voltagc stability under several gate driver
conditions and threshold voltage stability during operation in a boost
converter circuit at temperatures up to 125C. Zero charge loss is
observed for the GaN Flash MOS-HFET device extrapolated for the
lifetime of the device at temperatures up to 125 0 C during power
converter operation. This is the first dCInonstration of zero charge loss
over time in the GaN Flash MOS-HFET device structure at high
temperatures, overcoming a key challenge. The GaN Flash
MOS-HFET is thus demonstrated for high performance, high
threshold voltage, low leakage enhancement mode operation without
any Inodifications requircd to typical power convcrter circuit dcsign.
References 1. B. Lee, C. Kirkpatrick, Y. Choi, X. Yang, A. Q. Huang
and V. Misra, physica status solidi (c) (2012). 2. B. Lee, C.
Kirkpatrick, X. Yang, S. Jayanti, R. Suri, .1. Roberts and V. Misra,
20.6. 1 (2010). 3. C. Kirkpatrick, 13. Lee, Y. H. Choi, A. Huang and
V. Misra, physica status solidi (c) (2011).
3:45 PM D3.08
Evaluation of Low-Carrier Thick n-GaN Schottky Diodes on
GaN Free-Standing Substrates. Kenji ShiojiIna
1
, Yuhei Kihara
1
,
Toshichika Aoki
1
, Naoki Kaneda
2
,1 and TOInoyoshi MishiIna
2
;
1 Graduate School of Electrical and Electronics Engineering,
University of Fukui, Fukui, Fukui, Japan; 2 Corporate Advanced
Technology Group, Hitachi Cable Ltd., Tsuchiura, Ibaraki, Japan.
1. Introduction: The recent progrcss of free-standing GaN substrates
[1], points to the development of vertical p-n junction [2] and
Schottky diodes for power device applications [3]. A Schottky diode
255
has an advantage of lower turn-on voltage, however, it requires
high-quality thick n-GaN layers with low carrier density. In the GaN
crystal growth using rnetalorganic chernical vapor deposition
(MOCVD), when the Si doping concentration is as low as around
lxl016 cm-3, because of carrier compensation with unintentionally
incorporated C atoms, the electron concentration is lower than the
expected value from the Si doping level. Since C-incorporation is not
avoidable in MOCYD growth, for better low-carrier layers,
establishment of growth conditions taking account of the
compensation is important. In addition, C atoms can form deep-level
defects, which may induce the effect in device operation. In this
paper, we fabricated and evaluated low-Si-doped thick GaN Schottky
diodes on GaN substrates with varied C-doping concentrations. 2.
Sample preparation: Two-I-'m-thick Si-doped (2x1018 cm-3) n-GaN
films and 12 I-'m-thick 10w-Si-doped-GaN films were grown on
GaN-bulk substrates using MOCVD. Si and C concentrations were
varied in the range of 1.2-3.Sx1016 crn-3. TilAl ohrnic electrodes were
formed on the rear surface, and Ni/Au Schottky contacts were formed
on the front surface. 3. Electrical characteristics: In the I-V
characteristics, the samples with Si "" C showed good linearity in the
forward current, and Schottky barrier height and n-value were
obtained to be 1.04-1.10 eV, and 1.01-1.03, respectively. The reverse
currents were as low as 100 pA at -200 V. From the C-V carrier
profiles, the net carrier concentration were controlled in the range
between 0.72 and 1.9x1016 cm-3. It was confirmed that the Schottky
characteristics were secured from the amount of Si and C doping
levels in this experirnental condition. For the sarnples with Si < C, as
expected, a large compensation resulted in a large series resistance in
the I-V characteristics. 4. Defect characterization: Deep-level transient
spectroscopy (DLTS) measurements were conducted for the samples
with Si "" C. Three peaks (E1, E3, E4 Ec-0.25, 0.60, 0.70 eV) were
detected in the spectra. The trap concentrations are as srnall as below
2x1013 cm-3 for E1 and E4, 1.2x1014 cm-3 for E3. Larger peak
intensities in E3 and E4 were obtained from Si-, and C-rich samples,
respectively. 5. Conelusion: Low-Si-doped thick GaN Schottky diodes
on GaN substrates were evaluated. Good Schottky characteristics were
obtained at a net carrier concentration around 1x1016 crn-3, even
though the amount of Si and C doping levels were different. DLTS
measurements revealed three defect levels, but the concentrations
were as small as below 1.2x1014 cm-3. References [1] T. Yoshida et ai,
J. Cryst. Growth, 310, p. 5 (2008) [2] K. Nomoto et ai, p.s.s. (a), 208,
p. 1535 (2011) [3] Y. Saitoh et ai, APEX, 3, 1'.081001 (2010)
4:00 PM D3.09
Interface State Characterization of AI 20
3
/AIGaN/GaN
Structure with Inductively Coupled Plasllla Etched AIGaN
Surfaces. Zenji Yatabe
1
, Yujin Hori 1 and Tamotsu Hashi7.:ume
1
,2;
I Research Center for Integrated Quantum Electronics, Hokkaido
University, Sapporo, Hokkaido, Japan; 2JST-CREST, Chiyoda-ku,
Tokyo, Japan.
AIGaN/GaN-based HEMTs are promising for high-power switching
devices. In order to reali7.:e a normally-off operation from the fail-safe
viewpoint, a combination of recessed and insulated gates is often used
in AIGaN/GaN HEMTs. It is known that plasma-assisted etching
degrades the electrical properties of AIGaN surface. However, no work
has been reported regarding the characterization of the
insulator/AIGaN/GaN structures with an ICP etched AIGaN surface.
In this study, we thus report the effects of the Cl2 -based ICP etched
AIGaN surface on the interface properties of the Al,03/AIGaN/GaN
structures. In particular, we focus on the interface state density
distribution evaluated by a combination of rigorous
C- V characteristics calculation and a photoassisted C- V technique.
An undoped Alo.2Gao.8N/undoped GaN heterostructure with an
AIGaN layer thickness of 34 nm was used in this work. The AIGaN
surface was etched at RT by the ICP etching process using a
CI
2
/BCI
3
gas mixture (25/5 seem). The ICP and bias powers were
300 and 5 W, respectively. The etching depth was 7 nm at an etching
rate of 10 nm/min. An Al 2 0 3 film with nominal thickness of 20 nm
was deposited on the AIGaN surface at 350C using ALD system.
Water vapor and TMA were used as a and Al sources, respectively.
The calculation of C- V curve was carried out using a numerical
solver of the Poisson equation based on the one-dimensional Gummel
algorithm, taking into account the fixed charge at the AIGaN/GaN
interface originating from spontaneous and piehoelectric polarihation
as well as the charge in the electronic states at the Al,03/ AIGaN
interface. For the calculation, a discrete and a U-shaped continuous
interface state density distributions Dit(E) at the AI2 0 3/AIGaN
interface were assumed. The experimental C- V curves showed two
steps, peculiar to the MaS HEMT sarnple fabricated on the
heterostructure with a 2DEG. The ICP-etched sarnple showed a
gradual slope of the C- V curve, a high on-set voltage and an
inflection point appearing in the forward bias range. These indicate
the higher state densities at the Al,03/ICP-etched AIGaN interface.
To fit the experirnental C- V curves with the calculated ones, a
continuous and discrete interface state densities within the energy
range Eo - 0.8 eV were assumed at the AI
2
0
3
/AIGaN interface.
Assuming that the discrete level is at Eo - 0.1 eV and that the
continuous interface states have densities ranging from 1 X 10
12
to 4
X 10
13
crn-
2
ey-
1
, we obtained good agreernent between the
experimental and calculated C- V data. To evaluate the interface
states near-midgap, we then applied the photoassisted C- V technique
using a photon energy less than the bandgap of AIGaN. It was found
that the near-midgap interface state density ranges from 3 to 8 X
10
12
crn-
2
ey-
1
. FrOIll the cornbination of rigorous calculation of
C- V characteristics and the photoassisted C- V technique, for the
first time, we have evaluated Di,(E) at the Al,03/ICP-etched AIGaN
interface.
SESSION DP2: Poster Session: Electrical Devices
Tuesday Evening, August 27, 2013
6:00 PM
Potomac C/D & 1-6
DP2.01
AIGaN/GaN Reverse Conducting HFET for Power
Conversion. Jin Wei
1
,2, Yao Yao
1
, Wei Zhang
1
, Meng Zhang
2
,
Zhiyuan He
'
, Bo Zhang
2
, Baijun Zhang
'
and Yang Liu'; I Sun
Vat-sen University, Guangzhou, China; 2University of Electronic
Science and Technology of China, Chengdu, China.
An AIGaN/GaN reverse conducting HFET is proposed and verified
for the first time, in which a Schottky diode is imbedded. Although
silicon power MOSFET and RC-IGBT exploit their body diodes as a
reverse conducting path [1, 2], so far, there have been no reports on
GaN HFET with an inner diode. EPC Corporation suggests directly
using the HFET itself as a "body diode" by driving VGD higher than
threshold voltage [3]. This, however, results in a large turn-on voltage
for the "body diode". In the proposed AIGaN/GaN RC-HFET, a
Schottky contact (named S2 here) is placed between the gate and the
drain, and electrically connected to the source. The heterostructure is
grown on silicon substrate by MOCVD. The processing of RC-HFET
is compatible with conventional HFET, with no extra mask required.
The measurement shows that the inner Schottky diode of the
AIGaN/GaN RC-HFET turns on at around 1.0 V while the "body
diode" in the conventional HFET (of the same dimensions) at over 3.0
V. In the forward working conditions, the RC-HFET is working as a
switch while the inner Schottky diode is reversely biased. Our
experiment shows that the on-resistance of the AIGaN/GaN
RC-HFET is barely changed cornpared to that of the conventional
HFET. On the other hand, RC-HFET effectively reduces the
saturation drain current by 46%, because the pinch off occurs at the
edge of S2. This is beneficial for power conversion, since a lower
saturation current increases the short circuit safety [1,4]. In
conelusion, the proposed AIGaN/GaN RC-HFET provides a cost
effective solution for power conversion. An efficient conducting path
inside the device is achieved for the inductive load, thus avoiding the
need to anti-parallel an external diode. References: [1] S. Linder,
Power Semiconductors. Lausanne: EPFL Press, 2006. [2] H. Jiang, J.
Wei, et aI., IEEE Electron Device Lett., vol. 33, no. 12, Pl'. 1684-1686,
2012. [3] A. Lidow, et aI., GaN Transistors for Efficient Power
Conversion. El Segundo: Power Conversion Publications, 2012. [4] M.
Mori, Y. Dchino, et al., IEEE Trans. Electron Devices, vol. 54, no. 8,
Pl'. 2011-2016, 2007.
DP2.02
Effect of Telllperature on Gate Leakage Current in
AIGaN/GaN High Electron Mobility Transistors.
Weiwei Chen
1
,2, Ping Ma
1
,2, I3in Hou
1
,2, Jincheng Zhang
2
, Xiaohua
Ma
,
,2 and Yue Ha0
2
. 'School of Technical Physics Xidian University
Xi'an, ShanXi, h i n ~ 2Key Lab of Wide Bandgap'Semiconductor .,
Materials and Devices, Xi'an, ShanXi, China.
Many authors have observed the increase of gate leakage current with
temperature in the AIGaN/GaN high electron mobility transistors
(HEMTs) over a wide temperature range (from 110 K to 400 K). The
increase of gate leakage current with the temperature is a clear
disadvantage of devices operating at elevated ternperatures. S.
Arulkumaran et al. [1] found that the temperature dependence of gate
leakage current for AIGaN/GaN HEMTs have both negative and
positive trends for temperature range 20-400 degree celsius, but the
dependence of gate leakage current on temperature below 20 degree
celsius was not investigated in this paper. In this letter, we report the
effect of temperature on gate leakage current of AIGaN/GaN HEMT
on sapphire measured for the temperature range of 85 K to 300 K. We
found that gate leakage current decrease with temperature almost
linearly from 85 K to 150 K, then decrease suddenly from 150 K to
200 K. Above 200 K, gate leakage current increase with ternperature
almost linearly. This phenomenon was observed over a wide range of
gate voltage (from -5 V to -20 V). It's assumed that deep acceptor
initiated impact ionihation in the channel, rather than gate tunneling,
is the dorninant leakage rnechanisrn at very low ternperature. This
explains the decrease of gate current with the increase of ternperature
256
from 85 K to 200 K. The sudden decrease of leakage current from 150
K to 200 K suggests the disappearance of impact ionization
phcnolncnon. Above 200 K, the direct tUIlIleling and trap assisted
tunneling changes to the dominant leakage mechanism. Since direct
tunneling current and trap assisted tunneling current both have a
positive dependence on temperature, the increase of gate leakage
current with temperature from 200 K to 300 K can be easily
understood. [1J Appl. Phys. Lett. 82, 3110, 2003
DP2.03
High Linearity AlGaN/GaN Graded Heterojunction Filed
Effect Transistor. Fcng Zhihong, Fang YuLong, Yin Jiayun, Gu
Guodong, Lv Yuanjie, Song Xubo, Han Tingting, Dun Shaobo and
Cai Shujun; Science and Technology on ASIC Laboratory, Hebei
Semiconductor Research Institute, Shijiazhuang, China.
The large dynarnic range in the variable envelop of the rnodulation
signals in the next generation wireless communication systems has put
forward stricter requirements for the linearity of the GaN based
devices. However, the narrow available transconductance range in the
traditional GaN HFETs is the main obstacle for high linearity
applications. To extend the available transconductance range, the
research groups around the world have developed various methods,
including the introduction of the field-plate, the modification of the
source access resistance, and the introduction of double channel or the
cornposite channel. Recently a new type GaN based HFETs, narned as
polarization doping FETs (PolFETs), have attracted a lot of
attention. The basic structures of PolFETs are the graded Al mole
fraction AIGaN layers, the well-known two dimensional electron gas
formed at the AIGaN/GaN interface in traditional HFETs would
extend to a quasi-three-dirnensional electron slab across the graded
AIGaN/GaN region in PoIFETs. The geometry extension of the
carriers profiles provides the basis of wider and flat transconductance.
The PolFET sample employed in this work was epitaxially grown by
MOCVD on a 2 inch sapphire substrate. The material structure
consists of a 2JLIn unintentionally doped (UID) GaN, a 60 rnn channel
from GaN graded to AIO.35GaO.65N, approximately. The bulk
three-dimensional dopants profile in PolFET was verified by the
capacitance voltage measurements, as shown in figure 1 (b). There was
an average charge of 1.2E+18 cm-3 calculated over about 60nm. The
DC I-V characteristics of PolFET are plotted in Fig. 2. A peak
transconductance about 92mS/mm was obtained and remained
roughly flat. The notable flat and wide transconductance indicates the
potential for high linearity devices. The on wafer small-signal
S-parameters characterization were conducted on a the 1 X 40 J-Lm
PolFETs at various DC bias points, i.e. VGS and VDS, and the
frequencies mapping at different biases were graphed. Similar to what
observed in DC transfer characteristics, it appears a flat frequency
across large VGS and VDS ranges. The bias insensitive frequency
characteristics spell the tolerance of undesirable input signal distortion
in PoIFETs. At the optirnurn bias point, the cutoff frequency of 15.6
GH7, and maximum oscillation frequency of 43.6 GH7, were obtained.
DP2.04
Trap Assisted Tunneling as Reverse Bias Conduction
MechanisITl in Ni/InAlN/GaN Schottky Contacts.
Loren7,o Lugani, Marcel A. Py, Jean-Francois Carlin and Grandjean
Nicolas; Institute of Condensed Matter Physics, Ecole Polytechnique
Federale de Lausanne, Lausanne, Switzerland.
InAIN/GaN high electron mobility transistors, despite having reached
extremely high cutoff frequencies in excess of 300 GHz," are still
seriously affected by strong parasitic gate leakage currents which limit
their breakdown voltage and power output. Here, we propose
tunneling assisted by a deep trap2 as the conduction rnechanisrn
responsible for reverse bias current in Ni/InAlN/GaN Schottky
contacts. The heterostructures investigated here were grown by
metal-organic vapor phase epitaxy on sapphire and are composed of a
2 J1.HI GaN buffer, a 1 rnn AIN spacer and an InAIN barrier of variable
thickness. The InAIN barrier thickness has been precisely determined
by X-ray reflectivity measurements. Schottky diodes fabrication
started with the deposition and annealing of the Ti/AI/Ni/ Au Ohmic
metal stack and was completed by the deposition of the Ni/ Au
Schottky contact. The relevant InAIN rnaterial pararneters, narnely
the static dielectric constant ElnAlN and the polari7,ation charges
O"InAlNjGaN, have been firstly determined from the dependence,
respectively, of the heterostructure capacitance and pinch-off voltage
on the InAlN barrier thickness. Values of 10.1 and 3.07x 10"
3
cm-
2
where obtained, respectively, for ElnAlN and O"InAlNjGaN' With
these parameters, the capacitance-voltage curves of a set of
InAIN/ GaN heterostructures could be modeled in order to extract the
Schottky barrier <P B, which turned out to be 2.8 eV. Thanks to this
set of parameters, the voltage-dependent electric field in the InAlN
barrier could be calculated using a Schrodinger-Poisson solver
3
and
used for current modeling. We simulated the reverse bias
current-voltage characteristic of three heterostructures having a total
(AIN + InAlN) barrier thicknesses of 3.3, 4.8 and 8.1 nm. Excellent
agreement with the experimental results has been obtained with a
trap assisted tunneling using a trap level located 1. 7 eV below the
InAIN conduction band edge. More details concerning the current
temperature dependence and other possible current paths will be
provided during the conference. [IJ Y. Yue et a!.,
IEEEElectronDeviceLett. 33 988 (2012) [2J D. M. Sathaiya and S.
Karmalkar, J.AppI.Phys. 99 093701 (2006) [3J nextnano
3
software,
www.nextnano.de
DP2.05
On the Bulk and Interface States Trapping PhenoITlena in the
GaN-Based MaS Heterostructure Gate Dielectric.
Milan Tapajna
1
, Michal Jurkovic
1
, Lukas Valik
1
, Stefan Hascik
1
,
Dagrnar Gregusova
1
, Frank Brunner
2
, Enjung-Melanie Cho
2
, Oliver
Hilt
2
, Eldad Bahat-TriedeI
2
, Joachim Wuerfl
2
and Jan Kuzmik
2
;
1 Institute of Electrical Engineering, Slovak Academy of Sciences,
Bratislava, Slovakia; 2Ferdinand-Braun-Institut, Leibniz Institut fur
Hochstfrequenztechnik, Berlin, Gerrnany.
The performance of GaN MOS-HFETs is still limited by the presence
of traps related to the gate oxide, partly also due to lack of the
effective characterization techniques. In particular, adoption of the
conventional techniques for interface trap density (Dit) deterrnination
usually neglects other parasitic effects that may effectively hamper
the correct analysis, leading to e.g. unexpected oxide thickness
dependent Dit distribution. Here, the trapping phenomena in GaN
MOS-HFET structures with AI203 dielectric were deeply investigated
using cornprehensive capacitance rneasurernents. The MOS-HFET
structures with 10 and 20-nm-thick AI203 gate dielectrics were
deposited by MOCVD at 600C on GaN cap/AIO.24GaO.76N/GaN
heterostructures. In contrast to Schottky barrier HFET structures,
capacitance-voltage (C-V) measurements of MOS-HFET structures
showed positive Vth shift with increased base plate ternperature (Tb),
accompanied with change of the C-V hysteresis from positive to
negative. This suggests coexistence of two competitive
trapping/detrapping processes related to the gate dielectric. To
analyze this in rnore detail, we deterrnine Vth transients by rneasuring
capacitance transients at the onset of the depletion after stepping the
gate voltage (Vg) from 0 - 8 V (filling pulse, Vg,F) to
While Vth increased with time for Vg,F=O V, indicating dominant
electron trapping in the dielectric bulk, it decreased for Vg,F=2-8 V,
consistent with dorninant electron ernission froHI interface traps. To
determine Dit distribution, Vth transients for Vg,F=O V were
subtracted from those for positive Vg,F, and analyzed using
isothermal DLTS concept. The trapping process in the dielectric was
similar for 10 and 20-nm-thick Al203 indicating oxide traps to be
located just a few nrn under the gate. The ternperature dependence of
the trapping process was found to be consistent with thermionic field
emission showing trap level located eV above the metal Fermi
level, corresponding to eV in the oxide. The sheet density
of the oxide traps (NT) was estimated to be in the range of
crn-2. Additionally, to characterize interface traps with deeper
activation energy, Vth transients were measured also upon the
monochromatic light pulse exposure. Dit was then calculated from the
difference between two adjacent Vth shifts. Typical U-shape Dit
distributions ranging froHI 1013 - 1011 eV-1crn-2 was deterrnined,
sirnilar for sarnples with both Al203 thicknesses. In surnrnary, a
careful separation between the trapping process in the oxide bulk and
the oxide/semiconductor interface traps emission allowed us to
determine Dit distributions and quantify traps in the oxide. The
trapping process in the oxide was found to be consistent with the
thermionic field emission of electrons from the gate into traps located
a few nm below the gate. Funding from EU FP7 project HipoSwitch
(grant no. 287602) and Slovak projects APVV-0367-11 and
APVV-104-10 is gratefully acknowledged.
DP2.06
Surface TreatITlent Effects on Surface States of AlGaN and
Interface States of AI203/AlGaN. Brianna S. Eller, Jialing Yang
and Robert .T. Nemanich; Department of Physics, Arizona State
University, Ternpe, Arizona.
The disparate polarization at AlGaN/GaN heterostructures engenders
a 2D electron gas (2DEG) that effectively reduces on-resistance and
power loss, resulting in a high electron mobility ideal for
high-frequency, high-ternperature, and high-voltage requirernents
associated with HFETs and HEMTs. However, the concentration of
the 2DEG is related to interface and surface states. Since GaN and
AIGaN are characterized by a large spontaneous polarization, there is
a large polarization bound surface charge (2.2x1013 and 3.2x1013
charges/crn2) that rnust be cornpensated. Cornpensation charge gives
rise to a large concentration of surface states. Charge neutrality
suggests a higher concentration of surface states may increase the
2DEG concentration and reduce the potential drop across the AlGaN
layer. This ultirnately affects device reliability, increasing gate leakage
current and current collapse. Understanding the states may thus prove
crucial to reliable device performance. In this work, AIGaN samples
257
were cleaned with several wet chemicals that have been shown
effective on GaN. The AIGaN samples were AIGaN/AIN/Si with 25%
AI. Lincar intcrpolation gavc a band gap of 4.1 cV and thc doping
density (1017 cm-3) determined the Fermi level ~ 0 1 eV below the
conduction band minimum. The various surface treatments included
sonication in acetone and methanol followed by DI water, HF, HCI,
H202, NH40H, or (NH4)2S, and a final DI rinse. X-ray and
ultraviolet photospectroscopy (XPS and UPS) were used to
characterize the constituents and surface band bending. Results
suggest that none of the wet chemicals were effective at removing
carbon contamination, and only HF and HCI made significant reduced
the oxygen covcrage. Thc band bending of AIGaN rernains stable after
the various treatrncnts, giving ",0.3 eV upwards or rv3.1 x1013 nct
positive surface charge/ cm2. After cleaning, remote plasma-enhanced
atomic layer deposition was used to deposit rv2 nm of amorphous
A1203. XPS and UPS determined the valence band offset (VBO),
giving 1.1-1.3 eV. This corresponds to a conduction band offset
(CBO) of 1.3-1.1 eV. Similar studies were also conducted on
GaN/AIN/AI203. On GaN, the surface treatments did impact
oxygen-related states, though they were unable to reduce carbon
contamination. The band bending was then determined to be ~ 0 2 eV
upwards, which corresponds to '"'-'2.0x1013 net positive charge/crn2.
Similar determination of the VBO and CBO gave of A1203/GaN 1.8
and 1.3 eV, respectively. In summary, wet chemical treatments did not
typically affect the surface states and interface bonding at
A1203/ AIGaN interfaces. Similar band bending on GaN and AIGaN
suggcst the surface states increasc with the polarization charge and
thus AI-content. Future work will continue to study the relationship
between the AI-content and band bending. Furthermore, the similar
CBO of A1203/GaN and AIGaN suggests the difference in band gap
manifests at the VBO. Research is supported by ONR through
DEFINE MURI.
DP2.07
Comparison of AIGaN/GaN MISHEMT Powerbar Designs.
Stevc Stoffels, Nicolo Ronchi, Rafael Venegas, Brice De Jacger, Denis
Marcon and Stefaan Dccouterc; irncc, Leuven, Belgiurn.
Conventional AIGaN/GaN powerbar designs, presented in literature,
typically use a long gate finger layout. However, such long finger
configurations can lcad to scveral issucs whcn uscd in rcal
applications. First of all, the long gate fingers lead to an excessive
gate resistance and limit the choice of metal stack which can be used
as gate metallization, i.e. metals with a high sheet resistance would
lead to very high values of the gate resistance. A second issue is the
switching delay differencc between the beginning and thc cnd of these
gate fingers. Due to the propagation delay of the electric signal, the
active region at the end of such a finger will switch off at later time
than the beginning, causing it to draw a large amount of current
during switching and potentially leading to reliability issues. For this
work we have dcsigncd, fabricated and evaluated thrce diffcrent
AIGaN/GaN powerbar architectures. During the design phase we have
developed analytical models to calculate the interconnect parameters
such as gate resistance, access resistance and parasitic capacitances.
The intcrconnects were rnodeled as a distributcd network of lurnped
cornponcnts, which were subsequcntly sirnplified to get the
interconnect parasitics between each of the terminals. The models
were then applied to three different designs, with very different gate
and interconnect topologies. The first design was the more
conventional, long gate finger (LGF) design with a single activc island
and long interdigitated fingers. To improve on the high gate
resistance, we have investigated a second design with several active
islands with shorter gate finger (SGF) and interconnects running in
between the active islands. The final design has 3D interconnects
(3DI) running in a stacked crossbar configuration on top of thc activc
islands. The designs were fabricated in an 8 inch GaN-On-Si
MISHEMT technology, with a barrier recess at the gate level to shift
Vt towards more positive values. Wafers with and without gate recess
were compared to evaluate the impact of the gate recess on the
powcrbar characteristics. On cach wafer wc have perforrned a
parametric analysis of 13 powerbars for each design. Powerbars with a
total gate width of 18mm and 36mm were analyzed. Capacitance and
impedance measurements were performed to evaluate the gate
resistance and on-state capacitance. We found that the analytical
rnodels gave for rnost dcsigns a good agreernent (error<15%) with thc
measured values and could be used to identify contact resistance
problems in the gate bus. Moreover, measurements showed that the
SGF and 3DI designs exhibited gate resistances which were a factor 4
to 8 srnaller than the LGF design. The irnpact on thc on-state
capacitance was rninirnal for the SGF dcsign and lirnitcd to a 15%
increase for the 3DI design. The capacitance model gave an agreement
of 10% with the measured capacitance values. Static parameters were
also measured and the on-resistance, breakdown and threshold voltage
werc cxtracted frorn these rneasurcrncnts. Thc SGF/3DI powerbar
designs reached the design goal of reducing the gate resistance with a
factor of 4 to 8 with respect to the long gate finger designs. The SGF
design had no negative impact on the powerbar operation and
exhibited figures of merit (FOM) for Ron/Cgs,on and VBD2/Ron,sp
comparable to the LGF design. The 3DI design on the other hand
only showed a slight irnpact on Ron/Cgs,on, but exhibitcd a reduced
value for the FOM VBD2/Ron,sp due to vertical breakdown at the
interconncct crossings. However, this was expected as no optirnization
was performed on the inter-metal dielectrics (IMD) and will be
addressed in future process iterations by a tailored process integration
scheme with thicker IMD's.
DP2.08
HVPE GaN Schottky Diodes. Randy P. Tompkins", Joshua R.
Smith", Kevin W. Kirchner", Kenneth A. Jones", Jacob H. Leach
2
,
Kevin Udwary2, Edward Preble
2
, Jeffrey Leathersich
3
, Puneet
Suvarna
3
and Fatemeh (Shadi) Shahedipour-Sandvik
3
; "US Army
Research Laboratory, Adelphi, Maryland; 2Kyrna Technologies,
Raleigh, North Carolina; 3College of Nanoscale Science and
Engineering, University at Albany - State University of New York,
Albany, New York.
Properties of galliurn nitride (GaN) such as a high critical field rnake
it a promising material for high power electronics. We have identified
carbon in GaN as an impurity that increases the specific
on-resistance, increases the turn-on voltage, and leads to premature
breakdown of GaN power Schottky diodes [1]' where presumably C
sitting on the N site acts as a deep level acceptor. To date, most
device layers are grown by MOCVD where a direct source of C exists
from the trimethlygallium source. An alternative to MOCVD growth
of device layers is hydride vapor phase epitaxy (HVPE) where the Ga
source is HCl reacting with liquid galliurn and thcre are no dircct
sources of C. We have shown that diodes fabricated directly on
freestanding HVPE substrates show breakdown voltages in excess of
900 V, but the high breakdown is at the cost of a large specific
on-resistance stemming from the thick low-doped substrate. However,
after subtracting thc contribution of the low-doped substrate to the
series resistance, a figure of merit of ~ 250 MW/cm
2
was extracted
[2]. The focus of this work is the growth of low-doped HVPE GaN
films on doped freestanding HVPE substrates. In these devices the
majority of the series resistance is across the film and not the
substrate. The biggcst issue with growing epitaxial layers by HVPE is
lowering the net carrier concentration of the film or drift layer.
Carrier concentrations generally range 5 x 10
16
cm-
3
- 1 x 10
17
cm-
3
where the likely source of background doping in the drift layer is Si
and a froHI HCl reacting with the quartz reactor. If onc can lower the
unintcntional doping in the drift laycr to ::::::::: 10
16
crn-3 a theoretical
breakdown voltage of 3000 V can be achieved. GaN power Schottky
diodes generally fall well short of their theoretical maximum .
breakdown voltage due to a large number of defects such as threading
dislocations and point defects. This talk will focus on thc cffects of
point defects and crystalline defects on the performance of GaN power
Schottky diodes. Device results will be presented for vertical Schottky
diodes fabricated on HVPE GaN films grown on HVPE GaN bulk
substrates. If time permits, comparisons will be made to results of
Schottky diodes fabricated on MOCVD GaN films grown on
conductive HVPE GaN bulk substrates. [1] R.P. Tompkins et ai, J.
Mater. Res., Vol. 26, No 23, p. 2895 - 2900 (2011). [2] R.P. Tompkins
et ai, Solid State Electron., 79 p. 238-243 (2013).
DP2.09
An Etch-Stop Barrier Structure for GaN Normally-Off High
Electron Mobility Transistors. Min Sun",2, Bin Lu",2 and Tomas
Palacios1,2; 1 Department of Electrical Engineering and Computer
Scicnce, Massachusetts Institute of Technology, Carnbridge,
Massachusetts; 2Microsystems Technology Laboratories,
Massachusetts Institute of Technology, Cambirdge, Massachusetts.
Gate recess by plasma etching is an important process technology for
rnaking GaN norrnally-off transistors. There are two rnajor drawbacks
in dry plasma etching: one is the plasma damage and the other is the
device uniformity across the wafer [1]. In this work we report a new
transistor barrier structure to address these problems. This structure
consists of a 22 nrn GaN:Si cap layer with 6x 10
18
crn-
3
Si doping /
1.5 mn AlN / 3 mn Alo.15GaO.85N / 1.2 ,un i-GaN / 2.8 lun buffer /
p-Si substrate. The 2DEG in this structure can be fully depleted by
removing the n-doped GaN cap layer. High selectivity etch of GaN
over AIN is achieved by using Fluorine based plasma due to the
non-volatility of AIF
3
. To ensure uniforrnity, a 70-second-over-etch
was used. A 10 nm Al
2
0
3
gate dielectric was deposited after UV
m7,one and HCI cleaning. The sample was annealed in forming gas
after the gate metallization. Averaging over 13 devices, the E-mode
devices have a threshold voltage of 0.300.04 V in linear scale and a
subthreshold slope of 621 mV/decade. The CV characteristics have
low frequency dispersion between 1 kHz and 1 MHz and very small
hysteresis ~ 10 mV) under bi-directional CV sweeps, which indicates
very low interface trap density in the recessed gate region. The
maximum effective electron mobility in the channel is 1131
crn
2
V-
1
s-
1
, as extracted froHI the IV and CV characteristics. This
value is largely improved compared to other reported results on
258
normally-off GaN MISFETs. An additional advantage of the proposed
structure is its compatibility with Au-free ohmic metallization. After
rcrIloving the n-CaN cap layer in the drain and source region, a low
R
c
value of 0.6 !lmm was obtained by annealing Ti/Al (20/100 nm)
metal stacks at 560 0 C in N2. Smoother annealed metal surface and
edge were observed on Au-free ohmic contacts. The above results
show the great potential for this structure in mass production of high
pcrforrnancc nonnally-off RF and power GaN transistors.
Acknowledgements - This work was supported in part by the
Advanced Research Projects Agency - Energy ADEPT project and
by GIGA project of the U.S. Department of Energy. References: [1] B.
Lu, et aI, IEEE Electron Device Lett., 9 (2010) 900.
DP2.10
Performance Improvement of NpN-GaN/InGaN/GaN
Heterojunction Bipolar Transistors on Sapphire Substrates
by Modified Doping Profile. Jeomoh Kim", TSllng-Ting Kao",
Jae-Hyun Ryou",2, Theeradetch Detchprohm", Shyh-Chiang Shen"
and Russell D. Dupuis"; "ECE, Georgia Institute and Technology,
Atlanta, Georgia; 2Department of Mechanical Engineering, University
of HOllston, HOllston, Texas.
III-nitride power electronics offer IIl3UY advantages for operation
under harsh environment such as high voltage, current density, and
temperature. They also offer the potential for high frequency
switching operations. In this study, we demonstrate improved device
performance of NpN-GaN/InGaN/GaN heterojunction bipolar
transistors (HBTs) grown OIl sapphire substrates by In3niplllating
doping profile in the Base-Emitter (B-E) junction. The device
structures were grown in a Thomas Swan 6 X 2" metalorganic chemical
vapor deposition reactor. The layer structure consists of a GaN:Si+
subcollector (0.85 pm, n=6x1018 cm-3), a GaN:Si collector (0.3 pm,
n=l X 1017 cm-3), an InxGa1-xN:Si graded collector (x=0-+0.03, 30
nm, n=l X 1018 cm-3), an InO.03GaO.97N:Mg base (100 nm,
p=l X 1018 cm-3), an InxGa1-xN:Si+ graded emitter (x=0.03-+0, 30
nm, n=l X 1018 cm-3), a GaN:Si++ emitter (100 nm, n=l X 1019
cm-3), and a GaN:Si++ contact layer (20 mn, n>2x1019 cm-3). The
graded layers serve to reduce strain between the interfaces, rnitigatc
V-defect formation, and to eliminate conduction band discontinuities,
particularly at the base-emitter junction. The epitaxial structures on
sapphire substrates were grown on a GaN buffer layer including a 20
llIll low tcrnpcraturc buffer layer for strained hctcrocpitaxy. For the
sample A, doping profile was modified by controlling the molar flow
rate of Cp2Mg which is the precursor of Mg dopant atoms. Sample B,
which is typical NpN-GaN/InGaN/GaN HBT without doping profile
manipulation, was also grown on sapphire substrate for a comparative
study. After growth and rnatcrial characterization, the layers were
fabricated into devices with emitter si'es of 20 X 20 pm2. The 20 X 20
pm2 device shows d.c. gain ((3) of 25 and 20 for Sample A and Sample
B, respectively, at VBE = 10 V. The common-emitter I-V family
curves of these devices demonstrate a collector current density (Jc)
greater than 3 kA/cln2 for the sarnplc A. A significantly irnprovcd
"knee voltage" by 2.0 V at Jc > 3 kA/cm2 was observed. The detailed
experimental method and following enhanced device performance will
be further discussed.
DP2.11
Normally-Off InAlN/GaN MIS-HEMT Using Fluoride-Based
Plasma Treatment. Shenglei Zhao, Peng Zhang, Junshuai Xue, Yi
Wang, Jincheng Zhang, Xiaohua Ma and Yue Hao; Key Laboratory
for Wide Band-Gap Scrniconductor Materials and Devices, Xidian
University, Xi'an, China.
Owing to the high 2DEG density induced by the uniquely strong
spontaneous polarizmtion, the specific ON-resistance of the
InAIN/GaN HEMTs is very low, indicating that the InAlN/GaN
HEMTs are promising power electronic devices. However, the
breakdown voltage in the InAIN/GaN HEMTs is limited due to the
relatively large gate-leakage current as a result of the high dislocation
density in the InAlN barrier layer. To reduce the gate leakage in
HEMTs, the gate insulator layer was used, resulting in MIS-HEMT
structures. Besides, normally-off devices are necessary because they
can not only help simplify the complexity of the circuit but also reduce
power consumption. Fluorine treatment technique was employed to
the InAlN/GaN HEMTs to shift the threshold from negative to
positive. In this work, we present normally-off AI203/InAlN/GaN
MIS-HEMTs using fluoride-based plasma treatment. Using this
method, the threshold voltage of AI203/InAlN/GaN MIS-HEMT can
be shifted from -7.7 V to 1.2 V. For the MIS-HEMT treated with
fluorine plasIna at 150 W for 150 s, the peak transconductance has
only decreased from 175 mS/mm to 151 mS/mm. Compared with the
conventional MIS-HEMTs, the gate-leakage current of the
MIS-HEMTs treated with fluorine plasma was reduced by one order of
magnitude. Therefore, the combination of gate dielectric and the
fluorine treatInent technique can not only reduce the gate-leakage
current but also enable the reali:z;ation of normally-off devices.
DP2.12
Anomalous Resistance Gradient along Length of Individual
n-type GaN Nanowires Grown by Molecular Beam Epitaxy.
Paul Blanchard, Kris Bertness, Todd Harvey, Aric Sanders and
Norman Sanford; Physical Measurement Laboratory, NIST, Boulder,
Colorado.
Accurately characterizing the transport properties of seIniconductor
nanowires (NWs) is an essential step in developing and optimi:z;ing
novel nano-scale devices. However, NW metrology remains a
challenge, and new subtleties of NW behavior continue to emerge. In
this work, we characterize an anoInalous resistance gradient along the
lengths of individual GaN NWs through position-dependent I-V
measurements. The NWs in this study were Si-doped (n-type) ~ 1 1 7
cln-
3
, grown by catalyst-free MDE under static growth conditions.
NW lengths were between 15 and 20 pm, with diameters between 100
and 300 nm. Devices from individual NWs were fabricated by
dispersing NWs onto an insulating substrate, then depositing contacts
on top. In the first part of the experiInent, four ohInic contacts were
placed on each individual NW. Resistances (R
rn
) were measured
between adjacent pairs of contacts, yielding three separate values of
R= along the length of each NW. Based on the dimensions and
resistance of each section of NW, Prna,T = R rn xAxs/LNW was
calculated, where A
xs
is the physical cross-sectional area of the NW
and L
NW
is the distance between the contacts. Because the surface
depletion and contact resistance are unknown, Prnax represents an
upper limit on the NW resistivity Ps in which the NW is assumed to
have no surface depletion and negligible contact resistance. For
uniforrnly-doped NWs, one would expect Prnax to be consistent along
the length of the NW, perhaps with some random variation due to
local surface contamination or contact area differences. On the
contrary, we found that P=a.T correlated strongly with the position of
the contacts along the NW length. More than 20 individual-NW
4-contact devices were tested fronl two separate Si-doped growth runs.
On average, Pmax was a factor of 2 to 5 times higher for contacts near
the NW tips compared to contacts closer to the NW roots. In the
second part of the experiment, one ohmic contact was placed near the
root of an individual NW, and 8 Pt contacts were placed successively
along the length of the sanle NW by use of focused electron heaIn
induced deposition (FEBID) in a SEM system. After each contact was
placed, I-V was measured in-situ. R= agreed well with a model of a
uniformly-doped NW for contacts located in the first few micrometers
froIII the root, hut once again increased to a factor of lnore than 2
higher than predicted for contacts located closer to the NW tip. The
mechanism behind the gradient in resistance along the length of the
NWs is unclear. However, artifacts due to systematic differences in
device fabrication or the measurement process between the NW root
and NW tip have been ruled out. Despite the fact that conditions
were constant during each NW growth, it is clear that either the bulk
resistivity, the surface doping level, or the surface band bending is
changing along the length of each NW. Explanations for this
phenomenon are the subject of ongoing investigations.
DP2.13
Investigations of CMOS-Compatible Non-Gold
Ta/Si/Ti/Al/Ni/Ta Ohmic Contact for AlGaN/GaN HEMT
on Si with Low Contact Resistance. Yang Li, Geok I. Ng,
Subramaniam Arulkumaran, Chandra Mohan Manoj Kumar, Kian
Siang Ang, Hong Wang, Gang Ye, Rene Hofstetter and Mulagumoottil
Jesudas Anand; School of EEE, Nanyang Technological University,
Singapore, Singapore.
High Electron Mobility Transistor (HEMT) based on AIGaN/GaN
heterostructure exhibits great potential for high-power switching
applications. Recently, GaN HEMTs on large size silicon substrates
(8-inch) have been extensively explored in order to develop a
high-voluIne low-cost Inanufacturing process using the existing 8-incl:l
silicon CMOS facilities [1]. In order to process AlGaN/GaN HEMTs
in Si fabrication line, CMOS-compatible non-gold ohmic contacts with
low contact resistances are necessary [2,3]. So far, improved contact
resistance of ~ 5 !I.mm was achieved in un-doped AIGaN/GaN
HEMTs by ohInic-recess process [2]. Recently, we have deInonstrated
a CMOS-compatible non-gold (Ta/Si/Ti/ Al/Ni/Ta) ohmic contact
with low contact resistance of 0.24 !I.mm [3]. In this study, we have
systematically analyzed the ohmic contact formation by annealing at
different teInperatures. The AlGaN/GaN HEMT structure and
process details are presented elsewhere [3,4J. For this study, we used
non-gold metal stack Ta/Si/Ti/Al/Ni/Ta (5/5/20/120/40/30 nm) and
annealed at different temperatures (650degC to 850degC with the
increment of 50degC for 30 s) in a N2 environment with a rapid
therInal annealing (RTA) systeIn. The linear TLM patterns were used
for the extraction of contact resistance (Rc) and specific contact
resistivity (pc). The annealed samples exhibited smooth surface
morphology with a RMS surface roughness of ~ 5 5 n m when compared
with the conventional Ti/Al/Ni/Au ohmic contacts [4,5]. Smooth
surface lnorphology and good edge definition is essential for deep
sub-micron gate formation and good device reliability. Significant
259
reduction of Rc and pc has been observed with the increase of
annealing temperature. The 850degC annealed sample exhibited
average Rc value as low as 0.230.03 O.mm and pc of 1.01x10-6
O-cm2. This is the lowest Rc value ever reported using
CMOS-compatible non-gold ohmic contacts for un-doped AIGaN/GaN
HEMT structures on Si substrate. These values are almost equivalent
to the conventional Ti/AI/Ni/ Au ohmic contacts for similar
AIGaN/GaN HEMT structure [3,4J. For the 850degC annealed sample,
the formed Ti-silicide is touches the GaN cap layer. However, only Ta
is in contact with GaN cap layer for the sample annealed at 750degC.
This has been confirmed by XRD, HRTEM and EDX analysis. From
these results, we can conclude that the observation of low contact
resistance in this non-gold ohrnic contact is due to the furrnation of
titanium silicide alloy. 1) S. Arulkumaran et aI., JJAP 51, p.111001,
(2012) 2) H-S. Lee, et aI., EDL.32, p.623, (2011) 3) S. Arulkumaran,
et aI., APEX.6, p.016501, (2013) 4) S. Arulkumaran, et aI., APEX.4,
p.084101, (2011) 5) J.W. Johnson, et aI., EDL.25, p.459, (2004)
DP2.14
True Normally-Off AIGaN/GaN Trench MOSHFET
Fabricated by Selective Area Growth. Yao Yao, Zhiyuan He, Fan
Yang, Zhcn Shell, Jinchcng Zhang, Yiqiang Ni, Jin Li, Lei He,
Zhisheng Wu, Baijun Zhang and Yang Liu; Sun Vat-sun University,
Guangzhou, China.
Normally-off GaN-based MOSHFET have attracted significant
attention because they can realize low gate leakage and high positive
threshold voltage, which are necessary for power switching
applications. In this work, a true normally-off AIGaN/GaN trench
MOSHFET was proposed. Trench gate structure was formed by
selective area growth (SAG) technique. Si02 was used as regrowth
IIl3Sk in gate channel region, and then two SAG layers containing a
thick u-GaN (90nm) layer and a 25nm u-AIO.3GaO.7N layer were
regrown to form high quality recess region. Room temperature Hall
measurement of the regrown region showed a low sheet resistance of
2180/square, and the sinooth surface Inorphology with root lnean
squares (RMS) of 0.319nln of the regrown recess region was observed
by AFM. The device was fabricated after removing the Si02 mask
pattern. A 30nm atomic layer deposition (ALD) AI203 dielectric layer
was used to reduce the gate leakage and enhance the threshold
voltage. A high threshold voltage (Vth) of 3.29V was achieved. In
comparison with the result obtained by gate recessing method using
ICP technique [1, 2], and a true normally-off operation was confirmed
in our device from the subthreshold characteristics (the entire
subthreshold region was located in the range of Vg > OV), which was
attributed to the higher quality MaS interface in SAG schelne. The
device also had a high on/off current ratio more than 7 orders of
magnitude, which indicated a good controllability of channel by the
MOSHFET. Combined with the low gate leakage current of about
10-5mA/mm, which was improved 2 orders of magnitude when
cOlnpared to that of the conventional Schottky-gate HFET, suggested
the good insulativity of ALD-AI203 gate dielectric in GaN
MOSHFET. The maximum transconductance (gm_max) was
77mS/mm, maximum drain current density (Idmax) was 550mA/mm
at Vg = 12V and Vds = 8V, and channel mobility ('Lch) was
113cln2/Vs at V g = 12V. The results Inentioned above indicated that
the method of combining SAG and ALD-AI203 technique is a
promising scheme to fabricate high performance normally-off
AIGaN/GaN MOSHFETs for power switching applications. [lJ.
Kambayashi, H., et aI., Solid-State Electronics, 2011. 56(1): p.
163-167. [2]. Huang, W., et al. ISPSD, 2008. p.295.
DP2.15
Carrier Transport Mechanism of Low Resistance Til AllAu
Ohmic Contacts to AIGaN/GaN Heterostructures. Seongjun
Kim
1
, Eunjin .lung
1
, Munsik Oh
l
, Yunju Choi
2
and Hyunsoo Kim
1
;
ISchool of Semiconductor and Chemical Engineering, Semiconductor
Physics Research Center, Chonbuk National University, .Teonju,
.leollabukdo, Korea, Republic of; 2Korea Basic Science Institute
Suncheon Center, Suncheon, .leollanamdo, Korea, Republic of.
An exact understanding of the carrier transport mechanism of low
resistance Ohmic contact to AIGaN/GaN heterostructures is very
ilnportant for fabrication of reliable heterostructure field-effect
transistors (HFETs). Several groups have investigated this subject by
employing current-voltage-temperature (I-V-T) measurements. It was
shown that the tunneling of a two-dimensional electron gas (2DEG)
against the AIGaN barrier layer is the predominant Ohmic
lnechanisln. Liu et al. applied the therrnionic field elnission (TFE)
theory by developing the modified AIGaN barrier model involving two
barriers in series. An anomalous temperature dependence on contact
resistance was suggested to be associated with the presence of
randomly distributed TiN contact inclusions (CIs), a so-called spike
contact Inechanisln. Indeed, recent structural studies have revealed
that the generation of TiN CIs dominated Ohmic formation in the
Ti/ AI-based contact to AIGaN/GaN heterostructures. Based on these
findings, our group developed a parallel network model consisting of a
low-resistance component (TiN CIs) and a rest high-resistance region
to better understand the carrier transport mechanism of Ti/AI/ Au
Ohlnic contact to AlInN/GaN heterostructures. Using the parallel
network model, the formation of Ohmic contact was due to tunneling
of carriers through the thin barrier formed at the TiN-based CIs,
where the barrier height was 0.45 eV and the carrier density was
9.0e18 cm-3.
DP2.16
Detection of Pancreatic Cancer Biomarker (CA19-9) with
Nitride-Based High Electron Mobility Transistor Biosensors.
Wen-Ti Hsu
l
, Chia-Chang Tsai
l
, Shi-Ya Hsu
l
, Sheng-Hsiang Wang
1
,
Hung- Yuan Wang
'
, Kuang-Hung Cheng
2
, Shu-chen Hsieh
3
, Hay-Van
Wang
4
, Kung-Kai Kuo
5
, Ying SunG and Li-Wei Tu
l
; IDepartment of
Physics and Center for Nanoscience and Nanotechnology, National
Sun Yat-Sen University, Kaohsiung, Taiwan; 2Institute of Biolnedical
Sciences, National Sun Yat-Sen University, Kaohsiung, Taiwan;
3Department of Chemistry, National Sun Yat-Sen University,
Kaohsiung, Taiwan; 4Department of Biological Sciences, National Sun
Vat-Sen University, Kaohsiung, Taiwan; 5Department of Surgery,
Kaohsiung Medical University Hospital, Kaohsiung, Taiwan; 6 Dept . of
Electrical, Computer & Biomedical Engineering, University of Rhode
Island, Kingston, Rhode Island.
Semiconductor-material based field-effect transistors have been widely
used in biosensor applications for the past two decades. Alnong theIn,
the nitride-based high electron mobility transistors (nitride-HEMTs),
such as AIGaN/GaN HEMTs, are good candidate for biological
detection due to their high stability in reactive environment
(chemical/physiological solutions), not easy to be damaged by static
electricity, and silnple to be fabricated. Furtherrnore, AIGaN/GaN
HEMT structure has a high mobility two-dimensional electron gas
(2DEG) formed in the junction between the AIGaN and the GaN. The
conductance of the 2DEG conduction channel of HEMT can be easily
modulated by the surface functionalbation/detection of biomolecules,
for exalnple, the binding of antibody-antigen. In this work,
AIGaN/GaN films grown on c-plane sapphire were used as the
conduction channel of the nitride-HEMTs. The AIGaN/GaN-HEMTs
were fabricated by photolithography process. The as-fabricated
AIGaN/GaN-HEMTs were then used as biosensors to detect the
biolnarker of pancreatic cancer, CA19-9. The results show that the
CA19-9 proteins were successfully detected by nitride-HEMT with a
detection limit of about 150 unit/mL. Further investigations will be
discussed.
DP2.17
Influence of Buffer Layer on Current Collapse in AIGaN/GaN
HEMTs on Si Substrate. Wen-Chia Liao, Yan-Lun Chen and
Yue-ming Hsin; National Central University, .Thongli, Taiwan.
The detrapping behavior under current collapse test was studied in
AIGaN/GaN HEMTs on Si substrate with different buffer layers. The
epitaxial layers grown by MOCVD contain a buffer layer, a 100-nm
GaN channel layer, a 1-nm AIN interlayer, and a 30-nm AIGaN
barrier. Two different buffer layers in this study arc C-doped GaN
layer (3900-nm) and undoped AIGaN/GaN (1000/2400-nm)
combination. Devices with different buffer layers were fabricated in
same process flow with ion-implantation isolation. The methodology of
current collapse measurement is based on Prof. Jesus A. del Alamo's
study. Firstly, a device is biased into a stress condition for 100 sec.
After stress, device is biased into on-state and the drain current is
recorded from 2 ms to 20 s. After biasing device in different stress,
IDS- VDS curve and dyanmic RDS(on) under different relaxation time
can be obtained. Two kinds of stress conditions (VGS = -10 V /VDS
= 0 V and VGS = -10 V /VDS = 50 V) were tested. The experimental
results under the stress test of VGS = -10 V and VDS = 0 V show
devices have same detrapping behavior under low VDS stress.
However, as the devices stressed under the condition of VGS = -10 V
and VDS = 50 V, a detrapping tilne constant in Inillisecond level is
only observed in device with C-doped GaN buffer layer. By comparing
M. Faqir's result, the traps with millisecond relaxation time were
inferred to be located in the GaN buffer layer. Therefore, more buffer
traps are found in AIGaN/GaN HEMT with carbon doped buffer layer
than device with undoped AIO.05GaO.95N/GaN buffer and cause
current collapse as device stressing at high VDS.
DP2.18
Effects of Oxygen Annealing on Electrical Characteristics of
AIGaN/GaN HEMTs Grown on Si by MOCVD
Alexander Y Polyakov
1
, Nikolay B Smirnov
1
, Min-Woo Ha
2
,
Cheol-Koo Hahn
2
, Elena A K07,hukhova
'
, Anatoliy V Govorkov
'
,
In-Hwan Lee
3
; IInstitute of Rare Metals, Moscow, Russian
Federation; 2Korea Electronics Technology Institute, Seongnam,
Korea, Republic of; 3School of Advanced Materials Engineering and
Research Center for Advanced Materials Developlnent, Chonbuk
National University, .leonju, Korea, Republic of.
260
AIGaN/GaN HEMT structures grown by MOCVD on Si(lll)
substrate were annealed at 8000C for 5 minutes in dry oxygen, with
subsequent rcrnoval of oxide in buffered HF. Schottky diodes with
diameters from 0.4 to 1.5 mrn and concentric ohmic contacts with the
distance to the Schottky diode edge of 20 micron and 50 micron were
prepared by photolithography on mesa diodes made by dry etching.
Compared to control sample without oxygen treatment these samples
showed runch lower leakage current of the Schottky diodes with
virtually no dependence of the current density on the diode diameter
or distance to the contact ring. The threshold voltage after oxygen
treatment became slightly less negative, the interdevice insulation
resistance increased after the trcatrncnt by about two orders of
Inagnitlldc, with the activation energy of conductivity increasing frorrl
0.38 eV to 0.59 eV. PICTS spectra of the SI GaN substrate showed
deep traps with energy 0.38 eV and 0.6 eV for control sample and 0.6
eV and 0.82 eV for the oxygen treated sample. In DLTS spectra of
HEMTs a dorninant trap with ionization energy 0.6 cV was observed
in both control and oxygen treated sample under conditions probing
the AIGaN/GaN interface. These traps have parameters similar to the
ones detected by PICTS in SI substrate. Annealing and HF etching
also slightly increased the 2DEG mobility and concentration, with
total sheet resistivity increase by about 1.5 tiInes. The observed
phenomena are explained by oxidation, etching and HF passivation of
the AIGaN surface, thus suppressing the dislocation related leakage,
the surface Fermi level pinning in AIGaN, the dry etching damage and
introducing deep acceptor centers at the AIGaN/GaN interface, which
shift shift the threshold voltage to less negative value, as in other
AIGaN/GaN HEMT structures.
DP2.19
Characteristics of AIGaN/GaN MOS-HEMT on Si Substrate
with A1203/HF02 Gate Dielectrics with NH3 and TMA
Pre-Treahnent and Post-DeposItion Annealing.
Yan-Lun Chen
1
, Wen-Chia Liao
1
,2, Shih-En Yeh
1
, Chia-Wei Hsu
1
,
Zheng-Xing Chen
1
and Yue-ming Hsin
1
; lNational Central University,
Jhongli, Taiwan; 2 Joint Research Center of NCU & Delta, Jhongli,
Taiwan.
AIGaN/GaN MOS-HEMTs are attractive because of low gate leakage
and enhanced gate voltage swing due to the gate oxide, but
dielectric-AlGaN interface trap is a key issue to iInpact the
performance of AIGaN/GaN MOS-HEMT. In this study, the epitaxial
structure grown by MOCVD contain a 4000-nm buffer layer, a 300-nm
GaN channel layer, a 1-nm AIN interlayer, and a 30-nm AIO.3GaO.7N
barrier. To fabricate MOS-HEMT, high-k A1203/Hf02 (1/6 mn) gate
dielectrics deposited by ALD were used with NH3 and TMA
pre-treatments. The NH3 pre-treatment was carried out before
loading into ALD chamber, and TMA (50 cycles) pre-treatment was
performed before A1203/Hf02 deposition in the ALD chamber. After
A1203/Hf02 deposition, devices with and without post-deposition
annealing (in N2 ambient at 450C) were investigated and compared.
Device (LG = 2 I-'m and LGD = LGS = 4 I-'m) fabricated with NH3
and TMA pre-treatments and post-deposition annealing shows
reduced gate leakage current by three orders of magnitude at negative
bias of 12 V and Ion/loff ratio of E8. A device with LGD = 20 lun
shows specific on-resistance of 2.5 mOhm-cm2 and breakdown voltage
of over 800 V. The measured C-V characteristics on devices with and
without post-deposition annealing show two-step behavior in forward
and reverse bias regions. The frequency dispersion in C- V
characteristics at the onset of step (at positive VGS) is referred to the
oxide/ AIGaN interface shallower state and can be used to estimate
the effective interface state distribution (Dit). The frequency
dispersion from 1 to lOOK Hz at the onset of step (VGS of 6 V) was
Ineasured. For device with post-deposition annealing, Dit for interface
states with ore between E-5 and E-4 s (0.40 < EC - ET < 0.46 eV)
is 5.94 E12 cm-2, and the Dit for ore between E-4 and E-3 s (0.46 <
EC - ET < 0.52 eV) is 5.11E12 cm-2.
DP2.20
Selective Etching of p-GaN Layers for Nortnally-Off
AIGaN/GaN HEMTs by Electrochetnlcal Process.
Yusuke Kumazaki
1
, Naoki Azumaishi
1
, Hiroyuki Ueda
2
, Masakazu
Kanechika
2
, HideInoto TOInita
3
, TaketoIno Sato
1
and TaInotsu
Hashi7:ume
1
,4; lResearch Center for Integrated Quantum Electronics,
Hokkaido University, Sapporo, Hokkaido, Japan; 2 T he Toyota Central
Research and Development Laboratories Inc., Nagakute, Aichi, Japan;
3Toyota Motor Corporation, Toyota, Aichi, Japan; 4CREST, Japan
Science and Technology Agency, Tokyo, Japan.
A p-type GaN gate structure is often used for the normally-off
AIGaN/GaN high-electron-mobility transistors (HEMTs), in which
the p-GaN layer in the access regions should be selectively removed.
To achieve high stability and high perforrnance of the HEMT, a
damage-free etching process with good controllability is required. In
this study, we aimed to develop the selective etching process for
p-GaN layers using an electrochemical reaction. We used the
p-GaN/ AIGaN/GaN heterostrcuture grown on the Si substrate. An
ohmic contact for current supply was fabricated on the p-GaN surface.
Then, a Si02 film (100 nm) used as an etching mask was deposited on
the p-GaN surface. An electrocheInical process was conducted using a
standard cell with three electrodes: a Pt counter electrode (CE), a
reference Ag/AgCI electrode (RE), and a p-GaN electrode as a
working electrode (WE). The surface potential of the p-GaN, Vs, with
respect to RE was precisely controlled by a potentiostat. The
electrocheInical etching was carried out in the pH-controlled
electrolyte consisting of tartaric acid under the dark condition. The
reaction current curves obtained by applying the potential waveform
clearly showed the rectifying behavior with the on-set potential of
around 1.5 V. This result indicated that the corresponding potential
barrier was initially forrned at the electrolyte/p-GaN interface. After
two cycles of the electrochemical processes, the sample surface was
investigated using an atomic force microscopy (AFM). The p-GaN
surface was etched along the lines of the Si02 mask patterns. The
analysis on the AFM line profile showed the etching depth of 57 nIn
and the etching rate was roughly estimated as 30 nm/cycle for the
applied potential waveform. The rms roughness of 2.0 nm was
obtained in the range of 100 x 100 I-'m2, showing that the relatively
smooth surface was obtained after the electrochemical etching.
DP2.21
First Principles Study on the Conduction Band Electron
States of GaAsN Alloys. Kei Sakamoto and Hiroyuki Yaguchi;
Graduate School of Science and Engineering, Saitama University,
SaitaIna, Japan.
GaAsN alloys have received much attention because they have a large
band-gap bowing, i.e., a significant decrease in the band-gap energy
caused by adding N into GaAs. This unique property of GaAsN alloys
provides potential applications for high-perforrnance laser diodes and
high-efficiency solar cells. The electron effective mass of GaAsN is
investigated experimentally, for example, using electrorefiectance
(ER), optically detected cyclotron resonance, and so on. Some studies
showed that the effective Inass is heavier than that of GaAs while
others showed lighter. Furtherrnore, SOIne reported that the effective
mass decreases with increasing nitrogen concentration while others
reported the opposite tendency. Thus, the effective mass of GaAsN
has been controversial. In the present study, we have analy:tied the
electronic states of the conduction band of GaAsN alloys based on the
first-principles calculation. In order to study the nitrogen
concentration dependence of the electron effective mass, we have used
the supercell method, where a nitrogen atom is substituted for an
arsenic atom in GaAs. First, the relaxation of atomic positions was
perforrned by pseudo- potential density functional theory (DFT)
program, and then we calculated the electronic structure of GaAsN
alloys using full potential DFT program. The calculated effective mass
of GaAso.992No.008 is about twice as heavy as that of GaAs. In
addition, the effective mass is found to decrease with increasing
nitrogen, although it is always heavier than that of GaAs. These
results qualitatively support the experimental results based on ER.
Our calculation suggests the discontinuity of the physical property
from GaAs to GaAsN. In conclusion, we analyzed the conduction
band electron states of GaAsN alloys based on the first-principles
calculation and elucidated the nitrogen concentration dependence of
the electron effective mass, which provides on important insight into
the formation of the conduction band states of GaAsN alloys.
DP2.22
Nitrogen Ion Itnplantation Isolation Technology for
Nortnally-Off GaN MISFETs on p-GaN Substrate.
Hayao Kasai, Hiroki Ogawa, Nishimura Tomoaki and Tohru
Nakamura; Eelectrical Engineering, Hosei University, Tokyo, Japan.
Normally-off GaN devices are required for reali7:ing high operating
voltage, low loss and single power supply switching devices. MISFETs
fabricated on p-GaN layers are one of the promising candidates of
normally-off devices. However, leakage current due to n-type inversion
layers at the p-GaN surface and buffer layers between sapphire
substrate and GaN epitaxial layer is the major challenge to fabricate
the GaN MISFETs. We demonstrate nitrogen ion implanted isolation
technology to prevent leakage current between adjacent devices
fabricated on p-GaN layers on sapphire substrate. Leakage current
between adjacent devices with ion implanted nitrogen isolation areas
reduced five orders magnitude less than that without isolation layers.
A 1 urn thick Mg-doped p-GaN layer was grown on a sapphire
substrate by MOVPE. Silicon ions were implanted into source/drain
regions at doses of 1 x 1015 /crn2 at an energy of 50 keV through a 30
nm thick SiNx film. The SiNx film was removed and a 40 nm thick
SiNx film was deposited again, followed by activation annealing at
1200 oC for 2 min. Nitrogen ions were implanted into field regions to
isolate adjacent devices at the dose of 3.5 x 1014 and 1 x 1015 /cm2
at energies of 30 and 80 keV and the both energies through the SiNx
film. Source/drain ohmic contacts and a gate electrode were formed
by depositing Ti/ Al (50/300 nm) layers. Finally, the sample was
annealed at 550 oC for 1 min. A profile of the displacement gallium
261
atoms or damage layers generated by nitrogen ion implantation was
taken by 1.5 MeV He ion Rutherford Backscattering
Spectroscopy(RI3S) technology. The profile showed that the
concentration of surface damages of the samples implanted at an
energy of 80 keY was lower than that of 30 keY. DC characteristics of
the fabricated GaN MISFET and leakage current between adjacent
MISFETs were also measured. Maximum drain current of 10 mA/mm
at Vg=10 V, rnaxirnlun transconductancc of 2.7 rnS/nun and
threshold voltage of +1.5 V were obtained for 2 um gate MISFETs on
p-GaN with carbon concentration of 7.2 x 1017 /cm3. Leakage current
below 10-9 A at 10 V between adjacent devices having isolation areas
fabricated at cncrgies of 30 and 80 keV was obtained. On the other
hand, the lcakagc currcnt betwecn devices without isolation areas was
about 10-4 A. We have demonstrated that the leakage current greatly
reduced by using nitrogen ion implantation. Nitrogen ion implanted
isolation technology will become essential for fabricating devices on
p-GaN substrate.
DP2.23
High Performance Normally-Off Self-Aligned Metal Gate
GaN MISFETs on Free Standing GaN Substrates.
Hiroki Ogawa
1
, Hayao Kasai
1
, Naoki Kaneda
3
, Tornonobu Tsuchiya
2
,
Tornoyoshi Mishirna
3
and Tohru Nakarnura
1
; IDept. of Electrical and
Electronics Eng., Hosei University, Koganei, Japan; 2Central Research
Lab., Hitachi Ltd., Kokubumji, Japan; 3Research & Development
Lab., Hitachi Cable Ltd., Tsuchiura, Japan.
Wc dernonstrate nonnally-off rnode Mo-gate ion-irnplanted GaN
MISFETs in a GaN p-type epitaxial layer on free standing GaN
substrate with high resistivity carbon doped layer. Since N vacancies
act as donors in GaN[1] and since surface inversion layers due to
surface damages in p-GaN layers cause leakage current, we fabricated
isolation regions using nitrogcn ion irnplantation to prevent leakage
current between adjacent devices at N vacant GaN surface. Fabricated
MISFETs showed that the drain current was considerably higher than
GaN MISFETs on sapphire substrates. Moreover the leakage current
greatly rcduccd by using nitrogcn ion irnplantation. The starting
rnatcrials arc MOCVD grown p-GaN with Mg conccntration of 5 x
1017 /cm3 on free standing GaN substrates with carbon concentration
of 7.2 x 1017 /cm3, 2.2 x 1016 /cm3 and 1.1 x 1019 /cm3. A 30 nm
thick SiNx gate dielectric film was deposited on p-GaN by sputtering.
The rnetal gates werc fonncd by depositing Mo (200nrn). Si ions wcre
implanted into source/drain regions at the dose of 1 x 1015 /cm2 at
an energy of 50 keY through a SiNx layer, which were self-aligned to
the Mo gate electrodes. The 50 nm thick Si02 was deposited by
sputtering followed by activation annealing at 1100 oC for 2 min in
N2 arnbicnt. After rernoving the Si02, N ions were irnplanted into
field regions to isolate adjacent devices at the dose of 1 x 1015 at an
energy of 150 keY through the SiNx layer. Source/drain ohmic
contacts were formed by depositing Ti/ Al (30/200 nm) layers,
followed by the thermal annealing at 550 oC for 1 min. The fabricated
devices with rninirnurn gate length of 2 urn and a gate width of 50 lun
were tested. DC characteristics of the fabricated GaN MISFET were
measured. Maximum drain current of 98 mA/mm at Vg=10 V,
maximum transconductance of 10 mS/mm and threshold voltage of
+0.4 V were obtained on p-GaN with carbon conccntration of 7.2 x
1017 /crn3. The rnaxirnurn drain currcnt of MISFETs fabricated on
p-GaN on free standing GaN substrates was much higher than that on
sapphire substrates. When the distance and applied voltage between
adjacent devices were 5 urn and 30 V, respectively, the leakage current
for p-GaN on frce standing GaN substratc was below 10-10 A, which
is much smaller than that of p-GaN on sapphire substrate. We have
demonstrated normally-off GaN MISFETs on free standing GaN
substrates with self-aligned structure. The positive threshold voltage
and high drain current show the potentials and advantages of GaN
MISFETs for high voltage, current applications. [1] H. Ishikawa et a!.,
J. App!. Phys. 81 (3), p. 1315 (1997)
DP2.24
A New Gate Structure Overlapping Source for Low
On-Resistance in AIGaN/GaN MOS-HEMTs. Ogyun Seok,
Woojin Ahn, Jeong-Soo Lee, Soo-Yeon Lee and Min-Koo Hani Seoul
National University, Seoul, Korea, Republic of.
Wc proposed and fabricatcd a new gate structure in the AIGaN/GaN
MOS-HEMTs for low on-resistance without any additional process
step. Also, the effects of LGD and on the reduction ratio of Ron,sp
was investigated. In the proposed devices, the TaN-gate overlapped
the source with 15 nm-thick RF-sputtered Hf02 insulation while the
conventional HEMT didn't includc the overlap region. We obtained a
low specific on resistance (Ron,sp) of 2.28 m!lcm2 by using the
proposed gate structure at LGD of 10 Mm while the conventional
MOS-HEMT had 2.91 m!lcm2. GaN (3 nm)/ AIO.23GaO.77N (20
nm)/i-GaN (100 nm)/C-doped GaN (3.9 Mm) on Si substrate was
used. The 3 l.LIn-Iong LGS and 3 l.LIn-long LG were used for the
conventional MOS-HEMTs. Ti/Al/Ni/ Au (20/80/20/100 nm) and
TaN (43 nm) were used for source/drain and gate, respectively. 15
nm-thick Hf02 gate insulator resulted in small VTH shift of 1.1 V due
to high-k characteristics. High breakdown field of Hf02 gate insulator
enables stablc on/off switching by sustaining positive and negative
VGS. The maximum drain current at VGS of 2 V and 10 Mm-long
LGD was increased from 332 to 420 mA/mm. The improvement in
Ron,sp and drain current agrees well with the removed LDS (3 Mm)
by the overlapping gate structure. The proposed gate structure with
short LGD was rnore helpful to rcducc on-resistance becausc short
LGD allowed showed large ~ L S L S value. The breakdown voltage
and drain leakage current were not significantly altered by the
overlapping gate structure because same LG and LGD were used as
the conventional devicc. LG and LGD are key factors decide the
breakdown voltagc. At LGD of 10 l.LIn, the conventional device and
the proposed one had breakdown voltage of 1410 and 1460 V,
respectively. Those values were not increased by much with LGD due
to gate-substrate conduction and breakdown at the high drain-source
voltage. For thc rcasons, we obtained highest figure of rnerit of 872
MWcm-2 in the proposed device with 10 Mm long-LGD.
DP2.25
Simulation of Membrane Thickness Effect on Piezoelectric
Pressure Sensor Sensitivity. Jaroslav Dzuba
1
, Gabriel Vanko
1
,
Milan Dr:dk
2
, Vladimir Kutis
3
, Martin Vallo
1
, Ivan Ryger
1
and Tibor
Lalinskyl; 1 Department of Microelectronics Structures, Institute of
Electrical Engineering, Slovak Academy of Sciences, Bratislava,
Slovakia; 2International Laser Centre, Bratislava, Slovakia;
3Department of Applied Mechanics and Mechatronics, Institute of
Power and Applied Electrical Engineering, Slovak University of
Technology, Bratislava, Slovakia.
In previous work, AIGaN/GaN based circular high elcctron rnobility
transistors (C-HEMTs) have been introduced and simulated as
piezoelectric pressure sensors [1, 2]. They consist of a parallel plate
piezoelectric capacitor with Schottky gate as a first electrode and the
two dimensional electron gas (2DEG) in the role of the second
electrode. Thc circular syrnrnetry of the 2DEG channel is fully
compatible with the circular AIGaN/GaN membrane structure
required for MEMS pressure sensor design. Operating range of the
sensor presented in this work is strongly affected by two factors: (a)
residual stress in thc rnernbrane and (b) rnernbrane thickncss. Due to
cornplicated evolution of residual stress during hetcrostructure growth,
it has to be experimentally determined. Resonant frequency method
was used to determine the stress state of our MEMS membrane [3]. To
obtain natural frequencies of the membrane, modal FEM simulation
was also perfonncd. Results of rncasurernent were then cornpared with
those of simulation and finally, residual tensile stress of 40 MPa was
taken as an initial state of the membrane. In the following Ansys
simulation, the model of a 4.2 Mm thick AIGaN/GaN membrane
structure previously grown on 450 /-Lm thick Si substrate was created
according to the real fabricated structures. In ordcr to find the
optimal working window for pressure sensing, the overall membrane
thickness in combination with remaining Si substrate was changed
(4.2 Mm of AIGaN/GaN and 0-50 Mm of Si). 2-D model of circular
membrane pressure sensor was then loaded by external differential
pressure. The rnaxirnal possible loading (to prevcnt rnernbrane
cracking [4]) decreases with decreasing membrane thickness. However,
the sensor sensitivity increases due to enhanced maximal deflection.
[1] T. Lalinsk-*acutey*-, M. Drzik, G. Yanko, M. Vallo, V. Kuti",
J. Bruncko, -*ucarons*-. Hascik, J. Jakovcnko, M. Husak,
Microelectronic Eng. 88 (2011), Pl'. 2424-2426. [2] J. Dwba, T.
Lalinsk-*acutey*-, G. Yanko, M. Vallo, I. R-*acutey*-ger, V.
Kuti", V. Knilovic, Proceedings of the 13th Mechatronics Forum
Conference in Linz, Austria (2012), Pl'. 773-778. [3] M. Drzik, H.
Loschncr, E. Haugcncder, W. Fallrnan, P. Hudak, I. W. Rangelow, Y.
Sarov, T. Lalinsk-*acutey*-, J. Chlpik, Microelectronic Eng. 83
(2006), Pl'. 1036-1042. [4] edited by J. I. Pankove, T. D. Moustakas
(Eds.), Semiconductors and Semimetals, Gallium Nitride (GaN) II,
Vo!' 57, Academic, San Diego, 1991, p. 292-297.
DP2.26
Mo-Based, Au-Free Process for AIGaN/GaN-on-Si
Heterostructure Power FETs. Shinhyuk Choi, .lae-Gil Lee,
Ho-Young Cha and Hyungtak Kirn; Elcctrical Engineering, Hongik
University, Seoul, Korea, Republic of.
Au-free AIGaN/GaN heterostructure field effect transistors (HFETs)
on Si substrate have been fabricated using Mo- based metallization. A
Si/Ti/ Al/Mo rnetal stack was investigated for ohrnic rnctallization
where the thickness of each layer and annealing temperature were
optimized to achieve low contact resistance and smooth surface
morphology. In addition, a recess process was carried out prior to
ohmic metalli:tiation to further optimi:tie the ohmic process. The
optirnized rnetal stack and anncaling conditions wcre thc
Si/Ti/AI/Mo of 5/40/60/50 nm and rapid thermal annealing in N2
ambient at 870 0 C for 60 sec, which resulted in a contact resistance of
0.76 !I-mm and a sheet resistance of 300 !I/sq. In comparison, an
Au-based ohmic process, which was also optimi:tied, exhibited a
262
contact resistance of 0.36 n-mm and a sheet resistance of 293 n/sq. It
should be noted that superior surface smoothness and edge acuity
were achieved for the Au-free ohrnic process; a root ruean square
surface roughness for Au-free and Au-based ohmic processes were
4.819 and 21.231 nm, respectively. The optimized Au-free process was
employed to fabricate AIGaN/GaN-on-Si HFETs where a Ni/ Al/Mo
(=20/110/30 nm) was utilized for gate and field plate metallization.
Conventional Au-based AIGaN/GaN-on-Si HFETs were also
fabricated for comparison. The source-to-gate distance, gate length,
field plate length, and gate-to-drain distance were 3, 2, 1.5, and 10
/Lm, respectively. A maximum drain current density of 653 mA/mm
was achieved for the Au-free device which was 94 % of that for the
Au-based device. The extracted on-resistance for Au-free and
Au-based devices were 1.169 and 0.944 mn-cm2, respectively. No
noticeable difference was observed in breakdown characteristics. Both
samples exhibited a breakdown voltage of 610 V. We have successfully
developed an Au-free process for AIGaN/GaN HFETs and the
prototype device exhibited excellent and comparable characteristics in
comparison with conventional Au-based HFETs. Currently, long term
reliability of both samples is under investigation.
DP2.27
Evaluation of an InAIN/A1N/GaN HEMT with Ta-Based
Ohmic Contacts and PECVD SiN Passivation. Anna Malmros
1
,
Piero Gamarra
2
, Mattias Thorsell
l
, Marie-Antoinette di
Forte-Poisson
2
, Cedric LacaIn
2
, Maurice TordjInan
2
, Raphael Aubry2,
Herbert Zirath1 and Niklas Rorsman1; 1 Microtechnology and
nanoscience (MC2), Chalmers University of Technology, Gothenburg,
Sweden; 2 3_5 Lab/Thales Research & Technology, Marcoussis, France.
An InAIN/AIN/GaN HEMT with Au-free Ta-based ohmic contacts
and a high-quality PECVD SiN passivation is reported. The
MOVPE-grown heterostructure consisted of a 6 nm undoped nearly
lattice matched InAIN layer and a 2nm thick AIN layer on top of a
GaN buffer. We show that ohmic contacts to this heterostructure may
be fabricated using a Ta/ Al/Ta metallization. Annealing at 550 0 C
yielded a contact resistance of 0.64 Omm and a very smooth contact
surface morphology. The HEMT had a gate width of 2 x 50 /Lm, a
source - drain distance of 1 /Lm and a nominal gate length of 25 nm.
The device perforrnance and the process were evaluated by perforrning
DC-, pulsed IV-, and RF IneasureInent. Essential inforrnation on the
impact of the passivation layer was obtained by comparing the results
from the non-passivated and the passivated device. A notable result
was the extremely low gate leakage prior to passivation. However, the
gate leakage increased by several orders of Inagnitude after
passivation, but was still reasonably low for a GaN HEMT 1
mA/mm). On the contrary the channel current density increased by
62 % to 1240 mA/mm at zero gate bias, and the DC
transconductance increased from 382 to 477 mS/mm after passivation.
Results froIlI pulsed IV IneasureInents revealed that the surface was
effectively passivated by the SiN. The current slump ratio increased
from 69 to 91 % when performing pulsed measurements from a
quiescent biasing of (Vgs, Vds) = (-10, 0) V to a pulse level of (Vgs,
Vds) = (0, 10). Hence gate lag due to surface traps was efficiently
suppressed. Extrinsic IT and fInax were 90 and 207 GHz, respectively,
before passivation. fmax decreased considerably after passivation to
140 GHz, whereas IT remained unchanged. The drop in fmax is
associated with the increase in output conductance after passivation.
DP2.28
Photoelectrochemical Properties Depending on pH of
Electrolyte. Hyojung Bae
1
, Akihiro Nakamura
2
, Kayo Koike
2
,
Hyung-Jo Park
3
, Tak Jeong
3
, Hyo -Jong Lee
4
, Katsushi Fujii
2
and
.lun -Seok Hal; lChonnam National University, Gwangju, Korea,
Republic of; 2University of Tokyo, Tokyo, Japan; 3Korea Photonics
Technology Institute, Gwangju, Korea, Republic of; 4 Dong-A
University, Busan, Korea, Republic of.
In this abstract, we report effect of electrolyte pH on
photoelcctrochemical (PEC) properties of c-plane GaN grown by
metal-organic chemical vapor deposition (MOCVD). GaN has carrier
concentration of 2.09E17 /cm3, thickness of 2E-6 m and mobility of
5.28E2cm2/Vs. In order to investigate effect of electrolyte pH, H2S04
(pH 0.2), Na2S04 (pH 6.3) and NaOH (pH 14.0) electrolytes were
used. After C- V, cyclic voltaInInetry IneasureInent, we can evaluate
flat-band potentials and photocurrent densities from dependence of
electrolyte pH. The flat-band potential is important because it affect
decision of turn-on voltage. It is generally recognized that the
flat-band potential corresponds with Nernst equation, E =Eo -
0.059pH V vs. SHE. I3ut flat-band potential obtained under Na2S04
electrolyte was out of accordance with Nernst equation (Fig.1). It is
might be due to other factors such as degree of ionization. Therefore,
in this study, we can know that Na2S04 electrolyte not corresponds
with Nernst equation and choice of electrolyte is iInportant. Fig.2
shows photocurrent densities as a function of the bias vs. the Pt
coun-terelectrode (CE). Turn-on voltage obtained under Na2S04
electrolyte is larger than that under other electrolyte. It indicates
there is some resistance at interface electrode with electrolyte and this
resistance influences large turn-on voltage. Finally in this study, we
can know that Na2S04 electrolyte not corresponds with Nernst
equation and choice of electrolyte is important.
DP2.29
Degradation of OFF-State Leakage Current in AIGaN/GaN
HEMTs Induced by an ON-State Gate Overdrive. I3aikui Li,
Kevin J. Chen, Qimeng Jiang, Shenghou Liu and Cheng Liu; HKUST,
Kowloon, Hong Kong.
In GaN RF/power electronic devices, lower OFF-state leakage current
is always preferred. Besides energy dissipation consideration, the
OFF-state leakage current also directly affects breakdown voltage
and/or the device reliability. In this work, we studied the effect of
ON-state gate overdrive on the transient OFF-state leakage current of
AIGaN/GaN HEMTs. Ni/ Au is used for the Schottky gate electrode.
Transient behaviors of OFF-state drain and gate leakage currents
were recorded after an ON-state gate overdrive. The dependences on
gate drive bias (from 2.3 to 3.0 V) and gate drive duration (from 0.01
to 10 s) were investigated. It was found that when the gate bias
exceeded 2.5 V, the OFF-state drain leakage current (Ineasured after
the gate bias was reduced to below the pinch-off) increased
significantly while the change of gate leakage current was small. With
a 3-V / 10-s ON-state overdrive to the gate, the OFF-state drain
leakage current increased by three orders (from 10-6 to 10-3 mA/mm).
It takes Inore than 20 s for the de-gradated drain leakage current to
recover to its original level (in dark) which is dominated by the gate
leakage. The recovery processes of the drain leakage current follows a
stretched-exponential law. Electroluminescence with a corresponding
GaN band-edge emission energy has been observed from a forward
biased Ni/ Au-AIGaN/GaN Schottky diode. Photons emitted during
the ON-state overdrive can pump electrons trapped at deep levels
(donor-like or acceptor-like) in GaN buffer layer, lower the energy
band in the buffer layer and subsequently leads to larger buffer
leakage. This work indicates that gate overdrive protection is
necessary to preserve low transient OFF-state drain leakage current
and improve device reliability.
DP2.30
Experimental and Theoretical Investigations into Sensitivity
of Ungated Reference Electrode Free A1GaN/GaN-Based Ion
Sensors. Anna Podolska
l
, Daniel Broxtermann
2
, .loerg Malindretos
2
,
Gilberto Umana-Membreno
1
, Stacia Keller
3
, Umesh Mishra
3
, Agela
Rizzi
2
, Brett Nener
l
and Gia Parish
l
; lThe University of Western
Australia, Crawley, Western Australia, Australia; 2IV. Physikalisches
Institut, Georg-August Universitat Gottingen, Gottingen, Germany;
3Department of Electrical and Computer Engineering, University of
California, CA, Santa Barbara" California.
Miniaturisable transistor-based sensors are of great interest for
chip-based chemical and biological sensing. Such sensors must be
robust and reliable to replace existing glass electrode pH and ion
sensing. Realisation of reference electrode free measurements is
extreInely iInportant to keep these devices sInall and on-chip.
AIGaN/ GaN transistors have been investigated over the past decade
as a chip-based sensor technology. However successful demonstrations
of reference electrode free operation have been rare. Only recently
have theoretical calculations for AIGaN/GaN HEMT parameters, such
as carrier charge density and Inobility variation with gate voltage
and/ or drain source voltage, been used in an attempt to explain the
behavior of ungated AIGaN/GaN HEMT devices used in sensing [1].
Even less has been published regarding systematic investigations of
reference electrode free operation, despite a few successful
deInonstrations of pH sensing [2,3J. Also the Ineasure of sensitivity in
the absence of a reference electrode has not been explored. The gain
in IDS or VDS per unit pH is an excellent direct measure of
sensitivity and is used in this work. Here we present an investigation
into iInproved charge sensitivity of ungated reference electrode free
AIGaN/GaN ion sensors based on experimental results and theoretical
modelling. Our results indicate strong dependence of sensitivity on
AIGaN/GaN barrier thickness and composition as well as strong
sensitivity variation as a function of VG. These results are important
for understanding and optiInisation of a reference electrode free
measurement approach. References [1] S. Rabbaa et aI., J. Phys. D:
Appl. Phys., 45(47), p. 475101, 2012. [2] A. B. Encabo et aI., Sens.
Actuators, 13,142, pp 304-307, 2009. [3] T. Brazzini et aI., Sens.
Actuators, 13, 176, pp. 704-707, 2013.
DP2.31
Novel Dual-Channel AIN/GaN HEMT for Mitigation Of
DC-RF Frequency Dispersion. David Deen1,2, Andrei Osinskyl
and Ross Miller
l
; 1 Agnitron Technology, Eden Praire, Minnesota;
2Electrical and COInputer Engineering, University of Minnesota,
Minneapolis, Minnesota.
III-Nitride high electron mobility transistors (HEMTs) are becoming
263
increasingly prevalent in high voltage, high frequency switch-mode RF
applications currently occupied by vacuum electronics. GaN based
HEMTs possess the intrinsic rnatcrial properties and innovative
heterostructure architecture possibilities to offer superior
application-specific performance over conventional Si based
technology, extending the capabilities of solid state devices to higher
frequencies and voltages. Highly efficient GaN HEMT power
arnplificrs have been dcrnonstratcd at low frequencies, but device
performance is still limited by current collapse and DC-RF dispersion.
In the off state, uncompensated surface charge collects near the gate
contact. The long-lifetime states trap charge density which continues
to partially deplete the channel after the device voltage is turned OIl,
leading to a "gate lag" and poor depIction control at high frequencies.
The current benchmark to decrease the effects of gate lag often
decreases electron mobility from damage caused during the deposition
of a passivating Si3N4 capping layer. We propose a novel
patent-pending HEMT device design with a dual-2DEG channel to
mitigate the gate lag which results from the build-up of surface charge
density. The upper 2DEG serves to screen the electric potential of the
surface charge from the primary, recessed gate-modulated 2DEG
channel located below. Preliminary device simulations indicate that
engineering 2DEG charge densities for low threshold voltages is
possible through GaN and AlGaN layer thickness optimi7,ation. Novel
GaN based dual-channel HEMT design is befitting for device topology
that intrinsically maintains high mobility and thin device geometry,
permitting increased breakdown voltage, higher frequency switching,
and efficient power aInplification. This innovative HEMT design will
enable high voltage/power switch-mode operation at frequencies
extending beyond the K band into the millimeter wavelength,
potentially replacing the vacuum tube technology currently used in
millimeter wave radio communications and radar.
DP2.32
Surface Potential Study of III-Nitrides Epilayers and
Nanowires by Atomic Force Microscopy. Albert Min/, A. Cros'.
N. Garro
1
, A. Urban
2
, J. Malindretos
2
, A. Ri:ti:i..j2, D. Cavalcoli
3
, A.
Cavallini
3
, O. Tuna
4
, C. Giesen
4
and M. Heuken
4
,5; lInstitut de
Ciencia dels Materials, Universitat de Valf!ncia, Paterna, Valencia,
Spain; 2IV. Physikalisches Institut, Georg-August-Universtat
Gottingen, Gottingen, Germany; 3Department of Physics and
Astronomy, University of Bologna, Bologna, Italy; 4 AIXTRON SE,
Herzogenrath, GerrnanYi 5GaN Device Technology, RWTH Aachen
University, Aachen, Germany.
The efficiency of the optical and electronic devices based on group-III
nitrides is hindered by the difficulty in growing high quality epitaxial
layers, due to the large lattice Inisrnatch and differences in therrnal
expansion coefficients between them and the most commonly used
substrates. As a result, highly strained epilayers are prone to
relaxation by non-elastic processes, leading to the formation of
structural defects such as threading dislocations (TDs) and misfit
dislocations (MDs). Defects such as TDs arc of great debate in
III-nitrides, as we still lack a general consensus on their electronic
properties concerning their charge state, their role in leakage current
and their effectiveness as non-radiative recombination centers. Other
than planar-structures, nanowires (NWs) have a unique potential to
act as piezoelectric sensors and show iInproved perforrnance as
optoelectronic devices. Even though NWs should present a lower
density of structural defects, new and recent results evidence defect
formation, such as stacking faults. Owing to their nanometer si:tie of
defects and NWs, it becoInes very difficult to study electrical and
optical properties of individual NWs. Taking advantage of high
precision of atomic force microscopy over nanometer scale and no
requirement of complicated sample preparation, we have probed
individual TDs, V-defects and MDs in a wide range of III-nitride
layers, including GaN, InGaN and AlInN alloys in order to study their
electrical properties. We have identified the charge state of the
dislocations and their effect on the leakage current. This was done
using a variety of scanning probe microscopy methods, such as Kelvin
Probe Force Microscopy (KPFM) and Conductive Atomic Force
Microscopy (C-AFM), including Electron DeaIn Induced Current
(EBIC) to measure the recombination strength of the defects. The
same methods were also applied to GaN NWs (both self-assembled
and selectively grown on Si and GaN/Sapphire substrate) with
different polarities and si:ties. Their measured diameters varied from 10
nrIl to 400 nrn with the length of approxiInately 1 rLIn. TEM
(including SEM) analysis suggests that these NWs contain stacking
faults and cracks. Using KPFM measurements on individual NWs, we
have distinguished the electrical properties of N-polar and Ga-polar
GaN NWs and identified the presence of p-n junctions present in
partially Si and Mg-doped NWs (i.e. in terrns of their work function).
The same method was further extended to verify the charge state of
the structural defects present in NWs.
DP2.33
A Low Temperature GaN Spacer to Alleviate InAlN
Degradation in High Temperature Growth Process.
Jieqin Ding
1
,2, Xiaoliang Wang
1
,2,3, Honglin Xiao
1
,2, Chun Feng
1
,2,
Cuimei Wang,,2 and Zhanguo Wang,,2; 'Key Lab of Semiconductor
Materials Science, Institute of Semiconductors, Beijing, China;
2Deijing Key Laboratory of Low DiInensional SeIniconductor
Materials and Devices, Institute of Semiconductors, Beijing, China;
3ISCAS-XJTU Joint Laboratory of Functional Materials and Devices
for Informatics, Institute of Semiconductors, Beijing, China.
During the past few years, significant progresses have been reported in
the development of high performance nitride-based electronic devices,
especially in high electron mobility transistors (HEMTs). Advanced
device structures are being investigated for further performance
irnprovernent. For sorIle structures, low teInperature to high
teInperature (LT-to-HT) growth process are necessary due to the low
growth temperature of InAl(Ga)N layer with respect to GaN or
AI(Ga)N. A key issue is the degradation of InAIN quality during the
high temperature growth process. Therefore, the growth temperature
variation frorn LT-to-HT can rnake a significant irnpact on the whole
structure quality. In this work, AIGaN/lnAIN/AIN/GaN HEMT
structures were grown on c-face sapphire substrates by metal-organic
chemical vapor deposition. A low temperature GaN interlayer was
deposited between the AIGaN and InAIN layer in order to reduce the
risk of InAIN degradation. The structure revealed an average sheet
resistance of 324.1 O/sq, with the resistance un-uniformity as low as
1.15%. The grown material structures were then processed to devices.
For a single-cell HEMT device of 60 pm gate width, a maximum drain
current density of 1031 mA/mm, an extrinsic transconductance of 170
rIlS/rIlrn were achieved. This experirnent contributes to alleviating the
InAlN degradation in high temperature growth process.
DP2.34
Trap States In InAIN/AIN/GaN-Based Double-Channel High
Electron Mobility Transistors. Zhang Kai, Xue JunShuai, Mi
MinHan, Zhang JinCheng, Ma XiaoHua and Hao Yue; Key
Laboratory of Wide Band Gap Semiconductor Materials and Devices,
School of Microelectronics, Xidian University, Xi'an, Shannxi, China.
Recently, lattice-matched InAIN/GaN heterostructures have become a
promising alternative to conventional AIGaN/GaN-based HEMTs.
Nevertheless, an excess leakage current of Schottky contact has been
discovered as the most significant limiting factor for the reali:tiation of
its high power applications. Another possible constraint on power
output is the unknown current collapse phenomenon probably related
to surface/bulk defects in the system, as is unavoidably present in
AIGaN/GaN HEMTs. For these reasons, the identification of trap
states quantitatively in the InAIN-based devices is of great necessity
to understand the irnpact of trap states on device perforrnance. In our
previous work, lattice-matched InAIN/GaN double heterostructures
were grown by pulsed metal organic chemical vapor deposition
(PMOCVD) at Xidian University [1][2]. Here, we present a detailed
analysis of trap states by frequency dependent conductance
rIleasureInents in conjunction with photo-assisted C-V rIleasureInents.
Up to ~ E 4 /cm2/eV of trap states was yielded to be present at
the higher InAIN/AIN/GaN interface. We assume the substantial
amount of shallow traps at the higher InAIN/ AIN/ GaN interface may
partially be responsible for higher gate leakage current when
compared to AlGaN barrier HEMTs. Nevertheless, the
InAlN/ AIN/ GaN interface was uniform as confirmed by the excellent
fitting results, demonstrating the validity of PMOCVD growth
approach for InAIN/ AIN/GaN heterostructures. In contrast, density
of interface traps at the lower InAIN/ AIN/ GaN interface showed
nearly two orders of magnitude lower. This is believed to be the result
of the introduction of novel LT-GaN interlayer, protecting InAIN
barrier from the subsequent high temperature GaN growth and
annealing process. Moreover, a low density of deep-level traps
(1.79xl0Ell /ern2) located at the interface between LT-GaN and the
bottom InAIN barrier was achieved by photo-assisted C- V analysis.
The results presented suggested that further enhancement in electrical
properties of single InAIN/ AIN/ GaN heterostructure can be realbed
by adding passivation layer on InAIN barrier (such as LT-GaN). [1] J.
S . Xue, J. C. Zhang, Y. W. Hou, H. Zhou, J. F. Zhang, and Y. Hao,
Appl. Phys. Lett. 100, 013507 (2012). [2] J. S . Xue, J. C. Zhang, K.
Zhang, Y. Zhao, L. X. Zhang, X. H. Ma, X. G. Li, F. N. Meng, and Y.
Hao, J. Appl. Phys. 111, 114513 (2012).
SESSION D4: Novel Nitride Electronic Devices and
Concepts
Chair: Yvon Cordier and Andrei Vescan
Wednesday Morning, August 28, 2013
Chesapeake 4-6
8:30 AM D4.01
Demonstration of III-Nitride Tunnel-Injection Hot Electron
Transfer Amplifiers (THETA). Digbijoy N. Nath, Zhichao Yang,
Pil S. Park and Siddharth Rajan; The Ohio State University,
ColuInbus, Ohio.
264
We report on the design and demonstration of the first III-Nitride
tunnel-injected hot electron arnplificr transistor (THETA). Vertical
devices are promising candidates for achieving high frequency
operation due to the high transconductance and ability to engineer
electron transport over very short distances. Unlike InP and SiGe
HBT technologies, bipolar GaN devices are challenging due to poor
hole properties. In this work, we dcrnonstratc tunnel injection vertical
transistors based on III-nitrides with current transfer ratio >0.90. A
THETA is based on tunnel-injecting electrons through an emitter
barrier followed by ballistic transport to the collector through a thin
basco A thin heavily doped base is desired to rninirnizc electron
relaxation and base sheet resistance. Hot electrons which do not relax
in the base travel ballistically and are collected by a reverse biased
collector. Detailed calculations for the III-nitride THETA will be
described to show that cutoff frequencies> 1 could be achieved
by exploiting tUIlIleling injection and ballistic transport. The
MBE-grown epitaxial stack consisted of 3.5 nm AIO.3GaO.7N emitter
barrier, degenerately doped GaN base, a thin In.15Ga.85N induced
electrostatic base-collector barrier with 7 nm UID GaN and A1GaN
graded from 20% to GaN as confirmed with XRD scan. We find
randorn alloys based OIl AIGaN do not provide base/collector current
blocking and adopted an approach using a polari:z;ation engineered
non-random alloy barrier with significantly lower leakage. A base
thickness series of 21.5, 12.5, 9 and 7.5 nm will be presented.
Ti/ Au/Ni emitter metallbation, Cl2-based ICP-RIE self-aligned base
etch, AI/Ni/ Au/Ni base contact, collector Inesa etching and collector
contact evaporation were done. The emitter area was 10 pm2 and
base mesa area was 100 11m2. The base-emitter I-V showed no
temperature dependence indicating tunnel injection. Emitter current
densities 100 kA/cm2 were observed. The base-collector leakage was
<10 A/cm2 at 1 V while the base-to-base I-V between two base pads
of a device showed Ohmic behavior and low base sheet resistance.
Devices exhibited clear output modulation (IC-VCE) in common
emitter configuration with emitter grounded. output current IC was
observed to increase as the input bias VI3E was increased. The
GUlnInel plot showing collector current as a function of elnitter bias at
zero base collector shows that large fraction of injected electrons
travel ballistically to the collector. For the four THETA samples with
base thicknesses 21.5 nm, 12.5 nm, 9 and 7.5 nm, the highest current
transfer ratio, (e>, defined as IC/IE) of 0.05,0.10, 0.45 and >0.9 were
observed which was found to follow an exponential dependence on
base thickness as exp(-t/1.8 nm). This indicated that an increasing
fraction of injected electrons travel ballistically as the base thickness
is decreased. In conclusion, we show the design and demonstration of
the first vertical tunneling based unipolar III-nitride devices with low
leakage, high current gain, and ballistic transport with potential to
terahertz electronics. This work is funded by Office of Naval Research
under the DATE MURI project (Program manager: Dr. Paul Maki).
8:45 AM D4.02
Novel p-channel HFET Using Polarization-Induced
Two-Dimensional Hole Gases at Metal-Polar GaNjAlInGaN
Interfaces. Benjamin Reuters
1
,3, Herwig Hahn
1
,3, Alex Pooth
1
,3,
Bernd Hollaender
2
,3, Michael Heuken,,4, Holger Kalisch',3 and
Andrei Vescan
1
,3; 1GaN Device Technology, RWTH Aachen
University, Aachen, NRW, Gerrnany; 2 P GI9-IT, Forschungszentruln
Julich GmbH, Julich, NRW, Germany; 3JARA-Fundamentals of
Future Information Technologies, Julich, NRW, Germany;
4AIXTRON SE, Herzogenrath, NRW, Germany.
Nitride-based heterostructure field effect transistors (HFET) utili7,ing
a two-dimensional electron gas (2DEG) have been extensively studied
for high-power and high-frequency applications. Less attention has
been paid to p-channel devices using a two-dimensional hole gas
(2DHG) due to the difficulty in both realization and analysis. Reasons
for that might be higher sheet resistances due to a low hole mobility
and that ohmic contact behaviour is challenging. Here, the formation
of 2DHG is presented and p-channel transistors are demonstrated. The
carrier density in the 2DHG is adjusted by the polarbation difference
between quaternary AlInGaN backbarriers and a GaN channel on
top. By variation of the AlInGaN composition the threshold voltage
can be shifted. With appropriate polarization-engineered
heterostructures, depletion mode and enhancement mode p-channel
transistors are for the first time. The layer stack grown by
metal organic vapor phase epitaxy (MOVPE) in an AIXTRON reactor
consists of a semi-insulating A1N/GaN buffer layer on sapphire
followed by a 35 nm thick AlInGaN backbarrier and a 3 nm thick
unintentional doped GaN channel. At the GaN/ AlInGaN interface, a
2DHG can be accuInulated if the valence band is raised close enough
towards the Ferrni level. This is achieved here by applying a weak
acceptor-type doping with Mg in the uppermost 20 nm GaN. A
concentration of about 1 X 10
16
cm-
3
ionized acceptors is sufficient
to compensate for the typical n-type background doping in
MOVPE-grown GaN. Further, a highly doped GaN:Mg++ layer on
top is grown to facilitate ohmic contact formation. The doping levels
are equal for all samples. It is shown that by changing of the
GaN/ AlInGaN heterostructure, achieved by different AlInGaN
compositions, the 2DHG density can be adjusted between very high
values of 2.03 X 10
13
cln-
2
and low values of 6 X 1011 cln-
2
Record
maximum mobilities for holes in GaN above 40 cm
2
/Vs (median 30
cm
2
/Vs) are observed for a moderate 2DHG density of 2.2 X 10'2
cm-2. Field effect transistors with 1 11m gate length were fabricated
on these heterostructures. While samples with larger show
depletion mode characteristics, the threshold voltage can be shifted to
negative values for samples with low resulting in enhancement
Inode behavior. This shift proves that a polarization-induced 2DHG is
the conductive path in this heterostructure. While samples with large
show maximum absolute drain currents in the range of 10-
2
A/mm, maximum drain currents are reduced for decreasing With
a siInultaneous reduction in off-state current, still large on/off ratios
up to 8 orders of Inagnitude are achieved for the enhancelnent Inode
devices, demonstrating the great potential for low-power applications.
9:00 AM D4.03
High In-Content InGaN/GaN Junctions Grown by
Plasma-Assisted MBE for Photovoltaic Applications.
Sirona Valdue:z;a-Feli p 1, Marie Pierre Chauvat
2
, Louis Grenet
3
, Yi
Wang
2
, Pierre Ruterana
2
and Eva Monroy'; 'INAC/SP2M/NPSC,
CEA-Grenoble, Grenoble, France; 2CNRS-ENSICAEN-CEA-UCBN,
CIMAP, Caen, France; 3LITEN, CEA-Grenoble, Grenoble, France.
In this work, we report our latest developments on high-In-content
InGaN/GaN junctions grown by plasma-assisted molecular beam
epitaxy (MBE) for photovoltaic applications. The junctions are grown
on various substrates: (a) directly on Si(l11) using a conductive
nanowire-like (3D) InGaN buffer layer, (b) on Ga-polar
GaN-on-sapphire templates, and (c) on strained-engineered Ga-polar
GaN-on-Si(111) templates, which include thick A1N layers in the
buffer structure. Smooth InGaN films (rms below 6 nm) with peak
photoluminescence (PL) emission in the range of 445-670 nm
(corresponding to 16-42% of In Inole fraction) are synthesized on the
different substrates by changing the growth temperature
In particular, Ino.35Gao.65N layers with PL emission
peaking at 595 nm show comparable FWHM nm) grown on both
(a) and (b) substrates. Planar InGaN films grown directly on (a)
substrates display hOInogeneous N polarity as verified by translnission
electron microscopy (TEM) and chemical etching by KOH. Nitrogen
polarity is desirable in solar cell designs containing In-rich
nanostructures in the active region. It prevents the potential barrier
that appears at the n - i interface due to the polarization
discontinuity, and improves the carrier collection. Increasing the In
composition from 26 to 42% leads to a higher density of stacking
faults in the InGaN layers, which are partially relaxed on GaN, as
determined by TEM and x-ray diffraction. Absorption experiments
carried out in Ino.35Gao.65N on visible-transparent substrates (b)
point out an absorption band edge at rv525 nm with an Urbach tail of
0.1 eV, leading to a Stokes shift of Moreover, an absorption
tail at longer wavelengths (0.7-1 11m) is observed, probably related to
defects or Mg levels within the band gap. Starting from n-InxGa'_.TN
layers, we delnonstrate the synthesis of both N- and Ga-polar
complete InGaN/GaN p - n junctions on the three substrates, where
p-type Mg-doped GaN is grown under Ga-rich conditions and at low
temperature to prevent the InGaN decomposition. First
n-Ino.35Gao.65N/p-GaN solar cells prototypes have been fabricated
on (b) substrates. The contacts consisted of a seInitransparent
oxidi7,ed-Ni/ Au layer with a Ni/ Au grid (p-side) and Ti/ Al/Ni/ Au
(n-side). The grid spacing was 150 11m, optimized by taking into
account the diffusion length of the minority carriers in the p-region.
Photovoltaic devices show rectifying current density vs voltage
behaviour in the dark and under non-standardized illuInination. The
7,ero bias photoresponse of the thick nm) InGaN devices is
red-shifted to nm (2.47 eV) indicating the photocurrent
contribution of the InGaN layer, as correlated to the measured
absorption edge. In the case of thin InGaN layers (rv230 Inn), no
redshift is observed. However these devices show a spectral response
in the 700 to 1000 nm wavelength range, consistent with the
previously observed absorption tail.
9:15 AM D4.04
Beyond Intervalley Transfer: Damped Bloch Oscillation and
Negative Differential Drift Velocity at Very High Fields in
Wide Bandgap III-Nitride Materials. Douglas Yoder' and
Sriraaman Sridharan
2
; 1Georgia Tech, Atlanta, Georgia; 2Global
Foundries, Milpitas, California.
We present evidence for a new mode of charge transport at very high
fields in gallium nitride (GaN) and other wide bandgap materials. In
conventional semiconductor materials, the collective (drift) velocity of
an enseInble of electrons is sInall cOlnpared to the randolnly-oriented
therrnal velocity of individual electrons, even at the highest attainable
electric field strengths, except in the most extreme spatially non-local
and temporally non-stationary situations. Even then, electrons may
experience true quasi-ballistic motion only for a short time and over a
265
short distance due to rapid energy and momentum relaxation through
interactions with various scattering mechanisms. Were it possible for a
sustained electric field to act on electrons with strength sufficient for
the rate of momentum and energy gain to substantially exceed the
loss, Bragg scattering at the Brillouin zone boundaries would
eventually reverse the velocities and trajectories of electrons, resulting
in a lowering of the drift velocity of the ensemble. It is straightforward
to dernonstrate the challenges of reaching this lirnit in any statistically
significant way in the more common semiconductor materials, such as
silicon and GaAs. With static dielectric breakdown field strengths in
excess of 3 megavolts per centimeter, GaN and the related alloys can
sustain electric fields large enough that the tirne required for an
electron to traverse the Brillouin zone can approach and even fall
below the characteristic scattering time for hot electrons. In this limit
of very high electric field strength, we find that charge transport is
characterbed by Bloch oscillation damped by momentum-randomizing
collisions, and that, except on short tirne scales, the relative phases of
electrons in the ensemble are uncorrelated. Moreover, it is the
damping itself that is responsible for a finite ensemble drift velocity
superimposed upon the oscillatory trajectories of individual electrons.
In this presentation, we introduce an original theory based on entirely
new solutions of the Boltzrnann transport equation to describe the
phenomenon of damped Bloch oscillation. We also identify the ratio of
the characteristic scattering time to the minimum time required for
electrons to traverse the Brillouin zone (evaluated at the static
breakdown field strength) as a material-dependent figure of merit for
darnped Bloch oscillation, and dernonstrate its relationship to the
damping present in our theoretical formulation. We further show that
in the regime of damped Bloch oscillation, electron drift velocity is a
monotonically decreasing function of electric field strength, giving rise
to an intrinsic negative differential drift velocity - entirely unrelated
to the (phonon-rnediated) process of intervalley transfer - which
holds exciting potential for the of room-temperature
millimeter-wave and terahertz sources. Analytic results are
corroborated for GaN with full-band ensemble Monte Carlo
sirnulation.
9:30 AM D4.05
Record High Current Density (776 kA/cm2) InGaN/GaN
Resonant Tunneling Diodes Using Polarization Induced
Barriers. Tyler A. Growden, Sriram Krishnamoorthy, Siddharth
Rajan and Paul Berger; Electrical and Computer Engineering, The
Ohio State University, Columbus, Ohio.
In this work, we report on polarization-engineered InGaN/GaN RTDs
with room temperature negative differential resistance (NDR) and
record peak tunneling current density of 776 kA/crn2 dernonstrated
across the sample on numerous 4 J.tm diameter devices. Our designs
use resonant tunneling barriers formed due to polarization dipoles in
addition to heterostructure band offsets. RTDs in III-nitrides typically
utilize GaN/ Al(Ga)N/GaN heterostructures with AIGaN barriers.
However, achieving high current density with repeatability and no
hysteresis has been a challenge. induced trapping often
manifests with a false NDR, tunneling into traps, which shows
hysteresis and erratic 1-V's under successive sweeps. Recent work on
unipolar GaN/ AIGaN transport indicates percolation pathways in
AIGaN barriers, which could possibly explain the "transparent"
nature of the ternary AlGaN barrier [D. N. Nath et aI,
http://arxiv.org/abs/1302.3942]. Here we show that using polarization
engineered electrostatic barriers to overcome percolation effects can
provide a pathway to repeatable roorn-ternperature RTDs. The
epitaxial layers were grown via plasma assisted MBE on Ga-polar GaN
(TDD 107 cm-2). The structure consisted of a 200 nm n-type GaN
buffer layer followed by the In(0.03)GaN/ln(0.25)GaN/ln(0.05)GaN/
In(0.2)GaN/GaN (2.5/3.5/2.5/3.5/2.5 nm) active region, and 100 nm
n-GaN contact layer. This stack allows for a srnaller, low cornposition,
InGaN first barrier with a slightly larger GaN second barrier.
Ti/ Au metal stacks were used for top and bottom contacts. Circular
mesas with diameter between 1-100 J.tm were fabricated, with crescent
shaped bottorn contacts for enhanced accuracy and better current
extraction. A specific contact resistivity of 3x10
2
5 O-cm2 was
extracted using TLM test structures. NDR was observed at room
temperature only in the smallest measured devices (diameter 4 !Lm).
The onset of the NDR was consistently observed at V during the
forward sweep. The value of the PVCR was consistently found to be
around 1.1. The peak current density ranged between 501-776 kA/cm2
on all devices where NDR was observed. The NDR was usually visible
for 5 sweeps at which point the device would break down. We believe
that this is due to the high currents and high contact resistance.
Future work will include an intensive study on the effects of varying
the indium concentration in the wells. Additionally, we will be looking
at how these devices behave at low temperatures. Our results on
polarization engineering to achieve the highest current density nitride
based tunneling devices with NDR suggest that alloy fluctuations are
critical for unipolar vertical devices, and could enable various devices
for optical and THz applications. Supported by ONR MURI project
for III-Nitride Terahertz Electronics, program manager: Paul Maki
9:45 AM D4.06
Interface Analysis and Modeling of Normally-Off GaN
MISFETs with an Etch-Stop-Barrier Structure. Bin Lu, Min
Sun and Tomas Palacios; MIT, Cambridge, Massachusetts.
Recently, we have developed an etch-stop barrier structure, consisting
of an n-GaN donor layer, an etch-stop AIN layer and a thin
AlO.15GaO.85N barrier, which greatly improves the gate-recess
uniformity and effective channel mobility in normally-off MISFETs
[1]. This paper provides a detailed analysis of the capacitance-voltage
(CV) characteristics of these devices through experirnents and
sirnulations using the device sirnulator Nextnan03. By rnatching the
simulated CV characteristics with the measured CV curves, the gate
dielectric interface trap density was extracted with a peak density as
low as 3.4xl011cm-2eV-l at around 2.2 eV below the conduction
band edge of Al203 gate dielectric. This low interface trap density
results in a steep subthreshold swing of 621 m V / dec with less than
10 m V hysteresis in the transfer characteristics of these normally-off
MISFETs. From the simulation of the spatial distribution of the
two-dimensional-electron-gas (2DEG) as a function of gate bias
voltage (Vgs), it is found that for Vgs > 1.5 V channel electrons
overcome the AIGaN barrier where they experience interface
roughness scattering and alloy scattering. As a result, effective
electron mobility decreases with increasing gate voltages.
Furthermore, the measured Hall electron density tracks closely with
the sirnulated electron density in the GaN channel layer which
confirms the assumption that the Hall measurement does not probe
the electrons injected into the AlGaN layer [1], which results in higher
Hall mobility values than the effective mobility extracted from the CV
measurement. For Vgs <:: 1.5 V with >90% of 2DEG in the GaN
channel, the Hall rnobility is about 1.2 tirnes of the effective rnobility
at Vgs = 1.5 V, which could be due to the Hall scattering factor
estimated to be around 1.2 in reference [2]. The simulation also
reports a positive compensation charge located at the A1203/ AIN
interface which plays a rnajor role in affecting the device threshold
voltage. The refined device rnodel presented in this work provides a
good foundation for quantitative studies of GaN-based devices.
Acknowledgements - This work was supported by the Advanced
Research Projects Agency - Energy ADEPT and GIGA projects of
the U.S. Department of Energy and by the Office of Naval Research.
References [1] B. Lu et aI., IEEE Electron Device Lett., 34, 369
(2013). [2] A. Asgari et aI., J. Appl. Phys., 110, 113713 (2011).
10:30 AM *D4.07
Novel Device Concepts in GaN Electronics. Urnesh K. Mishra,
Electrical and Computer Engineering Department, University of
California-Santa Barbara, Santa Barbara, California.
During the past years, GaN based transistors have entered commercial
rnarkets for high power and high frequency applications, and GaN
based power switching devices outperform traditional counterparts.
The vast majority of these devices are based on (Ga,Al)-polar (0001)
(AI,Ga)N heterostructures, for which highly optimized fabrication
procedures have been developed. When striving for operation
frequencies beyond Ka-band, however, the perforrnance of existing
devices rapidly degrades, requiring a re-design of the device
structures. Attractive for very high frequency operation are in
particular devices based on N-polar (AI,Ga,In)N grown on (000-1)
GaN. Due to the opposite direction of the internal electric fields in
N-polar heterostructures, the two dimensional electron gas (2DEG) is
located on top of the (AI,Ga,In) gating layer, which now
simultaneously serves as a back barrier leading to improved electron
confinement. In addition, the 2DEG is contacted via the GaN channel,
which in cornbination with re-grown ohrnic contacts enables extrernely
low contact resistances, and values as low as 23 O-J.tm were
demonstrated. Also advantageous in N-polar device structures is the
flexibility in channel scaling required for devices with very short gate
length. Recent advances in the design of N-polar
GaN/(Al,Ga,In)N/GaN high electron mobility transistors allowed the
demonstration of devices with 1.89 S/mm extrinsic transconductance,
4 A/mm drain current density, and 0.23 l2-mm on-resistance for
N-polar GaN MIS-HEMTs with a 5.4-nm GaN channel and a novel
InAlN/ AIGaN back barrier grown by MOCVD on a vicinal sapphire
substrate. Additionally, an fT of 204 GHz using a 70-nm T-gate (14.3
GHz*!Lm fT*L9 product) and an fmax of 405 GHz using a 90-nm
T -gate were obtained. Another example for an alternate transistor
approach is the GaN based Hot Electron Transistor (HET), which
operates by the injection of electrons over a first barrier (ernitter) into
a thin transient region (base) before getting collected over a second
barrier (collector). The ballistic carrier transport in these devices
potentially allows for extremely high operation frequencies. While
originally demonstrated in traditional compound semiconductors,
group-III nitrides are particularly attractive for HET applications due
to the large band off-sets and the strong internal electrical fields in
(0001) and (000-1) (AI,Ga,In)N hetero-structures. III-Nitrides also
have a large inter-valley separation (calculated to be 1.3-2.0 eV for
266
GaN), thus, higher injection energies can be used before the onset of
inter-valley scattering. III-N HETs have been demonstrated recently
in both Ga- and N-Polar configurations. The rnC3n free path of
electrons in GaN as a function of energy was estimated using the RET
as a spectroscopic tool, rising from 9 to 38 nrn when the injection
energy was increased from 0.3 to 1.8 eV. The HET device
characteristics will be discussed in detail at the conference.
11:00 AM D4.08
Thermally Robust RuOx Schottky Diode on III-Nitrides. Lwin
Min Kyaw,,2, Aju A. Saju', Yi Liu', Milan K. Bera', Sarab P.
Singh
1
, Sudhiranjan Tripathy 2 and Eng Fong CharI; lElcctrical and
Computer Engineering, National University of Singapore, Singapore
119260, Singapore, Singapore; 2 Analysis & Characterisation, Institute
of Materials Research and Engineering, A 'STAR, Singapore 117602,
Singapore, Singapore.
InAlN/ GaN heterostructure based devices have gained much interest
in high speed and high power applications owing to its wide bandgap,
high two dimension electron gas (2DEG) density and good thermal
stability. However, InAlN/GaN based Schottky diodes and high
electron Inability transistors (HEMTs) llsing traditional Nil Au
Schottky contact suffer from high reverse leakage current when
annealed above 600 DC. This leakage current limits the flexibility of
HEMT fabrication processes. As a consequence, only gate last process
can be used to fabricate HEMTs where the gate Inetallization is
perforrned after high ternperature annealing to forIlI ohrnic contact.
Therefore, we aim to develop a thermally more robust Schottky
contact. In this paper, we report investigations on RuOx Schottky
diode on III-nitrides and demonstrate that RuOx Schottky contact is
not only therrnally rnore robust than Nil Au contact, but also has a
much lower reverse leakage current and higher Schottky barrier height
(SBH). The substrates used were 4-inch n-GaN on Si (111) with a
carrier concentration of 5.57x10'7 cm-
3
and InAIN/GaN on Si (111)
with a sheet resistance of 513 O/sq purchased from NTT Corporation.
The ohmic and schottky contacts used for the Schottky diodes are
Ti/ Al/Ni/W and RuO.T (100 nm) respectively. Ni/ Au (30/80 nm)
Schottky diode on InAINI GaN heterostructure was also fabricated as
a reference for comparison. RuO
x
Schottky diodes on n-GaN/Si(l11)
substrate were annealed in N
2
and vacuum from 400 to 800C. When
annealed in vacuum, the reverse leakage current of RuOx diode
increases with increasing temperature. On the other hand, with N 2
annealing, the leakage rernains as low as that with no heat treatrnent,
which is s:: 10-
4
Acm-2. In addition, SBH of RuO
x
diode increases
with annealing temperature up to 700 DC when annealed in N
2
.
Hence, N 2 is the preferred annealing ambient for RuOx Schottky
contacts. RuOx and Ni/Au Schottky diodes on InAIN/GaN/Si(111)
substrate were then annealed in N
2
frorn 400 to 800 GC. The reverse
leakage current of Nil Au diode increases with annealing temperature
above 600 DC while that of RuO
x
diode decreases with increasing
annealing temperature. When annealed at 800 GC for 1 minute in N
2
,
the reverse leakage current and of RuO
x
Schottky diode at -40 V is
low at Acm-
2
, while that of Ni/Au Schottky diode has
increased to 10-
1
ACln-
2
. The corresponding effective STIH of RuO
x
contact is 1.27 eV, which is rnuch higher than that of Nil Au contact
at 0.86 eV. In conclusion, RuO
x
Schottky contact is thermally more
robust than Nil Au contact, with a reverse leakage current remaining
low at rv10-
5
Acm-
2
after annealing in N
2
at 800 GC, which is much
lower than that of Ni/ Au contact (by 10
4
times). It also has a higher
SBH (by than Ni/Au contact. This enables the flexibility of
device processing and the possibility to fabricate HEMT using
self-aligned gate-first process. Furtherrnore, RuO
x
contact is
Si-technology compatible.
11:15 AM D4.09
High Conductivity in Si-Doped GaN Wires.
Pierre Tchoulfian
1
,2, Fabrice Donatini
2
, Francois Levy1, Benoit
Amstatt', Pierre Ferret' and Julien Pernot
2
,3; 'CEA-LETI, Grenoble,
France; 2Institut Neel, CNRS and Dniversite Joseph Fourier,
Grenoble, France; 3Institut Dniversitaire de France, Paris, France.
As in planar epitaxial case, a large carrier concentration is required in
wire- based devices to decrease series resistance and to improve current
injection schemes into the wires. Consequently, control of doping and
understanding of electrical conduction are also essential to realize high
performance wire-based devices. In this work, temperature-dependent
resistivity measurements have been performed on single Si-doped GaN
microwires grown by catalyst-free metal-organic vapour phase epitaxy
[1]. A specific e-beam lithography setup has been used to connect
nurnerous single rnicrowires in a single step electron bealn lithography
using CL mapping. Low temperature cathodoluminescence (CL)
reveals an asymmetric and broad near-band edge emission peaking at
3.57 eV with a full width at half maximum of 170 meV, in agreement
with band-filling effect due to a high electron concentration (10
20
crn-3). Metal-like conduction is observed froln four-probe
measurements without any temperature dependence between 10K and
300 K, indicating a carrier concentration well above the metal-non
metal transition in GaN (N_MNM=1.6x10'8 cm-3). The resistivity
measurements yield resistivity values as low as 0.37 mn.cm. The
resistivity is found to be independent on the radius revealing that
surface-related effects on conduction are negligible. In order to explain
this unique conductivity behavior, it is necessary to estimate
separately the carrier concentration and the mobility whose effects are
combined in resistivity measurements. Coupled
resistivity-therrnoelectric rneasurelnents were thus perforrned on the
same region of single Si-doped GaN wires, resulting in the direct
probing of high carrier concentrations (>10
2o
cm_3). Additionally, a
similar carrier concentration was inferred using the lower branch of
the phonon-plasrnon coupling of rnicro-Rarnan experirnents on single
wires. As a conclusion, a set of optical and electrical characterization
techniques has been used to infer the doping properties of Si-doped
GaN wires. All techniques give similar doping properties suggesting a
higher dopant incorporation during wire growth as compared to
conventional epitaxial planar case to explain the unique conductivity
behavior.
11:30 AM D4.10
Novel Nitride Photoelectrode Based on Polarization
Engineering for Water Splitting. Akihiro Nakalnura
1
, Katsushi
Fujii
2
Masaka7,u Sugiyama' and Yoshiaki Nakano' 'School of
The of Tokyo, Tokyo, 2Global Solar+
Initiative, The University of Tokyo, Tokyo, Japan.
Hydrogen generation by photoelectrochemical (PEC) water splitting
is an attractive approach to storage the solar energy. GaN is
chemically stable and can split water under ultraviolet illumination
without an external bias. In addition, InGaN has the band gap in a
wide range covering the visible light region. Therefore, III-Nitride
semiconductors are promising materials as a photoelectrode. In the
PEC reaction, n-type GaN is usually used due to its high crystal
quality. However, the electrode stability is not enough because it
works as a photoanode, i.e., a lot of holes exist at the surface and
oxidize not only water but also GaN itself. A p-type GaN works as a
photocathode, thus, few holes exist at its surface. The p-type GaN is,
therefore, better in durability than an n-type one. However, a p-type
GaN suffers from high resistivity due to the deep Mg acceptor level,
which results in the Inuch poor I-V properties cornpared to that of the
n-type. In this report, we propose a novel structure for the nitride
photocathode which consists of only n-type materials. The samples
were grown by metal organic vapor phase epitaxy (MOVPE) on
(0001) sapphires. A 1.4 pm n-type GaN conducting layer with a
carrier concentration of 2 X 10
18
cm-3 was grown on the undoped GaN
buffer layer, followed by a few-nm thick undoped AlN layer, and an
undoped GaN light absorption layer of about 140 nrn thick. The
measurements were performed in 0.5 M H
2
S0
4
solution with a
platinum counter electrode, an Ag/ AgCI/NaCI reference electrode and
a Xe lamp. A considerably large electric field generated by the
polarbation charges at the both sides of the AlN layer forms a tunnel
junction between the undoped GaN and the n-type GaN. The bias
caused in the AIN layer depletes the entire undoped GaN layer. The
direction of the electric field in the undoped GaN layer is opposite
from that of a normal bulk n-type semiconductor. This polarization
engineered structure is expected to work as a photocathode. The I-V
rneasurelnents were perforrned under different light intensities. The
novel structure without illumination showed a typical diode-like I-V
characteristic of an n-type GaN except for the more negative
threshold voltage. When the light was irradiated, a cathodic current
was clearly observed at the voltage where no current was observed in
the dark condition. Since the density of the cathodic current increased
with the light intensity, the novel structure works as a photocathode.
Time dependences of the photocurrent density with some external
biases for the novel structure and the n-type GaN were measured for
200 Ininutes. Although the n-type GaN showed a higher anodic
photocurrent density at the beginning, rapid degradation of the
photocurrent was observed. On the other hand, the cathodic
photocurrent of the novel structure kept almost constant during the
200 minutes measurement. The lifetime of the novel structure is much
longer than the n-type GaN photoclectrode as we expected.
11:45 AM D4.11
p-Channel GaN/ AlinGaN Heterostructure Field Effect
Transistor Operation at Elevated Temperatures. Herwig Hahn,
nen Reuters, Alexander Pooth, Holger Kalisch and Andrei Vescan;
GaN Device Technology, RWTH Aachen University, Aachen, Germany.
The focus of nitride-based device research has been laid on n-channel
devices. Outstanding performance has been achieved for these devices
which use a two-dirnensional electron gas (2DEG) for current
transport. Low-power logic applications are currently limited to
direct-coupled logic as for this type, well performing n-channel
enhancement and depletion mode transistors are accessible. However,
with the introduction of p-channel devices in which the current
transport occurs rnainly due to a two-dirnensional hole gas (2DHG),
nitride-based complementary logic becomes possible. With GaN
267
having a high bandgap of 3.4 eV, also complementary logic operation
at high temperatures might be a possible application. So far,
p-channel devices have been reported sparsely. Additionally, up to
now, no investigations at elevated temperature have been carried out.
Thus, in this contribution, p-channel heterostructure field effect
transistors (HFETs) have been fabricated and characterised up to 175
DC. The layer stack was grown by MOVPE. On top of 300 nm AIN
and 2 rLIn GaN, a 35 HIll thick AlInGaN backbarrier and a top GaN
channel layer is grown. For the top GaN, the doping level of Mg is
step-wise increased, to achieve both, high hole mobility (no doping at
the AlInGaN/GaN interface) and well-performing ohmic contacts
(very high doping level in the uppcrrnost CaN). Device processing
included rncsa isolation and ohrnic and gate contact furrnation by
Ni/Au and Mo/ Au metal stacks, respectively. Room-temperature I-V
measurements show well-performing p-channel devices with on
currents in the range of several mA/mm (at V ds = -10 V). By
reducing -Vds-, both on-state and off-state currents arc decreased.
At V ds = -0.1 V, an on/off ratio of nearly 108 is realised, while the
subthreshold swing (SS) is as low as 72 mVIdee. Increasing operation
temperature up to 175 0 C, we observe a systematic decrease of the
on/off ratio while the SS is increasing continuously. Looking closer at
the tClnpcratllrc dependence of the SS, we see that it incrcases as
predicted by theory almost linearly up to 125 DC, at which it reaches
90 mV/dec. At this temperature, the on/off ratio is still impressively
high at 6x10
6
, demonstrating proper device functionality. At higher
temperatures (175 DC), we observe a significantly increased leakage
current. Conscquently, on/off ratio is also degraded. Still, reasonablc
device functionality is observed, which would be sufficient for the
device to be used in complementary logic. The decrease in on-current
with elevated operation temperature can be explained by a reduced
hole mobility within the channel. The constant pinch-off voltage over
the entirc ternperaturc range indicates a constant shect chargc (Ps).
This also confirms that current flow is dominated by 2DHG
conduction. The gate leakage current increases with temperature.
Thermionic emission is certainly increasing here. Additional effects,
such as a tcrnperature-dcpcndent Schottky barricr height or defect
activation, are still to be investigated.
12:00 PM D4.12
GaN/ AIN Double Barrier N anowire Resonant Tunneling
Schottky Diodes with Extremely High Peak Valley Current
Ratio. Ye Shao
l
, A.T.M. G. Sarwar
2
, Santino D. Carnevale
2
,
Roberto C. Myers
l
,2 and Wu Lu
l
,3; IDepartment of Electrical and
Computer Engineering, The Ohio State University, Columbus, Ohio;
2Departrnent of Materials Scicnce and Engincering, The Ohio State
University, Columbus, Ohio; 3Department of Nanobio Materials and
Electronics, Gwangju Institute of Science and Technology, Gwangju,
Korea, Republic of.
Resonant tunneling devices (RTDs) have attracted rnany intercsts
because of their extremely high switching speeds and potential
applications in multi-logic circuits. Recently, III-nitride nanowires
(NWs) have emerged as an alternative choice because the large
surface-to-volume ratio and small cross sections allows NWs
accornrnodate rnuch higher lattice rnisrnatch with an efficient elastic
strain relaxation thereby inhibiting the formation of dislocations that
are often found during the epitaxial growth of IIl-N thin film
structures. Previously we have demonstrated GaN/ AIN double barrier
RTDs with a maximum peak to valley current ratio of 5.09
and a rnaxirnurn rcsonant peak currcnt density of 10 A/crn
2
. Herc we
show that PVCR can be further enhanced using a Ni/ Au Schottky
metal contact at one end of the nanowire RTD. The Schottky barrier
suppresses the thermionic emission current before the onset voltage of
NDR to capture thc currcnt resulting fronl resonant tunneling. As a
result, an extrcrncly high PVCR of 41 is dernonstrated. To our bcst
knowledge, this is the highest PVCR value so far reported in
AIN/GaN RTDs.
12:15 PM D4.13
Electrical Characterization of MoS2/GaN Heterojunctions
Edwin W. Lee
1
, Masihhur R. Laskar
1
, Lu Ma
2
, Sriram
Krishnamoothyl, Digbijoy N. Nath
l
, Pil Sung Park
l
, Yiying Wu
2
,
Siddharth Rajan1; 1Departrnent of Electrical and Cornputcr
Engineering, The Ohio State University, Columbus, Ohio;
2Department of Chemistry and Biochemistry, The Ohio State
University, Columbus, Ohio.
Transition rnetal dichalcogcnides (TMDCs) havc garnered increased
attention as materials analogous to graphene in their 2D structure but
exhibiting non-zero band gaps. Molybdenum disulfide (MoS2) is a
layered semiconductor with band gaps ranging from 1.2 eV for bulk
material to 1.8 eV for monlayer. It exhibits relatively high mobility
and is an optically active rnaterial. The closc lattice rnatch betwcen
MoS2 and GaN (0.9%) facilitates the exploration of new class of
semiconductor devices based on heterostructures formed between 2D
and 3D materials. We report on the first chemical vapor deposition
(CVD) growth of single crystal (0002)-oriented MoS2 on GaN and the
initial characterization of the heterojunction formed by MoS2 and
GaN. This growth is based on previously reported large area MoS2 on
sapphire.1 I3y increasing thc CVD-growth ternpcrature of MoS2 fronl
500 C to 800
0
C, we improve the MoS2 structure from polycrystalline
to single crystal. This is verified by X-ray diffraction spectroscopy.
Clear peaks in Raman spectra verify the presence of large-area MoS2.
We utilbe current-voltage (IV) and capacitance-voltage (CV)
characteristics to gain insight into transport between MoS2 and GaN
and their interfacial properties. Our results show that
micromechanically exfoliated MoS2 obtained from bulk geological
samples, unintentionally doped CVD-grown MoS2 (grown at both
500C and 800
D
C), and Nb-doped, p-type MoS2 produce rectifying
hcterojunctions with GaN. Furtherrnore, unitcntionally doped and
micromechnically exfoliated heterojunctions exhibit this
rectifying behavior with similar current magnitude and approximately
1000:1 ratios between forward and reverse bias current. CV
rncasurernents perforrned on high ternperature MoS2/GaN show
negligible hysteresis present in the forward and reverse sweep. This
indicates the presence of a high quality heterointerface with low
interface state density. The doping profile extracted from the CV
measurement suggests depletion in the GaN and gives some
prclirninary suggestion of a typc I band line up bctween MoS---,2 and
GaN. This first report on heterojunctions between 2D layered
materials could lead to enhanced functionality and performance of
Ill-nitrides. E.L. and S.R. acknowledge funding from NSF NSEC
(CANPD) program (EEC0914790) and NSF ECCS Grant
ECCS-0925529.
SESSION DP3: Poster Session: Electrical Devices
Wednesday Afternoon, August 28, 2013
1:00 PM
Potomac C/D & 1-6
DP3.01
MOVPE and Characteristics of AI(In)N/AIN/GaN HEMTs
on Si(lll) and Si(OOl). Jonas Hennig, Armin Dadgar, Oliver
Krurnrn, Hartrnut Wittc, Andreas Lesnik, Juergcn I3laesing and Alois
Krost; Institute of Experimental Physics,
Otto-von-Guericke-University, Magdeburg, Saxony-Anhalt, Germany.
AlInN/GaN HEMTs are nowadays in the focus of high power
applications, because of thcir excellent properties like high carricr
concentration, high electron mobility, and high breakdown field
strength. Benefits of growing these structures on silicon substrates are
a good thermal management as well as possible compatibility to
CMOS technology in the case of Si(001). Furthermore, silicon reduces
dcvice cost by the availability of largc diarnetcr wafer. Wc have grown
AlInN/AIN/GaN HEMTs on Si(l11) and Si(001) by MOVPE and will
present a comparative study of the growth process and the
performance of the processed devices. In-situ growth monitoring was
used for optimizing the process parameters. In order to get crack free
sarnples, strcss rnanagernent is essential when growing GaN on Si,
especially on Si(OOl). X-ray e/2e-scans as well as GaN(0002) w-scans
and grazing incidence (GilD) GaN(lOIO) w-scans were performed on
the grown structures. Furthermore, grazing incidence X-ray
fluoresccnce (GIXRF) was used to analyze thc thickncss and Indiurn
content of thc AIN spacer and thc AllnN barrier. The influcnce of the
substrate and the AIN spacer as well as the AlInN layer on the
performance of HEMT devices will be discussed. C-V and Hall-effect
measurements in van der Pauw geometry were performed on the FET
structures undcr consideration of a cornplex equivalcnt circuit and thc
real contact geometry, respectively. For the structure grown on Si(OOl)
we achieve a shcet carrier concentration of n = 2.7x10-
13
crn-
2
, an
electron mobility I" = 521 cm
2
/Vs, and sheet resistivity Rs=
4410/sq. For Si(l11): n = 2 x10-
13
crn-2 , I' = 1200 crn
2
/Vs, Rs
2300jsq. The irnpact of the proccssing pararncters on the device
performance like mesa etching with Cl/ Ar chemistry and Ohmic
contact formation will be discussed as well. The HEMTs show a low
threshold voltage of around -2V up to -2.5V which makes it easier to
achieve cnhancernent rnode operation via a gate recess. Latest results
on enhancement mode operation of the devices will be reported.
DP3.02
Electrical Transport Behavior at the InNtGaN
Heterostructures Interface. I3asanta Roul
l
, , Mahesh Kurnar
1
,3,
Mohana K. Rajpalke
l
, Thirumaleshwara N. Bhat
l
and
S. B. Krupanidhi I; I Materials Research Centre, Indian Institute of
Science, Bangalore, Karnataka, India; 2Central Research Laboratory,
Bharat Electronics Limited, Bangalore, Karnataka, India; 3Centre of
Excellence in Information and Communication Technology, Indian
Institute of Technology, Jodhpur, Rajasthan, India.
In the last few years, InN and GaN have attracted considerable
attention because of their applications such as high efficient
solar-cells, light ernitting diodes, ficld effect transistors, high spced,
and high frequency electronics deviccs, etc. Due to the enorrnous effort
268
put into improving the quality of InN epitaxial layers, heterostructure
based devices have taken on much importance in semiconductor
research cornrnunitics. The interfaces of the heterostructure arc
important parts in the electronic and optoelectronic devices. One of
the most interesting features of the interface is its Schottky barrier
height (SBH), which is a measure of the mismatch of the energy levels
for the majority carriers across the interface. The performances of the
heterostructure based devices arc strongly dependent on the
homogeneity of the interfaces. In this report, we fabricated InN/GaN
Schottky junctions and extensively studied the temperature dependent
electrical transport behavior. The Schottky barrier height (SBH) and
the ideality factor were found to be tcrnpcraturc dependent. The
tcrnpcraturc dependence of the barrier height indicates that the STIR
is inhomogeneous in nature at the heterostructure interface. The
higher value of the ideality factor and its temperature dependence
suggest that the current transport is primarily dominated by
thcrrnionic field crnission (TFE) other than thcrrnionic clnission (TE).
DP3.03
Molecular Beam Epitaxial Growth of Nonpolar A-Plane InN
/ GaN Schottky Heterojunction. Mohana K. Rajpalke
1
,
Thirurnaleshwara N. Bhat
1
, Basanta RouI
1
,2, Mahesh Kurnar
1
,3 and
S. B. Krupanidhi 1; IMaterials Research Centre, Indian Institute of
Science Bangalore Karnataka India 2Central Research Laboratory
Bharat 'Electronics' Limited, Karnataka, India; 3Centre
Excellence in Information and Communication Technology, Indian
Institute of Technology, Jodhpur, Rajasthan, India.
Nonpolar a-plane InN films were grown on r-plane sapphire substrate
by plasma assisted molecular beam epitaxy with GaN underlayer. The
growth of nonpolar a- plane orientation was confirmed by high
resolution x-ray diffraction study. The RHEED patterns show the
weak streaky lines for a-plane GaN confirrns the reasonable srnooth
surface. Spotty nature of a-plane InN RHEED pattern indicating the
3D growth of nonpolar a-plane InN. The temperature dependent
current transport properties of nonpolar a-plane InN/GaN
heterostructure Schottky junction were investigated. The barrier
height (1Jb) and ideally factor (TI) estimated from the thermionic
emission model were found to be temperature dependent in nature.
The conventional Richardson plot of the In (Is / T2) versus l/kT has
two regions: the first region (150 - 300 K) and the second region (350
- 500 K). The values of Richardson constant (A*) obtained from this
plot are found to be lower than the theoretical value of n-type GaN.
The variation in the barrier heights was explained by a double
Gaussian distribution with mean barrier height values ( ) of 1.17 and
0.69 eV with standard deviation ( ) of 0.17 and 0.09S V, respectively.
The rnodified Richardson plot in the ternperature range of 350 - 500
K gives the Richardson constant which is close to the theoretical value
of n-type GaN. Hence, the current mechanism is explained by
Thermionic emission (TE) by assuming the Gaussian distribution of
barrier height. At low temperature 150 - 300 K, the absence of
ternperature dependent tunneling pararneters indicates the tunneling
assisted current transport mechanism.
DP3.04
Quantitative Characterization of Interface Traps in
ALD-AI203/AlGaN/GaN MOS-HEMTs by Conductance
Measurelllent Technique. Jiejie Zhu
1
,3, Xueyang Liao
2
,3, Tong
Yue
2
,3 Xiaohua Ma
3
,1 and Yue Ha0
3
,2. lSchool of Technical Physics
Xidian' University, Xi'an, Shaanxi, Chida; 2School of
Xidian University, Xi'an, Shaanxi, China; 3State Key Discipline
Laboratory of Wide Band Gap Serniconductor Technology, Xidian
University, Xi'an, Shaanxi, China.
While AIGaN/GaN HEMTs are attractive candidates for high-power
and high-frequency applications, there remain problems of large
off-leakage currents and current collapse due to the high-density
interface states. MIS-HEMT(or MOS-HEMT) structures have greatly
suppressed off-leakage currents. However, the insulators were almost
grown with ex-situ method, which may introduce some defects in
process. In this paper, the interface states of
ALD-AI203/AIGaN/GaN MOS-HEMTs were characterized
quantitatively. Interface traps can be equivalent to parallelled
capacitor Ctrap and conductor Gtrap, and capacitance RF dispersion
will be caused in C-V test, as Fig.l illustrates. Extraction of Ctrap is
very difficult, while accurate and reliable trap-related information can
be obtained by conductance rneasurernent[1]. While biased at
accumulation region, AIGaN/GaN interface traps levels in the band
gap, shown in Fig.2(a), only AI203/AIGaN interface states respond to
RF signals. Fig.3(a) gives the extracted Gsurf/w in accumulation
region, and when wTsurf=1, Gsurf/w reaches the rnaxirnurn Csurf /2.
Fig.3(b) shows that time constant of A1203/ AIGaN interface states
decreases exponentially from 75.6/"s to 1.34/"s as gate voltage
increases. This is because that Fermi level rises so that AC signal can
detect more faster (and shallower) traps. With 2DEG channel
cornpletely conductive in accurnulation region, the surface Ferrni level
changes nearly linearly with gate voltage, and time constant changes
exponentially with trap level, so it is also index-related to voltage.
The revealed trap levels are between 0.324eV and 0.42geV, indicating
that high-density deep interface states exist at A1203/ AIGaN
interface, partially due to the easy formation of Ga-O bonds[2]. The
traps density of A1203/ AIGaN interface changes slightly in
about two magnitudes smaller than that of
Schottky/ AIGaN interface, which may be due to the low defect
density and high uniforrnity of ALD-AI203. When biased near Vth,
AIGaN/GaN interface states can respond to RF signals, so the traps
information can be obtained after removing the contribution of
A1203/ AIGaN interface states. It is seen from Fig.4(b) that
MOS-HEMT has fast traps with tirne constant srnaller than 1.12/1:s at
AIGaN/GaN interface, while HEMT device test results show that
AIGaN/GaN interface state time constant is between 4.S9/"s and 51/"s.
The interface state density of both devices are in
orders of magnitude, but MOS-HEMT has much less slow(and deep)
interface states, indicating that the oxide layer is effective to reduce
deep level traps. The quasi-continuous trap level is between 0.27SeV
and 0.32eV, and interface states density decreases with level
increasing, indicating that there are more traps closer to Ec, which
may be caused by lattice mismatch. Experimental results show that
conductance rneasurernent rnethod is an effective way to analy and
characterize surface and interface states in semiconductor device.
DP3.05
Intrinsic Ferrolllagnetic Sellliconductor Rare-Earth Nitrides;
Magnetic Properties of FET Structures and Superlattices. Joe
Trodahl, Eva Anton, Franck Natali, Harry Warring, James McNulty
and Ben Ruck; MacDiarmid Institute for Advanced Materials and
Nanotechnology, Wellington, New Zealand.
In the recent years, GaN doped with rnagnetic irnpurities has been
investigated for use in spintronic applications to extend device
functionality of the group-III nitride family. In particular, transition
metal and rare earth-doped GaN have shown suggestions of room
ternperature ferrornagnetic behavior. However, although there has
been progress over the last decade, there is still a lack of cornplete
understanding of the ferromagnetic exchange interaction and there
remain severe growth issues such as the segregation of secondary
phases and the generation of defects when increasing the dopant
concentration, both of which are still to be overcorne. Furtherrnore, in
such systems the magnetic dopants act as electronic dopants,
preventing independent control of the carrier concentration and the
magnetism. These problems have motivated a search for intrinsic
ferromagnetic semiconductors. The rare-earth nitrides (RENs) have
prornise of being exactly such rnaterials that can be used to extend
device functionality. Most of the fourteen RENs combine the
properties of the ferromagnet and the semiconductor, an exceedingly
rare combination. We have demonstrated they are epitaxy-compatible
with group III-nitrides, so that with their optical bandgaps ranging
frorn "-'0.7eV to rv1.8eV, a heterojunction involving the two
semiconductors might have very attractive properties for
multi-wavelength. We have recently reported that high quality
heteroepitaxial GdN and SmN films can be grown by molecular beam
epitaxy on GaN or AIN ternplates. Magnetic rneasurernents on thern
reveal strikingly unusual and cornplernentary rnagnetic properties.
Thus, for example, GdN has a large magnetic moment while SmN
orders ferromagnetically with nearly zero magnetic moment.
Furthermore, the GdN-SmN pair has a huge contrast in their coercive
fields, suggesting they can act as the building block of any rnernory
devices. Here, we will present a full overview of the growth and
applications of this exciting new class of nitrides.
DP3.06
Impact of Drain-Induced Barrier Lowering (DIBL) Effect on
Breakdown in AIGaN/GaN Lateral Field-Effect Rectifier.
Wanjun Chen, Qi ZHou and .ling Zhang; University of Electronic
Science and Technology of China (UESTC), Chengdu, Sichuan, China.
In our earlier works, a lateral field-effect rectifier (L-FER) that is
cornpatible with the norrnally-off HEMT structure has been reported
and its high perforrnances such as low turn-on voltage and low
on-resistance have been proven. However, the physical mechanism of
breakdown in L-FER is still ambiguous. At reverse state, a high
electric field occurs at the end of Schottky contact. Thus, this
parasitic fluorine-treated SBD rnay be a potential origin for device
breakdown. There have been large amount of works devoted to
understanding the F-treated SBDs. These results, however, does not
successfully explain the relationships between the reverse currents and
reverse bias voltages in L-FERs. In this work, we propose that the
prirnary factor responsible for breakdown in L-FER is not the
fluorine-treated SBD but rather than the GaN buffer layer. The buffer
leakage current has the similar electrical behavior as a buried N-type
MOS biased at weak inversion region, i.e., the subthreshold region. An
analysis model for subthreshold region transmission is also proposed
and the results are in good agreernent with the experirnental value.
269
DP3.07
Impact of the Surface Modification for the Ga- and N-face
n-GaN Schottky-Type Diodes with Low Reverse-Bias Leakage
Current. Tohru Honda, Tomohiro Yamaguchi, Naoyuki Sakai, Shihei
Fujioka, Ryosuke Amiya and Yohei Sgiura; Graduate School of
Engineering, Kogakuin University, Hachiohji, Tokyo, Japan.
The surface rnodification is attracting luuch attention for the
application to Schottky-type (ST) diodes with a low reverse-bias
leakage (RBL) current. We have already proposed the Al facepack
technique for the surface modification. In the case of Ga-face GaN,
reduction in the RBL current was observed after the surface
Inodificatioll. In this study, Schottky-type diodes were fabricated using
the N-face GaN with the surface modification. The reduction in the
RBL current was also observed from the N-face GaN-based Schottky
diodes. The impact of Ga- and N-face after the surface modification
was also discussed using the ARXPS of these surfaces w / 0 the surface
modification. (000l)2H-GaN layers, whose electron concentration was
3x10l7 cm-3, grown by HVPE were used for the study. The surface
modification was adopted to modify the surfaces of the layers for the
formation of Schottky contacts. First, the layers were cleaned using
buffered hydrogen fluoride (I3HF) to rClnovc their surface oxides.
Next, an Al layer with a thickness of approximately 20 nm was
deposited on the surface. The layers were then annealed in air at
750C and the surface oxides were removed using BHF solution. This
sequence was named the facepack technique. Au electrodes were used
for the Schottky contacts. The diarnctcr of the circular Au electrode
and the window diameter in the ohmic Al electrode were 300 ",m and
1 mm, respectively. In the case of N-face GaN, the reduction of
reverse-bias leakage current in the ST diodes was drastically improved.
This was also observed from that using a Ga-face GaN. The ARXPS
spectra indicated that the 3IIlOllUt of the surface bending was changed
by the surface modification. The band bending depends on the energy
difference between the surface Fermi level and the bulk Fermi level in
the GaN. These details will be presented in the conference.
DP3.08
Evaluation of Radiated Emission of GaN-HEMT Switching
Circuit. Toshihide Ide
'
, Ryousaku Kaji
'
, Mitsuaki Shimizu
'
, Kenji
Mizllt3ni
2
, Hiroaki Ucno
2
, Nobuyuki Otsuka
2
, TctSllZQ Ucda
2
and
Tsuyoshi Tanaka
2
; 1ADPERC, AIST, TSllkuba, Ibaraki, Japan;
2panasonic, Kyoto, Kyoto, Japan.
Recently, by employing AIGaN/GaN HEMTs, low-loss switching
characteristics have been reported in switching COIlverter circuits.
However, when these converters are operated at a switching frequency
of above MH7., high-speed operation might cause considerable
radiated emission from the GaN-HEMT switching circuits. In this
study, the radiated emission from the GaN-HEMT switching converter
is investigated by two-dirncnsional clcctrornagnetic-probe scanning
The measured GaN switching converter is the half-bridge development
board EPC9001 made by EPC Corporation. The supply voltage Vcc is
24V. The switching frequency and duty ratio is 50Ok to 2MHz, and
50%, respectively. The radiated emission of the board is measured by
the whip antenna and the near-field probes in the anechoic charnber.
The spectrum of the electromagnetic field spread in the chamber has
the single peak at a frequency of 160 MHz. In addition, we performed
the two-dimensional z-direction magnetic-field Hz scanning at a
frequency of 160 in the altitude of 3mm from the GaN-HEMTs
on the board. The spectrurn of the radiated ernission around
GaN-HETMs agrees well with the spectrum of the spread
electromagnetic field in the chamber. When Vcc is varied, this peak
frequency is shifted. Therefore, we investigated the Vcc dependence of
the peak frequency. When Vcc is varied frorn 0 to 24 V, the peak
frequency is shifted from 110 to 160 MHz. This peak shift is thought
to be due to the change of the capacitance of the depletion region in
the GaN-HEMTs. Therefore, we calculate the resonant frequency
between the output capacitance of the GaN-HEMTs and the parasitic
inductance of the circuit wire Ls. The calculated results at Ls of 1.2
nH agree well with the experimental results.
DP3.09
Output Capacity on GaN HEMTs in Correlation to Its
Transistor Geometry and Sheet Resistance. Helrnut Jung
l
,
Peter Abele
l
, Jan Gruenenpuett
l
, Michael Hosch
l
, Schauwecker
Bernd" Herve Blanck
'
, Thomas Roedle
2
and Michael Schaefer
3
;
'United Monolithic Semiconductors GmbH, Ulm, Germany; 2 NXP
Semiconductors, 6534 AE Nijmegen, Netherlands; 3CADwalk GmbH
& Co, 89604 Allmendingen, Germany.
AIGaN-GaN HEMTs are dedicated for high power applications in
power bar designs especially for base station performance. Therefore,
the process has to be in the sense of high output power
density by sirnultaneously good and satisfying reliability. For
process-tracing and its control during fabrication, so called PCM
transistors are implemented across the whole wafer area. Lots of
parameters are measured on these PCM transistors, such as
breakdown voltage, current density, transconductance and also
small-signal-RF- parameters, such as input- and output-capacitance
and others. These rneasured results are irnrnensly irnportant for
tracing and controlling the process flow. Especially for power
applications a high output power is often a key request and power
information just from PCM- measurements would be very helpful and
appreciated. We found out that the gate-drain
srnall-signal-capacitance, called output capacitance, Cout, is directly
correlated to the RF-output power. In our case we could demonstrate
that wafers with high Cout showed high Pout. Thus the expected
output power can be directly estimated from the Cout-values
rneasured on the PCM transistors on wafer. As a consequence, Cout
has to be well understood in correlation to the epitaxy and process
parameters, especially the impact of transistor geometry, such as gate
sizes (foot and head) and field plate sizes. We investigated in detail
experimentally and also by simulation Cout in correlation to such
transistor pararneters. These investigations first revealed that Cout is
very significantly correlated to the sheet resistance, Rsheet of the
epitaxial layer measured in TLM structures with dimensions similar
to the transistor structure. An increase of Rsheet results in a decrease
of Cout. Since Cout relates to the effective charges in the channel. We
could show that Cout is directly proportional to 1/Rsheet. Transistor
RF-power becomes higher when Cout becomes higher. Therefore, the
process has to be optimized in the sense of high Cout. Additionally
this RF-output power evaluated from load pull measurements at 2
GHz were compared to Cout which shows also a very good
correlation. Another irnportant pararneter influencing Cout on
GaN-AIGaN HEMTs is the field plate (FP) si7,e. It is well known that
FPs are reducing the maximum electrical fields on the critical regions
between gate and drain. We in detail the impact of the FP
size on the Cout-value and found an increasing Cout for larger
FP-size. Further, the influence of the gate sizes (gate length and gate
head si7,e) was analY7,ed. Larger gate heads and larger gate lengths
leads to larger Cout, too. Finally, thicker Cap layer leads also to lower
Cout-values as the relevant distance, d, from the Schottky contact to
channel increases, in accordance with the sirnple capacitance rnodel.
The rneasured Cout-values in correlation to the transistor geornetries
were compared with simulated values and are in close agreement.
DP3.10
Controlled Barrier Oxidation and 100 0 C ALD for Gate
Insulation: A Way towards High-Performance Normally-off
GaN HEMTs? Dagmar Gregusova
'
, Michal Jurkovic
'
, Stefan
Hascik
'
, Alena Seifertova
'
, Michal Blaho
'
, Milan Tapajna
'
, Karol
Frohlich
l
, Joff Durleyn
2
, Marianne Gerrnain
2
and Jan Kuzrnik
l
;
I Institute of Electrical Engineering, Slovak Academy of Sciences,
Bratislava, Slovakia; 2 Epi GaN NV, Hasselt, Belgium.
There is an effort to develop normally-off HEMTs with a maximal
drain current Idsmax, rninirnal on-resistance Ron, and a rnaxirnal
threshold voltage V T. Oxidation of the gate area was reported to give
the positive V T together with a reduced gate leakage Ies, however,
with often severe (40 to 60 %) degradation of Id.<=ax and
transconductance grn compared to a virgin device. Reason for the
device degradation was not cornpletely clear. We used SiN (50
nm)/AIN (2 nm)/Alo.45GaNo.55N (3 nm)/GaN (150 nm)/
Alo.l8Gao.82N (2.3 ",m) grown by MOCVD on a 6 inch Si wafer. AIN
cap is supposed to provide a polarbation doping at the HEMT access
regions while it has to be oxidized in the gate opening to cancel
AIN/AIGaN quantum well (QW). We tested thermal oxidation which
was performed in an oxygen atmosphere at 750C for up-to 6 min.
Alternatively, a plasma oxidation was done at room temperature for
up-to 12 min under a very low power. Using a coupled
Poisson-Schrodinger solver, we calculated energy band diagrarns and
corresponding channel sheet resistances Rsheet assluning two lirniting
cases: with and without surface donors NDsurf at the AIOxN/AIGaN
interface. Comparisons of calculated Rsheet to the measured values
indicated a full compensation of any negative polarization charge at
the AIO
x
N / AIGaN interface by N Dam.f in the case of thermal
oxidation, while the negative charge seems to dominate in
the case of low-power plasma oxidation. This was in line with the
evolution of VT, which developed from - 1 V of the virgin device, to
about 0 V for the thermally AIN, and reached 1 V in the case
of plasrna oxidation. For the plasrna oxidized sarnple we found alrnost
invariant grn of oxidation time, which was about 125 mS/mm for a 2
",m gate length and 10 ",m source-drain distance. The virgin device
showed higher g= of 140 mS/mm presumably due to vicinity of the
un-oxidbed AIN/AIGaN QW. On the other hand g= 100 mS/mm
of the therrnally oxidized sarnplc indicated degraded channel. We
observed a more favorite Ies in the case of plasma oxidation, which
was reduced by about five orders of magnitude in the reverse bias
compared to a virgin device. Finally, on the plasma oxidized sample,
we deposited 10-nm-thick AI, 0
3
at 100 0 C by ALD, so that the same
resist rnask could be used thorough the processing. Additional oxide
provided the positive Ves swing enabling Ids=ax = 0.48 A/mm.
Despite substantial decrease of the gate capacitance, V T remained
constant, or was even shifted further towards 2 V in some cases. Such
270
a VT evolution can be again explained by an uncompensated negative
polarization charge at the plasma oxidized AIOxN/AIGaN interface.
In conclusion we suggest that the controlled barrier oxidation and 100
DC ALD gate insulation can lead to a high-performance normally-off
GaN HEMTs. Funding from EU FP7 project HipoSwitch (grant no.
287602) and Slovak projects APYY-0367-11 and APYY-104-10 is
gratefully acknowledged.
DP3.11
GaN-on-Si Wafers for HEMTs with High Power-Driving
Capability. Chengyu Hu, Saad Murad, Atsushi Nishikawa, Lars
Groh, Andrea Pinos, Weisin Tan, Ashay Chitnis and Stephan Lutgen;
AZZURRO Semiconductors AG, Dresden, Germany.
Ascribing to its low cost, GaN-on-Si technology is attracting more and
more attention from the electrical power semiconductor industry. Now
high-voltage GaN devices are rnainly in lateral configuration. For high
power-driving capability, the gate width can be as long as 100 mm or
even 1000 mm. Consequently, the requirements on wafer uniformity
and defect density are much more demanding. High yield of
large-perimeter devices is one of the key criteria for a high quality 150
lInn GaN-on-Si wafer for high voltage application. To address this
point, we evaluate the device-si7,e dependent buffer leakage by
measuring leakage current between isolated source and drain contacts.
We demonstrate high lateral Ybr@l J.tA/mm of 965 Y to 826 Y for
cornb test structure size up to 100 lInn. For a typical source-drain
distance of 14 rtIn we achieved excellent yield (>80%) at lateral
Ybr>600 Y@l J.tA/mm for 5 mm up to 100 mm devices. Based on
AZZURRO GaN-on-Si buffer technology, AIGaN/GaN-HEMT
structures with a typical thickness of 5-6 J.tm were grown by MOCYD
on 150 lInn Si(lll) substrates. We investigated the effect of isolation
depth on the lateral buffer breakdown to understand which layer of
the epi-stacks has dominant effect on the lateral buffer breakdown.
We found that the unintentionally doped GaN channel layer, which is
directly sited under the AIGaN barrier layer, is the most critical layer
for high lateral blocking capability. Furtherrnore, we found that the
lateral breakdown field (Ebr) was strongly affected by the growth
condition of the AIGaN/GaN-based buffer on the Si substrate. We
will show the impact of buffer growth on the GaN channel layer
quality and the corresponding lateral and vertical breakdown voltage
for large test device structures with high power driving capability.
DP3.12
Thermoelectric Study of Low Dimensional Thin Film GaN
Semiconductors. Bahadir Kucukgok", Baozhu Wang
2
, Qinyue He",
Andrew G. Melton", Na Lu
3
and Ian T. Ferguson"; "Department of
Electrical and Cornputer Engineering, University of North Carolina at
Charlotte, 9201 University City Blvd., Charlotte, NC 28223, USA,
Charlotte, North Carolina; 2College of Information Science and
Engineering, Hebei University of Science and Technology, 70 Yuhua
East Rd., Shijiazhuang, Hebei 050018, China., Hebei, China;
3Departrnent of Engineering Technology, University of North Carolina
at Charlotte, 9201 University City Blvd., Charlotte, NC 28223, USA,
Charlotte, North Carolina.
Therrnoelectric rnaterials have renewed interest frolIl rnany researchers
for last decay for both power generation and energy conservation
(waste-heat harvesting). Research in the discovery of best
thermoelectric materials (TE), such as, bulk materials, complex
structures, and the recent low dimensional plays crucial task to
achieve high efficiency TE rnaterials. The efficiency of a TE rnaterial
is strongly determined by its dimensionless figure of merit, shown as
ZT. Moreover, low dimensional structures offer a change to break the
interrelationship between the thermal and electrical transport which
gives great opportunity to obtain high efficiency devices. This
prornising enhancernent in ZT in low dirnensional rnaterials are
attributed to quantum-classical si7:e effect effects and increased
interfaces between layers resulted in scatter phonons strongly.
Therefore, in this study, the investigation of Seebeck and electrical
properties of low dirnensional thin filrn GaN, superlattice (SL) and
quanturn well (QW) were studied at roorn and high ternperatures. The
Seebeck coefficient as a function of applied temperature measurements
showed that Seebeck coefficient increased as the temperature increased
which is in a good agreement with common high-performance bulk TE
rnaterials. This Seebeck coefficient enhancernent due to vary
temperature is most likely induced by the system size decreases and
the density of state (DOS) is increased ultimately due to quantum
confinement. At 600K, highest Seebeck coefficients, 503J.tYK-1 and
420J.tYK-1, were observed for GaN SL and GaN QW samples,
respectively. Above 600K, sorne of SL and QW sarnples' Seebeck
coefficient tended to decrease due to unstable voltage values and heat
convection at 700K. Various Seebeck behaviors of QWs and SLs were
observed by their different multilayer structure configurations. For
comparison, n-type GaN thin film was also incorporated with low
dirnensional Seebeck values and showed lower Seebeck coefficient.
DP3.13
Noise Study of AIGaNjGaN FET Biosensors for High
Sensitivity Biodetection. Yuji Wang
1
and Wu Lu
1
,2; IDepartrnent
of Electrical and Computer Engineering, The Ohio State University,
Columbus, Ohio; 2Department of Nanobio Materials and Electronics,
Gwangju Institute of Science and Technology, Gwangju, Korea,
Republic of.
Over the past years, increasing attention has been drawn to
AIGaN/GaN FETs for biosensing due to its unique material
properties. To enhance the device sensitivity, optimization of surface
functionalization chernistry and device configuration has been
implemented. pM sensitivity of streptavidin protein detection in
phosphate buffered saline has been demonstrated in an AIGaN/GaN
bioFET biased at the sub-threshold regime with a control
gatel.However, there has been argument on what is the optimal bias
condition for bioFETs. In particular, sorne reports suggest that the
optimal biasing condition for bioFETs is the bias that gives the
maximum transconductance (Gm)2,3,while some other researchers
believe that the optimal biasing condition is at the subthreshold
regime
l
,4. To determine the optimal biasing regime, here we present
an evaluation of signal to intrinsic noise ratio (SNR) at different
biasing conditions by employing low frequency noise measurements
and extrinsic noise due to current deviation caused by variations of
probing contact pressure,reference electrode position,and device
stressing between rnultiple rneasurernents. Low frequency noise
rneasurernents were perforrned at three different biasing regirnes:
subthreshold regime,maxim Gm point, and saturation regime. The
normalized current noise power amplitude (Sf /1
2
) is the highest in
the subthreshold regime. Intrinsic SNR= Y) is introduced to
evaluate the device perforrnance, where 8i is the square root of the
integral of Sf over 1H7, bandwidth. is given by the change in the
product of the surface potential and Gm. The values of SNR are
1.8x 10
5
y-
l
(subthreshold),7x 10
5
y-
l
(maxim Gm),and
1.3 X 10
5
y-
l
(saturation),respectively,in three regimes. SNR is
maximized at the maxim Gm bias point, suggesting that biasing at
this point likely leads to a maximum absolute current change due to
specific binding, if only intrinsic SNR is considered. However, another
non-negligible factor is the current deviation between multiple
measurements under identical surface conditions, which is referred as
extrinsic noise, distinguished from the intrinsic noise from low
frequency noise measurements. The extrinsic noise is comparable to
the intrinsic noise in the subthreshold regirne and it is several
orders-of-magnitude higher than the intrinsic noise at the maxim Gm
point or saturation regime, which significantly degrades the sensing
ability in the linear and saturation regimes. For our devices, the
subthreshold regime is the best sensing regime, considering the impact
of both intrinsic and extrinsic noises. Under this biasing condition, 16
attomolar sensitivity (or 5 target molecules) has been demonstrated
for protein detection. To our knowledge, this is the highest sensitivity
ever reported on any field effect biosensors. 1. X.Wen et ai, App!.
Phys. Lett., 99, 43701,2011 2. N.K.Rajan et ai, App!. Phys. Lett., 98,
264107,2011 3.Q.Guo et ai, App!. Phys. Lett. 101, 93704,2012
4.X.P.A.Gao et ai, Nano Lett. 10, 547-552,2010
DP3.14
Unusual Contact Properties of GraphenejAIGaNjAINjGaN
Heterostructure. Haidong Zhang", Hyowook Kim
2
, Santhakumar
Kannappan
2
, Ye Shao", Charles W. Tn
3
,2 and Wu Lu",2; "Electrical
& Computer Engineering, The Ohio State University, Columbus,
Ohio; 2Nanobio Materials and Electronics, Gwangju Institute of
Science and Technology, Gwangju, Korea, Republic of; 3Electrical and
Cornputer Engineering, University of California at San Diego, San
Diego, California.
Graphene is a promising material as electrodes in semiconductor
electronic and optoelectronic devices. Here we report unusual
electrical properties of rnetal contacts on rnonolayer
graphene/ AIGaN/ AIN/GaN heterojunction field effect transistor
structure. Mono to few layer graphene was first grown on Ni/Si02/Si
substrate by chemical-vapor deposition, and then transferred onto
MOCYD grown AIGaN/ AIN/GaN heterostructure on a SiC substrate.
Hall rneasures show that the graphene layer has a rnobility 1770
cm2/Ys and a sheet resistivity of 497 n/-*bsquar*-. Ti/ Al/Ti/ Au
ohmic contacts to AIGaN/AIN/GaN 2DEG were formed by rapid
thermal annealing followed by non-annealed Ti/ Au contacts on
graphene. The current-voltage (I-V) characteristics show a near linear
forward current 250 n) at forward bias with a small 0.2 Y)
turn-on voltage. When the graphene contact is negatively biased, the
device exhibits both rectifying -2.5 Y) and ohmic n at <
-2.5 Y) behavior. A cross-over voltage is observed at both forward and
reverse bias frolIl ternperature dependent rneasurernents, suggesting
that the device behaves as a rectifying diode only in a small bias
range. Under forward biases, the low flat voltage is attributed to the
low local barrier of AIGaN to graphene due to local Ga rich (or Al
less) regions in AIGaN. Under reverse biases, the graphene's Fermi
level is shifted up, resulting a lower graphene work function hence a
271
smaller barrier according to the Schottky-Matt model, with increase
of negative bias. We thus attribute this unique electronic property of
graphcnc/nitridc scrniconductor hctcrojullctions to bias dependence of
barrier height caused by the work function change of graphene as a
function of bias. The results in this study provide a general
understanding of metal/graphene contacts on III-nitride
semicondllctors.
DP3.15
High Mobility InAIN/AIN/GaN HEMTs Grown on 6 Inch Si
Substrates. Po-Tsung Tu', Geng-Yen Lee', Yeh
2
and
.Jen-Inn Chyi,,2,3; 'Department of Electrical Engineering, National
Central University, Jhongli, Taiwan; 20ptical Sciences Center,
National Central University, Jhongli, Taiwan; 3Rcscarch Center for
Applied Sciences, Academia Sinica, Taipei, Taiwan.
AlInN, a material lattice-matched to GaN, is very promising for high
current, high transconductance, and high RF pcrforrnancc
high-electron-mobility transistors (HEMTs). However, to grow high
quality AlInN-based HEMT is challenging due to the large
immiscibility and difference in thermal stability between AIN and
InN, especially on silicon substrate. In this report, we will
dClnonstratc, to the best of OUf knowledge, the highest electron
mobility for AlInN-based HEMTs grown on 6-inch silicon substrates.
The AlInN HEMT structure was grown by Aixtron close-coupled
showerhead MOCVD system on a 6 inch Si (111) substrate. It
consisted of a 1.25 /-Lm AIN/ AIGaN composite buffer layer followed by
a 2.5 rLIn GaN undopcd buffer layer, an optirnizcd 1 HIll AIN spacer
layer, a 13 nm InAIN barrier layer with 88% of Al content, and a 13
nm GaN cap layer. The structure exhibited a high electron mobility of
1670 cm
2
V-'s-' with a high sheet carrier concentration of 1.63xl0'3
cm-
2
simultaneously, which led to a low sheet resistance (Rsh) of 229
ahrn/sq as obtained by Hall rIlcasurcrncnts. Large MOS-HEMTs with
Lc= 8 /-Lm, LDs= 26 /-Lm, and W c= 200 /-Lm were fabricated for
in-depth investigations. Attributed to the high mobility and low Rsh
of this structure, the InAIN/ AIN/GaN MOS-HEMTs exhibited a high
rnaxirnurn drain current density (Id,max) of 810 rnA/rnrn under V GS
of 3 V and V DS of 10 V, and a low Ron of 2.85 mohm-cm
2
. The
devices had threshold voltage of -14.3 V with good pinch-off
characteristics as indicated by a low drain leakage current of 10-
8
A/rnrn at the gate voltage of -20 V. Detailed device characteristics
will be presented.
DP3.16
Unipolar Vertical Transport Characteristics in III-Nitrides.
Digbijoy N. Nath', Zhichao Yang', Pil S. Park', Chun Y. Lee
2
, Yuh
R. Yu
2
and Siddharth Rajan
1
; IThe Ohio State University,
Columbus, Ohio; 2National Taiwan University, Taipei, Taiwan.
Unipolar III-nitride vertical devices exhibit unacceptably high leakage
currents which has prevented successful dernonstration of several
devices including resonant tunneling diodes, unipolar vertical
transistors, and vertical field effect devices (CAVETs). In this work,
we show that vertical transport in GaN/ AIGaN/GaN heterostructures
is dominated by percolation-based transport due to random alloy
fluctuations in the ternary AIGaN barrier. Potential barriers without
random alloys were designed using digital alloy and binary barriers,
and were found to eliminate percolation transport. To investigate the
origin of vertical current, a series of n+GaN/30nm AIGaN/n+GaN
structures were designed, where AIGaN composition was varied from
15-37%. Vertical currents were rneasured to be high (rv few kA/crn2
at 2 V) and independent of the AIGaN barrier composition. Current
densities estimated using Fowler-Nordheim tunneling theory and 2D
device simulations (Silvaco) were found to be several orders of
magnitude lower than those measured. To understand the impact of
dislocations, growths were perforrned on substrates with threading
dislocations varying from 105 cm-2 to "",108 cm-2. The measured
leakage was found to be independent of dislocation density. Sidewall
leakage was also shown to not playa role. The current shows weak
dependence on ternperature, elirninating trap-assisted or hopping
transport as a rnechanisrn. Since vertical currents do not depend on
heterojunction barrier height, dislocations, or sidewall leakage, we
hypothesize percolation-based transport as the dominant transport
mechanism. We propose that random alloy fluctuations in the ternary
AIGaN provide GaN-to-GaN nano-island-rnediated percolative path
for electron transport. Simulations were done using a 2D FEM
drift-diffusion model of transport and incorporating statistical
fluctuations in the AI-composition in AIO.2GaO.8N barrier1. The
vertical current obtained from this simulation was found to be
significantly high, whereas rernoving the fluctuation in Al-cornposition
in the simulation led to negligible current densities. To reinforce the
simulation results and test our hypothesis, barrier designs based on
non-random alloys were pursued using two methods: digital alloys and
barriers. Digital AIO.3GaO.7N barriers formed
by repeated 2 ML AIN/ 4 ML GaN were found to eliminate vertical
leakage by up to 3 orders of magnitude, confirming the role of alloy
fluctuations in vertical leakage. A second method based on
polarization-engineered GaN barriers using a thin InGaN layer to
provide polariZ'iation-induced dipole was tested, and was also found to
reduce vertical leakage by sirnilar rnagnitude. Our dernonstration of
the dominance of percolation transport in vertical AIGaN/GaN
transport, and methods to eliminate this are expected to have
profound impact on GaN vertical devices. [Acknowledgment: This
work is funded by Office of Naval Research (Dr. Paul Maki), (DATE
MURI project)][IJ Y.-R. Wu, R. Shivaraman, K.-C. Wang & .J. S.
Speck, App. Phys. Let. 101, 2012.
DP3.17
Low Ohmic Contact Resistance Re<O.l Omm for GaN
HEMTs Using Au-Free Metallization and Low-Temperature
Annealing. Zhihong Liu', Dirk Fahle
2
, Michael Heuken
3
, Geok Ing
Ng
1
,4 and Tomas Palacios1,5; lSingapore-MIT Alliance for Research
and Technology, Singapore, Singapore; 2 RWTH Aachen University,
Germany; 3AIXTRON SE, Germany; School of EEE,
Nanyang Technological University, Singapore, Singapore;
5Massachusetts Institute of Technology, Cambridge, Massachusetts.
Recently the heterogeneous integration of GaN optoelectronic devices
and transistors with Si CMOS digital integrated circuits has attracted
rnore and rnore interests, as it would enable a new level of circuit
design flexibility. Although some CMOS-compatible Au-free ohmic
contacts have been reported by our group and others, however, there
is still a lack of a CMOS-compatible low-annealing-temperature ohmic
contact technology, which is required for the CMOS-first GaN-Si
integration process. In this work we report a rnethod to realize very
low contact resistance (Re<0.10mm) using Au-free metal schemes
annealed at 500 DC through an n+-GaN/n-AIGaN/GaN structure.
Fig.l shows the schematic of the n+-GaN/n-AIGaN/GaN structure
and Fig. 2 draws its band diagram. The highly doped n+-GaN cap,
together with the doped AIGaN barrier, pull down the conduction
band and make the electrons easier to travel between the ohmic metal
and 2DEG. The wafer was provided by AIXTRON, and the process
includes BCI
3
/Cb plasma mesa etching followed by Ti/ Al (20/200
run) ohrnic rnetallization. Fig. 3 and Fig. 4 show the Rc and specific
contact resistivity PC rneasured by TLM after RTA at various
temperatures for 1 m, and at 500 DC for different temperatures,
respectively. At 500 DC for 1 m, the device obtained the lowest Re.
Compared to the typical RMS value>100 nm for Ti/AI/Ni/ Au ohmic
rnetal, the optirnized Ti/Al contact has a rnuch lower RMS of rv5 nIll.
Fig. 5 shows the TLM results of the Ti/Al ohmic contact just after
RTA and after the n+-GaN cap was removed. It can be seen that the
contact resistance does not change much when the n+-GaN cap was
removed. This shows the great potential for this low-temperature
ohrnic contact technology to be applied into the GaN-Si integration.
DP3.18
GaN-to-Si Vertical Conduction Mechanisms in
AIGaN/GaN-on-Si Lateral Heterojunction FET Structures.
Shu Yang, Qirneng Jiang, Daikui Li, Zhikai Tang and Kevin J. Chen;
Hong Kong University of Science and Technology, Kowloon, Hong
Kong.
GaN-based lateral power HEMTs and MIS-HEMTs implemented on
cost-effective and large-si7:e GaN-on-Si platform are attractive for
high-voltage power switches. For the mainstream AIGaN/GaN-on-Si
heterostructures, the breakdown voltages are ultimately limited by
GaN-to-Si vertical leakage. The forward and reverse GaN-to-Si
breakdown rnechanisrns have been investigated in sarnples on a high
resistivity Si substrate using high-voltage C- V measurement and on a
low resistivity Si substrate using temperature-dependent 1- V
measurement. When the GaN-Si diode is reverse-biased, the ohmic
contact to the top of GaN layer furnishes a free-electron reservoir that
provides electrons to fill/charge the buffer traps and eventually flow
to Si substrate, whereas the electron injection mechanism with the
GaN-Si diode forward-biased (which is more relevant to lateral power
HEMTs that operate at large positive drain bias) is not well
understood to date. This work investigates the charge
accurnulation/ depletion at the GaNlSi interface on a low reBiBtivity
p-type Si substrate under high-voltage operation, by conjunctly using
the temperature-dependent high-voltage C- V, 1- V characterizations,
and device simulation. The measured 1- V characteristics in an
AIGaN/GaN-on-Si reveal a clear difference between the reverse and
forward conductions. With an increasing forward voltage, 1D
simulation results indicate a physical process in the following
sequence: 1) ionization of acceptor traps and hole depletion in the
GaN buffer; 2) depletion/weak-inversion of the p-type Si at the
GaN/Si interface until the critical electrical field of Si (0.3 MV/crn) is
reached; 3) impact ionization in Si that provides free electrons to be
injected into GaN, which in turn, can fill up the donor traps in GaN.
Temperature-dependent high-voltage C- V characteristics feature two
falling edges that related to two turning points in the forward vertical
conductions. The first one validates the occurrence of Si depletion
which occurs prior to weak inversion and impact ionization. After the
donor traps in GaN are filled up with electrons that are injected from
272
Si, the second falling edge appears, the onset of which is reduced at
higher temperature because of the enhanced thermionic at the
GaNlSi interface and electron capture process by the donor traps in
GaN buffer.
DP3.19
High Performance AlGaN/GaN-Based Schottky Barrier
Diode with Very Low Reverse Recovery Charge at High
Telllperature. Jae-Hoon Lee
l
, Jong-Kyu Yoa
l
, Heon-Bok Lee
l
,
Myung-Sub .lung', Chanho Park', Hee-Sung Kang
2
and .lung-Hee
Lee
2
; 'Discrete Development, System LSI, Samsung Electronics Co.,
Ltd., Yongin, Gyuuggi-Do, Korea, Republic of; 2School of Electronic
Engineering & Computer Science, Kyungpook National University,
Daegu, Kyungpook, Korea, Republic of.
Several groups have reported excellent high breakdown voltage
pcrforrnancc frorn both lateral and rncsa-gcolnctry GaN and AIGaN
SEDs. However, most of them suffered from very high on-resistance
because of large series resistance caused by large distance between
anode and cathode. To increase the on-current, vertical-type GaN
SI3D fabricated on a bulk GaN wafer has been suggested. The device
is, however, vulnerable because the current flow of the device is
parallel to the direction of the dislocation propagation, which
considerably lowers the breakdown voltage of the device than
expected. In this work, we fabricated a Multi-finger lateral-type
AIGaN/GaN Schottky barrier diode (SI3D) fabricated on the
AIGaN/GaN heterostructure grown on sapphire substrate and also
present the electrical properties of the SBD measured by varying
temperature. To achieve high-power operation, a bonding pad over
active (BPOA) structure was used with opt imbed anode-to-cathode
distance. The I3POA allows the placernent of bonding pads over active
layer without the addition of reinforcing layers, which offers a
significant reduction in both the overall size of the die and the series
resistance of pads. The multi-finger patterned large-area SBD with
BPOA structure (BPOA-SBD) was fabricated. The size, the length of
the anode periIneter, and the anode-to-cathode distance for both
devices are 3000 etm X 3000 etm, 270 mm, and 20 etm, respectively.
The turn-on voltage and forward current of the packaged BPOA-SBD
at 1.5V is about 0.8 V and 4.5 A at room temperature, respectively.
As increasing teInperature, the turn-on voltage of the I3POA-SI3D
continually decreases due to the reduction of the band gap energy
which is inversely proportional to the temperature. However, the slope
of the current decreases as temperature increases in spite of the
decreased turn-on voltage. This results from the fact that the electron
Inobility for a rnajority carrier device decreases as ternperature
increases but the increase in 2DEG density is not significant in this
temperature range. The forward current of the BPOA-SBD at 1.5V is
about 2.5 A at 200C, which is 45% lower in magnitude compared to
the value at room temperature. The leakage current of the
I3POA-SI3D at a reverse voltage of - 600 V was 6 and 9.8 ILA at room
temperature and 175 a C. The corresponding values of the Si-diode are
0.2 and 17 etA. Though the reverse leakage current of the BPOA-SBD
at room temperature is higher than that of the Si-diode, but the
current of the SBD at high temperature is much smaller than that of
the Si-diode. The soft breakdown voltage of the I3POA-SI3D at
leakage current of 250 etA was 747 and 767 V at room temperature
and 175 C, respectively. The corresponding values of the Si-diode are
680 and 717 V due to avalanche breakdown. A typical reverse recovery
wave form of the BPOA-SBD was measured at the forward current of
IF = 4 A, the supply voltage of 400 V, and the di/dt of 200 A/liS at
room temperature and 175 a C. The reverse recovery time (Trr) of the
BPOA-SBD is 19.4 and 19.6 ns at room temperature and 175C,
much lower than the corresponding value of 26.6 and 116 ns for the Si
diode due to the high electron velocity of the originated rnaterial,
which is also cornparable to those obtained for srnall-area GaN-based
SBDs reported elsewhere. The temperature variations of BPOA-SBD
for the reverse recovery characteristics are much better than those of
Si-diode. The reverse recovery charge (Qrr) of Si-diode increases from
51.7 nC at 25C to 403 nC at 175 DC, which that of I3POA-SI3D
increases from 19.7 nC at 25 0 C to 19.93 nC at 175 DC. These
excellent device characteristics demonstrate that the AIGaN/ GaN
SBD with BPOA structure has a great potential application to the
high power electronics.
DP3.20
AlN/GaN Heterostructure TFTs with Plasma Enhanced
Atomic Layer Deposition of Epitaxial AlN Thin Film.
Cheng Liu', Shenghou Liu', Sen Huang,,2, Baikui Li' and Kevin.l.
Chen'; 'Department of Electronic and Computer Engineering, Hong
Kong University of Science and Technology, Hong Kong, Hong Kong;
2Department of Microwave Devices and Integrated Circuits, Institute
of Microelectronics of Chinese Academy of Sciences, Beijing, China.
AIN/ GaN heterostructure was realized by deposition of AIN thin fiIrn
with low-therInal-budget (300C) plasrna enhanced atoInic layer
deposition (PEALD) on a semi-insulating GaN /sapphire-substrate
template. The micro-structures, chemical composition distribution
and electrical properties of the AIN/ GaN heterostructure were
studied. The single-crystal epitaxial nature of ALD-AlN thin film on
GaN was confirIned by grazing incidence X-ray diffraction (GIXRD)
and high resolution transmission electron microscopy (HRTEM). The
first several monolayers ~ 3 n m of the ALD-AlN layer features
well-arranged atomic structure that follows the crystal pattern of the
underlying hexagonal GaN buffer. The resultant crystalline hexagonal
ALD-AIN fiIrn introduces a large binding energy of AI-N bond near
the ALD-AlN/GaN interface, as confirmed by X-ray photoelectron
spectroscopy (XPS). The ALD-AIN/GaN interface is atomically-sharp
without significant oxygen and carbon contamination. Owning to the
spontaneous and piezoelectric polarization of hexagonal crystal
ALD-AIN grown on GaN in our experirnent, a two-dirnensional
electron gas (2DEG) channel is formed at ALD-AlN/GaN interface.
The 2DEG density is extracted to be 1. 7 X 10'2/cm2 from the C- V
characteristics of a MIS-diode with an Ab03/ALD-AlN/GaN
structure. Srnall frequency dispersion (rv 3%) between 1 kHz and 100
kHz was obtained by the frequency dependent C- V measurement,
suggesting low-density traps at the ALD-AIN/GaN interface. Finally,
thin film transistors (TFTs) have been successfully fabricated with
Al
2
0
3
gate dielectric grown in - situ with AlN thin film. No
significant current crowding for the output perforInance was
implicated at low V DS, despite the presence of large source/drain
access resistance (Rs, R D ~ 150n-mm) as a result of the non-alloyed
source/drain contacts (Ti/ Au). The proposed TFTs exhibit good gate
control with a low sub-threshold slope of ~ 85 mV/dec and a low-field
rnobility of rv 27 crn
2
/(V-s), which is one order of Inagnitude higher
than that achieved in AIN/GaN heterostructures grown by magnetron
sputtering. The enhanced performance is attributed to high-quality
interface obtained at the ALD-AlN/GaN interface.
DP3.21
Pulsed Metal Organic Chemical Vapor Deposition of
Ultrathin AlN/GaN Heterostructure Field-Effect Transistors
Using Indium as Surfactant. JunShuai Xue, JinCheng Zhang and
Yue Hao; Xidian University, Xi'an, China.
Ultrathin all-binary AlN/ GaN heterostructures potentially offer the
highest performance HEMTs in the III-V nitrides due to the added
ease of vertical scaling for reducing short-channel effects. Many of the
reported results are realized by rnolecular beaIn epitaxy (MBE),
mainly because of its special capability to grow AlN barrier with high
quality and sharp interface. However, MBE is not economically
feasible and cannot satisfy the market requirement of mass-production
like metal organic chemical vapor deposition (MOCVD). In spite of
the potential application advantages, MOCVD ernploys high growth
temperature to achieve high quality AlN barrier, which is limited by
the ability of reactor heating system and requires special heater and
growth chamber designs. So, there have been few reports on the
growth of AlN/GaN heterostructures by MOCVD. In our previous
study, high quality nearly lattice-matched InAIN/GaN
heterostructures have been successfully grown by pulsed-MOCVD
(PMOCVD) based on series of optimization of growth parameters.
Here, this abstract presents a study of growth and characterization of
ultrathin AlN/GaN heterostructures grown by PMOCVD using
indiurn as surfactant at high growth teInperature. By optirnization of
growth temperature and thickness of AIN barrier layer, a high
electron mobility of 1398 cm2/Vs and a sheet carrier density of
1.3x 1013 cm-2 are demonstrated for the AlN/GaN heterostructures
with a barrier layer thickness of 4 nrn grown at a relatively low
temperature of 830 oC. Furthermore, we fabricate AIN/GaN HEMTs
on these heterostructures. A maximum drain current density of 305
mA/mm and a maximum transconductance of 95 mS/mm are
demonstrated for the AlN/GaN HEMT with a gate geometry of
(0.6x50) x2 lim2. Aggressive shortening of gate length by adopting
advanced electron beam lithograph and reduction of Ohmic contact
resistance by optimization of Ohmic contact metals and annealing
conditions can be pursued and applied to the future device process to
further improve the device characteristics. In light of the presented
results, PMOCVD could be a viable technique for epitaxy of ultrathin
AIN/GaN HEMT structures.
DP3.22
Thermal Assessment of GaN on-Si HEMTs and Diodes with
Different Cap Layers: GaN, in situ SiN, and in situ SiN/GaN.
Sara Martin-Horcajol, Maria Fatima Romero Rojol, Zhan Gaol,
Ashu Wang', Marko .l. Tadjer
2
, A. Koehler
2
, T. Anderson
2
and
Fernando Calle'; 'Dep. Ingenieria Electr6nica (ETSIT
Telecomunicaci6n), ISOM & Technical University of Madrid, Madrid,
Madrid, Spain; 2Naval Research Laboratory, Washington, District of
Columbia.
Gallium nitride based high electron mobility transistors grown on Si
substrate (GaN on Si HEMTs) are very attractive candidates for the
next generation cost-effective power devices. A lot of efforts have
already been done for the optimization of the epilayer quality and
technology as well as the use of the in situ SiN cap layer, in order to
273
have robust devices under harsh conditions. Additionally, D. Marcon
et al showed recently that in situ SiN cap layer is able to prevent
Inatcrial degradation at high tcrnpcraturc, in contrast to CaN cap or
without cap layer. However, the responsible mechanisms are partially
unknown, and further studies are demanding. The thermal stability of
A1GaN/GaN heterostructures (HS) using three different cap layer
(GaN (3 nm), in situ SiN (3 nm), and in situ SiN (3 nm) on top of the
GaN (3 nm) cap) has been systematically investigated. HEMT and
test diodes have been fabricated simultaneously in the three HS,
which are identical except for the cap layer. Both of the in situ
SiN-based HS were found to reduce drastically the gate leakage
current up to 4 orders of rnagnitudc, respect to the without-SiN
devices. Interestingly, the gate lag was snprcsscd only in the case of
SiN/AlGaN/GaN HEMTs and it correlates with the capacitance
measurements. Double pulsed gate and drain voltages were used to
discuss further the self-heating, drain-lag and gate lag in the different
HS, as a function of the gcornctry and T froIn 25K to 550K
DP3.23
First-Principles Calculations of Structural and Electronic
Properties of GaN(OOOl)/Au Interface.
and Stanislaw Krukowski,,2; 'Institute of High Pressure Physics,
Polish Acadcrny of Sciences, Warsaw, Poland; 2Intcrdisciplinary
Centre for Mathematical and Computational Modelling, Warsaw
University, Warsaw, Foland.
The problem of gallium nitride's Ga-terminated (0001) coverage with
bulk rnctals is still not well-represented in the literature. Although
some theoretical models of GaN/ Au interface were described recently,
they consider only zinc blende GaN with no built-in spontaneous
Le., no built-in electric field, Ga-terminated GaN(OOOI)
surface, covered with Au atoms is studied by density functional
calculations in slab-vacuurn rnodel, rarely used for
metal-semiconductor interface simulations. System properties were
studied in function of the electric field, Fermi level or equivalently, the
doping of the semiconductor bulk. The configurations used are lxl
and 2x2 slabs with vacuurn up to 30 A to cancel the effect of
periodicity. Metallic part of the structure is deposited one by one on
top of GaN slab and relaxed. The following structural and electronic
parameters, customary used to describe metal-semiconductor
interface, are calculated: structural parameters of Au phase imposed
by GaN (hexagonal AI3AI3 for lxl slabs and body centered
orthorhombic (bco) for 2x2 slabs) as compared to bcc Au phase, the
most stable in ambient conditions, interlayer distances of fully relaxed
Au bulk showing that bco Au phase is more relaxed, Schottky barrier
height (SBH, V for p-type GaN), electric potential showing no
irregularities in Au part, projected density of states across the
structure confirming fast fade-out of metallic states (two layers) inside
the semiconductor, band edges of the semiconductor part, band
structure projected onto interface plane (r-K-M). The possibility of
emergence of the localbed midgap states is discussed. The
consequences of the obtained results are discussed, e.g., rnetallicity of
the system (bandgap closure), linear dependence of SBH and energy
levels on electric field. This work is considered as the step towards
contact modelling on p-type GaN(OOOl) surface, especially Ni/Au
contact scherne, which becornes a technological standard and yet lacks
full control and full understanding. (The research supported by the
EU, European Regional Development Fund, Grant Innovative
Economy POIG.01.01.02-00-008/08, and Polish National Science
Center, Grant No. 20l2/05/B/ST3/02516,)
DP3.24
High Performance Normally-Off AlGaN/GaN MOSFET with
Al2 0 3 High-k Dielectric Layer Using a Low Damage Recess
Technique. Ye Wang', Maojun Wang', Bing Xie', Jinyan Wang',
Yilong Hao', Wengang Wu', Bo Shen
2
and Kevin .1, Chen
3
; 'the
Institute of Microelectronics, Peking University, Beijing, China;
2School of Physics, Peking University, Beijing, China; 3Dept . of
Electronic and Computer Engineering, Hong Kong University of
Science and Technology, Hong Kong, China.
A low darnage digital etching process using pre-oxidation and
following oxide wet etching to recess the AIGaN barrier and achieve
normally off operation for A1GaN/GaN MOSFET with Ab03 high-k
gate dielectric is demonstrated. The wet etching process eliminates
the large damages induced by plasma bombardment with chemical
and physical interactions in conventional inductively coupled plasrna
(ICP) etching process and atomic smooth surface morphology could
be reserved. The fabricated recessed A1GaN/GaN MOSFET exhibited
a completely enhancement-mode operation and excellent device
perforrnances. The rnaxirnurn output current density is 528 rnA/nnn
at 8 V gate bias with a threshold voltage of 1.68 V. The gate leakage
current is below 10-
7
mA/mm when the gate bias is below 2 V and
slowly increases to 3.5xlO-
4
rnA/rnrn when the gate bias is 7 V due
to the accumulation of electrons in the GaN channel. The three
terminal off-state breakdown voltage for the device with 3 Mm
gate-drain distance is 182 V when the gate terminal is biased at 0 V,
Such performance is benefiting from the good quality of the
AI20
3
/GaN interface as indicated by high resolution transmission
electron rnicroscopy, suggesting that the AIGaN barrier recess process
based on wet etching is of low damage and could be an effective
method to achieve normally-off operation for AlGaN/GaN FETs with
high performance,
DP3.25
Low Leakage Current AIGaN/GaN-on-Si HFETs Using
Gallium Oxide Sacrificial Layer. Jae-Gil Lee', Sang-Woo Han',
Bong-Ryeol Park', Kwang-Seok Se0
2
and Ho-Young Cha'; 'School of
Electronic and Electrical Engineering, Hongik University, Seoul,
Korea, Republic of; 2 Department of Electrical Engineering and
Computer Science, Seoul National University, Seoul, Korea, Republic
of.
A1GaN/GaN heterostructure FETs are suitable for high power
switching applications due to high carrier density, high mobility, and
high breakdown field. The leakage current plays an important role in
power loss during off-state condition and thus great care should be
taken of suppressing the leakage current. The surface of AlGaN/ GaN
HFETs tends to be damaged during device fabrication, especially
during high-temperature annealing. Though a prepassivation process
can reduce the surface damage by protecting the surface during device
processing, the high-temperature induced surface damage cannot be
cornpletely prevented. In this study, we developed a new process
employing a gallium oxide sacrificial layer to suppress the leakage
current. The process sequence of A1GaN/GaN-on-Si HFETs was (a)
mesa isolation, (b) ohmic contact formation and annealing at 830C,
(c) oxygen plasma treatment to form a GaOx sacrificial layer, (d) wet
etch to rernove the sacrificial layer, and (e) gate forrnation. The
epitaxial structure consisted of a 4-nm undoped-GaN layer, a 20-nm
undoped-Alo,23Gao.77N barrier, a I-nm AIN spacer, a 1.7-Mm
undoped-GaN buffer, and transition layers on an N-type Si(111)
substrate. The thickness of the GaOx layer formed by the oxygen
plasrna treatrnent was rv2 rnn. A reference sarnple without the oxygen
plasma treatment was also fabricated for comparison. Since the
epitaxial structure consisted of a 4-nm GaN top layer on top of
A1GaN/GaN structure, it is expected to have a lower effective barrier
height on the surface after rernoving the sacrificial layer. Nevertheless,
insignificant change was observed in threshold voltage and drain
current whereas the leakage current decreased dramatically by a few
orders of magnitude (from 90 MA/mm to 360 nA/mm at 100 V). It
was found that significant reduction in buffer leakage current were
associated with the total leakage current reduction. Both sarnples
exhibited similar breakdown voltages, i.e. 1018 V at LCD 20 Mm. In
order to investigate the change in the surface condition, several
samples with different treatments were prepared and examined using
X-ray photoelectron spectroscopy (XPS), Increase in carbon quantity
and nitrogen vacancy was observed after high-ternperature ohrnic
annealing, which seemed to be responsible for the high leakage
current. After oxygen plasma treatment, the carbon quantity
decreased while oxygen quantity increased. Ga 3d spectrum was
shifted to higher binding energy compared to as-grown and ohmic
annealed sarnples. However, when the GaO
x
sacrificial layer was
removed by wet etch, the initial binding energy was recovered. It is
suggested that the proposed process in this study can effectively
suppress the leakage current and thus reduce the power loss during
off-state,
DP3.26
The Effect of Residual Impurities in the Epitaxial Layer on
Fe-Doped GaN. Tetsuo Narita,,3, Hiroko Iguchi,,3, Tsutomu
Uesugi
1
,3, Tetsu Kachi
1
,3 and Tarnotsu Hashizurne
2
,3; lElectronic
Devices Research Div., TOYOTA CENTRAL R&D LABS. INC.,
Nagakute, Aichi pref, Japan; 2RCIQE, Hokkaido University, Sapporo,
Hokkaido pref., Japan; 3Japan Science and Technology Agency (JST),
CREST, Tokyo, Japan.
GaN-based switching devices have recently attracted significant
attention as core devices for in-vehicle inverters. GaN films prepared
by hetero-epitaxial growth on various substrates such as a sapphire
have the high density of dislocations. On the other hand, the high
quality free-standing GaN substrates have been reported recently, and
expected as device application requiring high reliability. We
investigate the epitaxial growth process to effectively utilize a high
resistivity (HR) GaN substrate for a lateral device. We prepared three
sarnples grown by rnetalorganic chernical vapor deposition on Fe
doped HR-GaN substrates provided by Hitachi Cable, Ltd. The layer
structure of sample A is a HR-GaN, a 2 Mm thick unintentionally
doped (UID) GaN, and a 25-nm-thick AIO.25GaO.75N layer. The Fe
concentration and the dislocation density were 2.6e18 cm-3 and under
3e6crn-2, respectively. The structures of sarnple Band C arc carbon
doped (CD) GaN layers, UID-GaN layers, and 25 nm thick
AIO.25GaO.75N layers on HR-GaNs. The Carbon densities of UID- and
CD-GaN layer were 2e16cm-3 and leI8cm-3, respectively. The
thicknesses of CD-/UID-GaN were 0.05/1.95 Mm and 1.5/0.5 Mm for
274
sample Band C, respectively. In order to demonstrate the buffer
leakage current, samples were processed as follows. Two electrodes
with Ti/ Al/Ni (20/200/100 nm) were deposited and annealed at 650
DC. Then only 200-nm-depth of the gap between electrodes was
etched by inductively coupled plasma. Finally, the etched surfaces
were passivated by the polyimide to prevent the surface leakage
current. The hall measurement showed the high mobility over 1700
crn2/Vs for all sarnplcs. The result of secondary ion rnass spectroscopy
for sample A showed the upward diffusion of Fe atom and the
spike-like Si at the interface between the epitaxial layer and the
substrate due to the adhesion of contamination. The Fe concentration
decreased exponentially with thickness of DID-CaN and was under
2c14 cm-3 in the upper 0.5 lun of UID-GaN. The UID-GaN contained
Oxygen of 1e16 cm-3 and Si under 2e16 cm-3. The result of 1- V curve
for sample A showed the large leakage current over 1mA/mm at 100V
independent of the gap width. The leakage current of sample B was
about 1/10 for sample A. The result of sample C showed the lowest
leakage current of 76pA/mm at 100V and the breakdown voltage,
which depended on the gap width, over 600V for the 10-J.'m gap
width. We can think of two leakage pass; one is the pass through the
spike-like Si, and the other is through UID-GaN due to residual
irnpllritics. The leakage current of sarnplc 13 was luuch higher than
that of sample C in spite of the compensation by Carbon for spike-like
Si donors. If the epitaxial layer has the high density of the edge
dislocations, low levels of carriers are trapped; and the material
appears to be insulating. Our results indicate that residual impurities
act as free carriers for the high quality UID-GaN because there is
little compensation due to dislocations.
DP3.27
Investigation of the Ti/ AI/ Pt/ Au and Ti/ Au Contact
Materials on N-face Surfaces of Oxygen Doping GaN.
Chia-Lung Tsai
'
, Yi-Keng Fu
'
, Hung-Tse Chen
2
, Chin-Hsueh Chou
2
and Rang Xuan
1
; lElectronics and Optoelectronics Research
Laboratories, Industrial Technology Research Institute, Hsinchu,
Taiwan; 2LED Opto-electronic OU, Walsin Lihwa Corporation,
Taoyu3n, Taiwan.
Ti/ AI/ Pt/ Au and Ti/ Au ohmic contact materials on N-face
surfaces of oxygen doped GaN (GaN:O) were investigated by
measuring the specific contact resistivity (pc) with respect to
annealing tcrnpcratnrc. Til Au contact showed good ohrnic property
in contrast to Ti/ Al/ Pt/ Au contact on N-face surface of GaN:O.
Based on the x-ray photoelectron spectroscopy results, we found that
the formation of N-Al bonds with increase anneal treatment
temperature and the increase of upward band bending near the N-face
GaN:O surface rnight lead to an increase in the effective Schottky
barrier high, resulting in an increase in the pc of N-face GaN:0.
DP3.28
Interface Charge Characterization of AIGaN/GaN MOS
Structures with High-Ii: Gate Insulator by
Capacitance/Conductance Measurements. Roman Stoklas
'
,
Dagmar Gregusova1, Kristina Husekova
1
and Peter Kordos
2
;
I Optoelectronics, Institute of Electrical Engineering, Slovak Academy
of Sciences, Bratislava, Slovakia; 2Microclcctronics, Institute of
Electronics & Photonics, University of Technology, Bratislava,
Slovakia.
AIGaN/GaN MOS structures that have a high-Ii: Al203 or Zr02 gate
insulator were studied by capacitance rncasurcrncnt to evaluate their
interface properties. The insulators with a thickness of ",,20 nm and
dielectric constant of 9 (AI203) and 23 (Zr02) were deposited by
CVD. Annealing of Zr02 was applied, as follows from our previous
study on InAIN/GaN MOS structures [1]. The C-V characteristics
were lneasured at various frequencies (lkHz-1MHz) and telnperatures
(25
D
C-200
D
C). The data is presented using a parallel
capacitance-conductance (C-G-V) model. The bias voltage was swept
from a negative value to a value::;> 0 V and then in the opposite
direction towards the starting negative bias. The characteristics
revealed the channel depletion and barrier accumulation regions. The
C- V characteristics in the depletion region yielded a negligible
hysteresis for both A1203- and Zr02-structures. Threshold voltage
Vth is commonly used to evaluate defect charges in GaN-based MOS
structures. However, an increase in Vth with increased lnaxiinUIn
value of the swept bias voltage Vmax was observed. The A1203- and
Zr02-structures exhibited an increase Ll. Vth = 1.6 and 1.3 V,
respectively, for Vmax changing from 0 V to 9 (7) V. This indicates a
difference in the trapped charge of ~ X 1012 cm-2. The C- V
characteristics in the acculnulation region show an increase of the
capacitance with bias voltage, which is more pronounced for the
AI203-structures. Steeper dC/dV indicates a lower density of
interface states [2]. However, other effects need to be considered also,
such as the spill-over (reduction of the effective barrier thickness due
to charge redistribution) and vertical current leakage. Telnperature
dependent C-G- V measurements show different behavior for the
A1203- and Zr02-structures in the depletion and accumulation
regions. While the Al203-structures exhibited a positive threshold
voltage shift with temperature, the Zr02-structures showed a negative
shift. This indicates different charges in the structures, i.e. the
negative vs. positive. Additionally, the Al203-structures exhibited a
negligible conductance increase in the accumulation region. However,
a relatively high conductance, which increased with temperature, was
found on the Zr02-structures. This can be explained considering a
high density of fixed positive charge in the Zr02 insulator and vertical
leakage current. The static I-V measurements support this assumption
(trap assisted leakage). One should consider the band gap difference
between Zr02 (5.8 eV) and AI203 ~ 7 eV) in comparison with that
of AIGaN ~ 4 eV). The work has been supported by the Slovak Grant
Agencies VEGA (Grant Nos. 2/0147/11 and 2/0105/13) and APVV
(Grant Nos. 0301-10 and 0367-11).
DP3.29
Optimization of Field Plate Structure for Enhancing Power
Gain of GaN-Based HEMTs. Zhang Kai, Zhao ShengLei, Cao
MengYi, Zhang JinCheng, Ma XiaoHua and Hao Vue; Key Laboratory
of Wide Band Gap Semiconductor Materials and Devices, School of
Microelectronics, Xidian University, Xi'an, Shannxi, China.
Field plate (FP) structures have been experimentally and
theoretically demonstrated to be effective in enhancement of the
breakdown voltage and suppression of dc-RF dispersion in GaN based
devices. However, few reports on FP design optilnization for
ilnproving frequency perforrnance are available, despite the traditional
source FP design has been frequently reported to induce an increse of
3dB in power gain [1]. In the article, influence of the dielectric
thickness under the traditional source FP on the frequency
characteristics is investigated for the first tilne. Moreover, a novel
composite field plate structure is proposed as an improvement over
the conventional FP techniques to enhance frequency performance in
GaN-based HEMTs. The device design is performed using device
simulator Silvaco "ATLAS". Parameters for frequency response
silnulation are carefully extracted fronl in-house 100 Jun AIGaN/GaN
HEMTs by using the standard small signal extraction method. 1.2 dB
higher power gain at 10GHz is obtained once a source FP is placed on
the second-layer 600nm-thickness SiN dielectric. Interestingly, when
the SiN thickness t is reduced to zero, the maximum power gain (4.2
dB higher) is achieved in cOInparison to HEMTs without source FP.
We, thus, develop a novel FP structure which is comprised of a
dramatically shortened gate FP and a source-connected FP featuring
the same photolithography mask as gate electrode. In the FP design,
the distance between source FP and gate FP (Dis) is determined to
significantly influence both breakdown characteristics and sInall single
gain characteristics. It is found that a shorter Dis, a higher power
gain. We believe that this improvement on gain can be attributed to
the fact that the reduction in Cgd leads to better isolation between
input and output ports, thereby greatly ilnproved the power gain.
Besides, for the used device structure, with Dis= 0.25 Jun, the electric
field distribution of source FP HEMTs closely resembles that of
conventional T-gate FP HEMTs with the same effective FP
length. This indicates that breakdown performance suffers no
degradation. We believe that gain iInproveinent should be partially
due to the minimi:z;ation of parasitic capacitance added by gate FP
and partially due to shielding effect introduced by source FP.
Therefore, the tradeoff characteristics between breakdown and
frequency response could be achieved by using the proposed FP
sturcture, which shows great potential for high frequency high power
application. [1] Ando Y, Wakejima A, Okamoto Y, Nakayama T, Ota
K, Yamanoguchi K, Murase Y, Kasahara K, Matsunaga K, Inoue T,
Miyamoto H, and Miyamoto H 2005 IEDM Tech. Dig. 585.
DP3.30
Magnetotransport Properties of the Two-Dimensional
Electron Gas in High Equivalent Al Composition
AIGaN/GaN Heterostructures Using AIN/GaN Superlattice
as a Barrier. Ning Tang
'
, Sidong Liu
'
, Xuqiang Shen
2
, Junxi
Duan
1
, Fangchao LuI, T. Ide
2
, M. Shilnizu
2
, Weikun Ge
1
,3 and Bo
Shen
1
; IState Key Laboratory for Artificial Microstructure and
Mesoscopic Physics, School of Physics, Peking University, Beijing,
China; 2 Advanced Power Electronics Research Center, National
Institute of Advanced Industrial Science and Technology (AIST),
Tsukuba, Japan; 3Departlnent of Physics, Tsinghua University,
Beijing, China.
Magnetotransport properties of the two-dimensional electron gas
(2DEG) in high equivalent Al composition AIGaN/GaN
heterostructures using AIN/ GaN superlattice as a barrier have been
studied at low temperatures and high magnetic fields. Well resolved
Shubnikov-de Haas oscillations were observed, indicating excellent
quality of the quasi-AIGaN/GaN heterostructures. It is measured that
the energy separation between the two subbands in the GaN
triangular quantuln well can be as large as 180.5 lneV, depicting
strong quantum confinement at the heterointerface. The strong
quantum confinement results in a high 2DEG density of 2*10 13cm-2.
275
The persistent photoconductivity investigation also indicates that the
superlattice barrier layer has a low density of impurities/defects. It is
believed that the AIN/ GaN sllperlattice, instead of high Al
composition alloy AIGaN layer, could greatly improve the device
performance.
DP3.31
Study of Wafer Curvature of AIGaN/GaN Electron Device
Structure on 8-Inch-Diallleter Si Substrate Using
Metal-Organic Chelllical Vapor Deposition \MOCVD).
Akinori Ubukata", Yuya Yamaoka", Yoshiki Yano , Toshiya Tabuchi"
and Koh Matsurnoto
2
; ITaiyo Nippon Sanso Corporation, Tsukuba,
Japan; 2 TN EMC Ltd., Tama, Japan.
AIGaN/GaN high electron mobility transistors (HEMTs) on large
diarnctcr silicon substrates arc very prolnising owing to the low cost.
A lot of work has been devoted to irnprovc the pcrforrn3ncc of HEMTs
grown on Si to widen its applications. However, it is important to
realize devices using large-diameter substrates in a multiwafer reactor
for mass production, since GaN epitaxial wafers with a large diameter
enable us to realize large devices and they can soon be applied to
conventional manufacture lines for GaAs or Si devices. Here, one of
issues encountered in the growth on a large diameter silicon substrate
is the control of wafer curvature during and after the growth run.
Wafer curvature is determined by the thermal effect and the inelastic
strain, which is caused not only by lattice rnisrnatch but also by other
various factors such as growth conditions. In this study, we investigate
the effect of wafer curvature on the growth parameters and
dependence of structure. Device structure was grown on 8-inch Si
(111) substrates in a multiwafer (6 x 8 inch) MOCVD system (Taiyo
Nippon Sanso, UR26K). The epitaxial structure consists of an AIN
nucleation layer, 240nm Ala.5Gao.5N, 2.4",m AIN/AIGaN strained
layer superlattice (SLS), 650nm GaN, 1nm AIN and 25nm-thick
nondoped Alo.25Gao.75N barrier. During the growth of the top AIGaN
barrier, a mixture of N 2 and H 2 was used as a carrier gas. The
curvature during the growth was Ineasured using a curvature rnonitor
employing laser reflection, which was installed on the top lid of the
reactor. The layer-by-layer wafer curvature was calculated using
Stoney's model. It shows a good agreement with the obtained in-situ
data. In cornparison to experirnental curvature with different
structures, it is found that the degree of epitaxial inelastic strain in
SLS is almost one order larger than that in other bulk layers, which is
possibly the result from nucleation grain size, grain boundaries. The
experimentally obtained magnitude of wafer bowing at room
ternperature was approxirnately 30 p,rn for 3.7 Jun thick layer. No
cracks were observed on the surface, and the sheet carrier density and
Hall mobility were 1.0 x 10"
3
cm-2 and 1680 cm
2
/Vs, respectively.
DP3.32
Effect of In-situ Relllote Plasllla Pretreatlllent on Device
Characteristics of AIGaN/GaN MOSHFET with Hf02
Dielectrics for Power Device Ppplication. Bongmook Lee,
Young-Hwan Choi, Jinwoo Kim, Alex Q. Huang and Veena Misra;
Electrical and COlnputer Engineering, North Carolina State
University, Raleigh, North Carolina.
High electron mobility transistors (HEMT) based on GaN/ AIGaN
heterostructures are promising candidates for high-power and high
frequency device applications due to its superior rnaterial properties.
However, high gate leakage current and AC-DC dispersion in drain
current should be overcome to achieve better performance.
Incorporation of gate dielectric under the gate could suppress the high
leakage current but the quality of dielectric or interface should be
carefully optilnized in order to rninirnize VT instability, AC-DC
dispersion, and early breakdown phenomenon. Therefore a thorough
understanding of the interface between dielectric and AIGaN layer as
well as a suitable surface treatment is critical for further enhancing
device performance. In this work, the effect of in-situ remote plasma
pre-treatrnent prior to the high-k Hf02 gate dielectric deposition on
device electrical and off-state stress characteristics is studied on
AIGaN/GaN power metal-oxide-semiconductor (MOS) HFETs. It was
observed that both device subthreshold and gate leakage current
characteristics are improved for the in-situ plasma treated sample.
Moreover, slight reduction in on-resistance was also obtained with
remote plasma treatment. It was also found that the remote plasma
treatment greatly suppress the positive threshold voltage (VT) shift
during DC off- stress (Vg = -6V while Vd changes from 20V to 100V)
resulting that only O.2V shift in VT is observed with in-situ plaslna
treated sarnple after lOOV drain bias stress whereas 1.2V shift in VT
is obtained without plasma treated sample. Finally, the effectiveness
of passivation of surface states by plasma treatment was analyzed
with pulse measurements. The dynamic current response of
AIGaN/GaN HEMT devices to gate voltage pulses (gate-lag) was
characterized and the result suggests that in-situ remote plasma
treated Hf02 provides more effective passivation compared to only
Hf02 dielectric without remote plasma treatment.
DP3.33
Barrier Layer Thickness Optilllization by Elilllinating Surface
Mobile Holes in AIGaN/GaN Heterojunction. Di Meng", Cheng
P. Wen
l
, Shuxun Lin
l
, Maojun Wang
l
, Yilong Hao
l
, Kei M. Lau
2
and Wengang Wu
l
; IInstitute of Microelectronics, Peking University,
Beijing, China; 2Department of Electrical and Electronic Engineering,
HKUST, Hong Kong, China.
In this article, based on polarization and energy band theory, we
present a model describing the nature of induced,
positive/negative charge pairs in AIGaN/GaN heterojunction. We
believe there are mobile holes on the top surface of AIGaN barrier
layer when the thickness of the layer exceeds a certain value. The
modcl was verified by a simple structure with only Ti/ AI/Ni/ Au alloy
electrodes. It contained an outer alloy ring and an inner alloy circle on
an isolated mesa. The outer electrode had larger contact area. The
current between the two concentric electrodes was measured with one
electrode grounded and the other applied a sweep voltage till
saturation occurred. Direction dependency of the saturation currents
between the two concentric, unequal size alloy electrodes was
observed, implying that the simple concentric Ti/ AI/Ni/Au alloy
electrodes structure is not a simple, passive circuit element. Then, a
well-controlled etching process was introduced. Through this process,
we can etch down the AIGaN barrier layer by approximately 2.4 Ji per
cycle. The direction dependency of the saturation currents
disappeared after nine cycles of etching treatment. Conventional
semiconductor models find difficulty in explaining these phenomena.
Yet if we take the above rnentioned surface rnobile hole into
consideration, all results can be easily explained. In fact, the ohmic
contacts for electrons (Ti/ AI/Ni/ Au alloy electrodes) are basically
Schottky contacts for positive charges (surface mobile holes). As a
result of the positive-negative polarization induced charge pairs nature
of the polar serniconductor, the loss of any surface rnobile positive
charges must be accompanied by the loss of equal number of negative
channel electrons. Loss of surface mobile holes through a forward
biased electrode will lead to lower saturation current density adjacent
to that electrode, causing the saturation current flowing between two
concentric, unequal size ohrnic contacts to becorne source electrode
periphery, or direction dependent. And this direction dependency of
the saturation currents will disappear when surface mobile holes are
eliminated by reducing the barrier layer to (or less than) the optimum
thickness. The Inethod of barrier layer thickness optirnization and this
new model can provide guidance to AIGaN/GaN HFET epitaxial
material growth and processing technologies.
DP3.34
Process Design for Illlproved Dialllond-Capped GaN HEMT
Devices. Travis Anderson, Andrew D. Koehler, Marko J. Tadjer,
Karl D. Hobart, Tatyana 1. Feygelson, Jennifer K. Hite, Brad B. Pate,
Francis .T. Kub and Charles R. Eddy; Naval Research Laboratory,
Washington, District of Columbia.
Diamond has been proposed as an integrated heat sink layer for
gallium nitride (GaN) high electron mobility transistors (HEMTs),
but has experienced limited success due to the harsh deposition
conditions and lilnited salnple size. We have previously reported
irnproved electrical perforrnance and a 20% reduction in self-heating
with a "diamond-before-gate" approach, which simplifies process
integration by depositing NCD on top of a thin passivation layer but
before the thermally sensitive Schottky gate. A significant drawback to
this approach is that the passivation layer acts as a therrnal insulator
between the hottest part of the device and the heat spreading layer.
In further experiments, we have addressed and optimi7:ed critical steps
that affect the reliability of this process, focusing on the diamond
nucleation and initial growth, diamond etching, and gate opening
steps. Irnprovernents in these steps have enabled the direct deposition
of diamond on the AIGaN/GaN surface, reduced both micromasking
and plasma damage to the device, and developed a sacrificial gate
process to improve scalability and yield. The stress and composition
of each layer has proven critical to the reliability of the process. To
better understand this effect, the ternperature dependence of the fiIrn
stress and composition in the structure was investigated. The SiNx
passivation/sacrificial layer is particularly prone to changes in the film
properties as it is heated in the diamond growth process. As a more
reliable solution, we have developed a sacrificial gate after diamond
process, where the gate "recess" is forrned as a dielectric pillar before
diamond growth, which is then realigned and removed prior to gate
metal deposition. The benefits of such an optimized process include
having diamond in contact with the hottest part of the device, no
dalnage to the gate area, and irnproved electrical characteristics in
addition to the established reduction in channel ternperature.
DP3.35
Effects of Access Series Resistance and other Nonidealities on
DLTS and Adlllittance Spectra of AIGaN/GaN HEMT
Structures Alexander Y Polyakov", Nikolay B Smirnov", Stephen J
Pearton
2
, In-Hwan Lee
3
, Fan Ren
5
, Cheol-Koo Hahn
5
, Wayne J
276
Johnson
G
, Wantae Lim
7
; lInstitute of Rare Metals, Moscow, Russian
Federation; 2Department Materials Science Engineering, University of
Florida, Gainesville, Florida; 3School of Advanced Materials
Engineering and Research Center for Advanced Materials
Development, Chonbuk National University, Jeonju, Korea, Republic
of; 4Department of Chemical Engineering, University of Florida,
Gainesville, Florida; 5Korea Electronics Technology Institute,
Seongnarn, Korea, Republic of; 6Kopin Corporation, Taunton,
Massachusetts; 7 GaN Power Research Group, Samsung LED, Suwon,
Korea, Republic of.
Knowledge of the spectra of deep traps in the buffer and at the
interface of AIGaN/GaN HEMTs is essential for understanding device
performance. In principle, these data can be obtained from DLTS and
admittance spectra measurements with correctly chosen bias and
pulse voltages. The standard problem with thin films DLTS
rneasurernents on insulating substrate is in that case the series
resistance that distorts the capacitance and can change the
capacitance transient sign at IMH7: probing signal as in standard
DLTS. The common way to circumvent this problem is to use
concentric Schottky and ohmic contacts geometry with a short
distance between the Schottky diode and ohrnic contact ring.
However, when dealing with semi-insulating buffers one commonly
observes that capacitance-frequency characteristics that roll-off at
frequencies higher than 1 MHz at OV, when the 2DEG conduction is
high, are shifted to much lower roll-off frequencies with increased
reverse bias depleting the 2DEG. As a result the series resistance
effects kick-in giving rise to hole-trap-like signal in DLTS. Decreasing
the diode diameter and the Schottky-ohmic contact spacing helps, but
has obvious limitations. We find that the best option is the
multifinger HEMT arrangement in real transistors, but even here, at
high ternperatures where the 2DEG rnobility decreases, quasi-hole
traps signals are often observed. The other problem in AlGaN/GaN,
AIGaN/AIN/GaN HEMTs is the presence of interfacial acceptor traps
that can recharge under bias and after illumination and shift the C- V
characteristic along the voltage axis. The pararneters of such traps can
be deterrnined, under certain conditions, by so called reverse DLTS
technique or by optical spectra measurements. Activation energies
obtained in admittance spectra measured during heating up after
illumination are shown to also be close to the energy of these traps.
SESSION D5: Novel Electronic Concepts
Chair: Shyh Chaing Shen and Douglas Yoder
Wednesday Afternoon, August 28, 2013
Chesapeake 4-6
3:00 PM D5,01
Selective Acoustic Mode Emission from a GaN-Based
Two-Dimensional Electron Gas. Lei Shao
'
, Meng Zhang
2
,
Animesh Banerjee
2
, Pallab K. Bhattacharya
2
and Kevin P. Pipe
'
,2;
IMechanical Engineering, University of Michigan, Ann Arbor,
Michigan; 2Electrical Engineering and COInputer Science, University
of Michigan, Ann Arbor, Michigan.
Topic: New Materials and New Device Concepts GaN-based
semiconductors offer many advantages for high-speed and high-power
devices. In addition to wide bandgap and high rnobility, GaN has a
polari7:ed crystal structure owing to strong spontaneous and
piezoelectric contributions that promote 2DEG formation at
GaN-based interfaces. The modulation of carrier density in a
GaN-based 2DEG offers a means for the generation and controlled
eInission of acoustic energy through dynaInic screening of the
pie7:oelectric field. Experimental evidence for this coupling has
recently been measured in the form of coherent phonon generation [1]
and surface acoustic wave (SAW) emission [2] from GaN-based
HEMTs under typical operating conditions. 2DEGs offer several
unique features for acoustic ernission cOInpared to traditional
IDT-based SAW emitters. First, their buried two-dimensional
geometry enables acoustic transduction to occur at a specifically
defined depth, allowing one to engineer efficient coupling to specific
Inodes which have strong intensity at that depth. Second, both the
built-in pie7:oelectric field and dynamic carrier screening occur over
very short 10 nanometer) distances and are uniformly oriented with
respect to the crystal axes, enabling high-speed and high-efficiency
transduction. Third, the ability to provide either traditional bulk
piezoelectric transduction or 2DEG transduction depending whether
the 2DEG is depleted or present provides the ability to selectively
transduce different acoustic modes. In this work we provide a detailed
study of acoustic transduction by 2DEG modulation in GaN-based
materials. We use a reflective optical probe at near normal incidence
to the 2DEG active region and detect acoustic ernission through the
effect, providing a full picture of the emitted spectrum. We
find four prominent emission peaks corresponding to Rayleigh (R),
Love (L), and 1st and 2nd pseudo-bulk modes (PBl and PB2), which
propagate with different polarizations and at different depths within
the epitaxial layer structure. When the device is rnodulated near its
bias point of maximum transconductance, maximum time variation of
the 2DEG carrier density occurs, and Rand L modes (which are
tightly confined to the surface) are strongly ernitted while PI31 and
PB2 modes are weak. When the device DC bias is moved away from
this point, the modulated voltage drop no longer primarily occurs in
the 2DEG, and PBl and PB2 modes become strongly emitted while R
and L modes weaken. We also find that n. and L modes shift to higher
frequencies as pinch-off occurs and the 2DEG channel length shrinks.
In conclusion, we find that a three-terminal 2DEG device is able to
selectively turn on or off the emission of different acoustic modes
based on applied bias conditions. This switchable source functionality
is unique to the acoustic coupling provided by a GaN 2DEG. ISong et
a!., APL 83, 1023 (2003) 2Shao et a!., APL 99, 243507 (2011)
3:15 PM D5.02
Ferromagnetism and Magneto-Transport in Gd-Doped
AlN-GaN Two-Dimensional Electron Gases. Zihao Yang
'
,
Tholnas F. Kent
2
, Hyungyu Jin
3
, Jing Yang
2
and Roberto C.
Myers
l
,2; lDepartment of Electrical and Computer Engineering, The
Ohio State University, Columbus, Ohio; 2Department of Material
Science and Engineering, The Ohio State University, Columbus, Ohio;
3Department of Mechanical and Aerospace Engineering, The Ohio
State University, Colurnbus, Ohio.
The III-Nitride family semiconductors are good host materials for the
rare earth element gadolinium (Gd) because of its high solubility
(dilute doping regime) and its capability of forming cubic GdN in
wurtzite GaNIl] (heavy doping regime). Further, Gd
3
+ contains 7
unpaired f-electron spins that open the possibility of engineering
magnetism into Nitride semiconductors. In particular, in the
ultra-dilute doping regiIne an anolnalous ferroInagnetic phase with a
Curie temperature (Tc ) above room temperature has been reported
by multiple groups, with the magnetism being thought to arise from
crystallographic point or line defects. Here we examine the possibility
of coupling between the anomalous ferromagnetic phase and
conduction band electrons in GaN. To exaInine this, we present
magneto-transport and magnetometry measurements on GaN and
AIN two dimensional electron gas (2DEG) heterostructures doped
with Gd. These structures are grown by plasma assisted molecular
beam epitaxy on 6H-SiC, where a <I-doped layer of Gd (OML, 0.2ML,
O.4ML and 2.4ML equivalent) is introduced at the expected position
of the 2DEG (O.4nm from the GaN/AIN interface). The structural,
magnetic and electrical properties are characterized by a variety of
complementary methods: atomic force microscopy (AFM), high
resolution X-ray diffractolnetry (XRD), superconducting quanturn
interference device Inagnetolnetry (SQUID), and variable telnperature
magneto-transport measurement. Doping with Gd (0.2ML and
O.4ML) is observed to induce a ferromagnetic phase with TC above
room temperature, with a preferred out of plane easy axis and a
saturation Inagnetization that decreases with Gd doping, silnilar to
earlier reports of anomalous ferromagnetism in bulk Gd:GaN. The
lowest doped sample (0.2ML) is observed to exhibit a magnetic
moment of at 5K revealing that the Gd ions (7PB) cannot
account for the magnetization. We will present detailed measurements
and analysis of Inagneto-resistance and anolnalous Hall effect
measurements revealing the coupling or lack of coupling between the
defect-mediated ferromagnetic phases and the conduction band
electrons in the interface 2DEG. The observed negative
magnetoresistance in all samples suggests the presence of
electron-electron interaction and weak localization at the AIN-GaN
interface. [1] T.F. Kent et. a!., Appl. Phys. lett. 100, 152111 (2012)
3:30 PM D5.03
Lattice Location Experiments of Mg in GaN and AlN:
Implanted Mg Occupies the Octahedral Site.
Ligia M. Amorim
l
, Stefan Decoster
2
, Ulrich Wahl
l
, Lino M. Pereira
l
,
Joao G. Correia
2
, Daniel Silva
2
,3, Kristiaan Temst
l
and Andre
Vantomme
l
; lphysics and Astronomy, Instituut voor Kern- en
Stralingsfysica, Leuven, Flanders, Belgium; 2Instituto Tecnol6gico e
Nuclear, Sacaveln, Portugal; 3Universidade do Porto, Porto, Portugal.
Mg is the p-type dopant most commonly used in the group-III
nitrides. However it only acts as an acceptor if it substitutes the
cation, whereas in other sites it is inactive or might even result in
self-cornpensation. So far, it has been difficult to investigate the
possible lattice sites of Mg in the nitrides using, e.g. EXAFS or ion
beam methods. We recently succeeded to perform Emission
channeling[l] experiments where we implanted the short-lived isotope
27Mg (tl/2=9.5min) at a fluence of lOE11 atoms.cm:2 into GaN and
AIN single-crystalline thin films using the ISOLDE-CERN facility. The
beta particles emitted during the decay of the 27Mg were recorded
with a 2D-detector[l] and by means of fitting their angular-dependent
emission patterns using simulations for different sites, we were able to
perform direct lattice location of Mg with a precision down to O.IA.
Irnlnediately after ilnplantation, the rnajority of the Mg was found in
the cation site both in GaN and AIN. Surprisingly, however, around
277
20% of Mg occupied the octahedral interstitial site. After annealing at
600C, the RT-implanted GaN octahedral fraction of Mg is reduced
while the Ga substitutional fraction further increases. However,
following implantation above 600C, the octahedral fraction of Mg was
converted to substitutional in both materials. For AIN, a similar
study was repeated, following the implantation of 10E15 26Mg.cm:2
(stable), in order to investigate the fluence range relevant when using
Mg as an electrical dopant. This yielded essentially the saIne olltcornc.
The temperature range where the lattice site changes of Mg occurred
indicate an activation energy of 1.4-2.5eV for the migration of
interstitial Mg. From these results, one can infer that the thermal
trcatrncnt required to activate the p-type conduction of the Mg doped
nitrides, which is cornrnonly associated with the rClnoval of H, also
results in the re-incorporation of interstitial Mg in the cation sites.
We can also determine from among the several Mg defects suggested
by first principle calculations [2-4], which are consistent with the
lattice sites in which Mg was derived frorn our data. Previous work on
heavier group-II impurities lattice location in GaN and AIN found no
evidences of interstitial Ca or Sr[5]. On the other hand light group-I
impurities, Na and Li, were found in octahedral sites of GaN and
AIN[6]. And first experiments regarding the lattice site of short-lived
llI3e(14s) in GaN indicate that a large interstitial fraction is also
found for this light group-II impurity. [1] U. Wahl et al. , Nucl. Instr.
and Methods in Phys. Res. B 138 (1998) 744 [2] C. G. Van de Walle,
and .l. Neugebauer, .l. Appl. Phys. 95 (2004) 3851 [3] C. G. Van de
Walle, C. Stampfl, and J. Neugebauer, J. Crys. Growth 189 (1998)
505 [4] Y. Zhang, W. Liu, and H. Niu, Phys. Rev. 13 77 (2008) 035201
[5] B. De Vries et aI., J. Appl. Phys. 100 (2006) 023531 [6] C. Ronning
et aI., Journal of Applied Physics 87, 2149 (2000)
3:45 PM D5.04
InGaN/GaN Multiple Quantmll Well Solar Cells Grown by
MOVPE with Extended Spectral Response, Anna Mukhtarova",
Sirona Valdueha-Felipl, Louis Grenet
2
, Christophe Durand
1
, Eva
Monroy" and Joel Eymery"; 1 CEA-Grenoble, Grenoble, France;
2CEA-Liten, Grenoble, France.
InGaN alloys have been proposed for photovoltaic applications [I]
thanks to their high absorption coefficients and the possibility to tune
their band gap in the whole solar spectrurn. In our previous work
InO.llGaO.89N/GaN (1.3 IlIn / 7.8 nm) multiple quantum wells
(MQWs) have been grown on sapphire substrate by metal-organic
vapor phase epitaxy (MOVPE). Solar cells consisting of a p-i-n
structure with 30 QWs in the active region were fabricated and they
revealed a rnaxirnurn external quanturn efficiency (EQE) equal to 38%
at 380 nm, an open-circuit voltage Voc = 2.01 V and short-circuit
current Jsc = 0.23 mA/cm2 under 1 sun of AM1.5G illumination,
leading to a fill-factor FF = 55% and a conversion efficiency of 0.26%
[2-3]. In this work we present the design optimbation of the InGaN
active region in terrns of MQW nurnber, In-content and well thickness.
When increasing the number of QWs to 40, the spectral response
red-shifts to 410 nm, as confirmed by its photoluminescence emission
wavelength corresponding to 13% of In composition. Additionally,
decreasing the growth temperature leads to an enhanced In
incorporation in the MQWs reaching 16% of In content in the
quantum wells while keeping the structure biaxially strained on GaN.
These photovoltaic devices show a spectral cutoff at 455 nm, together
with a photocurrent tail in the green to red spectral region, consistent
with the absorption observed in this wavelength range. The increase
of In-content leads to a considerable irnprovernent of the J sc value (by
more than a factor of 5) with a slightly decrease of Voc, resulting in a
higher electrical power of the solar cell. Dark measurements exhibit a
reduction of the leakage current by three orders of magnitude for
devices with higher In-content and higher thicknesses of QWs,
achieving 10-3 rnAjcrn2 after optirnizing the active region. In
summary, we demonstrate an enhancement of the electrical
performance of the devices with spectral response extending out to
the green spectral range by the improvement of the InGaN active
region design. [1] E. Matioli et al. Appl. Phys. Lett. 98, 021102
(2011). [2] A. Mukhtarova, et al. Phys. Stat. Sol. C, No. 10, 350
(2013). [3] S. Valdueza-Felip, et al. Jpn. J. Appl. Phys. 52 (2013)
4:00 PM D5.05
Pyroelectric Control of Rashba Spin-Split States in
GaN/lnN/GaN Topological Insulator, Parijat Sengupta, Rajib
Rahman, Yaohua Tan and Gerhard Klimeck; Electrical and Computer
Engineering, Purdue University, West Lafayette, Indiana.
Topological insulators (TI) are a new state of quanturn rnatter that
possess metal-like surface states and behave as insulators in bulk.
Bi2Te3, Bi2Se3 are some common examples of TIs. TI surface states
are a manifestation of the strong spin-orbit coupling in these
rnaterials. Strong spin-orbit coupling which leads to band inversion in
bulk is the necessary requirement for creation of TI states. Apart from
spin-orbit coupling, electric field and lattice strain can also be used to
invert the band structure. 111-V nitrides in wurtzite phase possess a
very strong internal electric field. This electric field due to intrinsic
spontaneous and piezoelectric polarization (in strained nitrides) is
sufficient to invert the band-ordering of a narrow-gap material such as
wurtzite InN. In this work, it is dernonstrated that a TI state can
exist when a thin-film of InN is sandwiched between GaN layers. The
combined piezoelectric and spontaneous polarization field in InN
inverts the band-ordering at the r point. For a certain quantum well
thickness the inversion of bands happen at a threshold value of the
polarization field. This suggests that tuning the internal polarization
field can allow the control of band inversion. Since the creation of TI
states requires inversion which in turn is polarization-dependent, this
work investigates devices with varying internal fields. Internal fields
are controlled by selecting a facet orientation of the quanturn well
layer. It is irnportant to note that various orientations of the quanturn
well layer will either reduce the spontaneous or
polarization. The choice of the facet is therefore adopted by
determining the dominant polarihation mechanism. Ab-initio
calculations were perforrned to obtain the conduction band effective
mass at r and the direct band-gap for bulk InN. These values were
inserted in to an 8-band k.p Hamiltonian including strain and the
internal polarization field. Lastly, the work utilizes the spin-polarized
surface states of the GaN/lnN topological insulator. The surface
states are degenerate at r. At a finite k-vector, the Rashba induced
spin-splitting on the surface of this heterostructure is computed for
the two spin states. The splitting under a first-order approximation is
independent of k-vector and corresponds to the internal electric field's
contribution to the Rashba coefficient 0:. Therefore, a pyro-electric
control of spin-polarization coupled to a choice of facet orientation is
accomplished.
SESSION D6: GaN on Silicon Electronic Devices &
Process Innovations
Chair: Ronghua Wang and Tornas Palacios
Thursday Morning, August 29, 2013
Chesapeake 4-6
8:30 AM D6.0!
AlGaN/GaN-on-Si Heterojunction Field Effect Transistor
with Embedded Fast Recovery Diode. Bong-Ryeol Park,
.lung-Yean Lee and Ho-Young Cha; School of Electronic and Electrical
Engineering, Hongik University, Seoul, Korea, Republic of.
AIGaN/GaN-based power devices have received great attention for
use in high efficient power rnanagernent ICs, such as DC-DC
converters and DC-AC inverters in various electronics. An important
issue in use of AlGaN/GaN HFETs is how to manage the reverse
current flow during off-state condition because no reverse recovery
diode is integrated in conventional AIGaN/GaN HFETs. That is, an
external diode needs to be connected in antiparallel with an
AIGaN/GaN transistor to flow the fly-wheeling current. In this study,
we present a novel AIGaN/GaN-on-Si switching transistor in which a
Schottky barrier diode (SBD) is monolithically embedded. The
normally-off transistor was implemented by a recessed AIGaN/GaN
MOSHFET configuration. In order to integrate SI3D, a Schottky
anode was inserted in the region between gate and drain, which was
electrically connected to the source electrode. The thickness of the
recessed AlGaN barrier layer under the gate region was 3 nm and a 30
run Si02 filrn was deposited as the gate oxide layer. A
Si/Ti/ Al/Mo/Au metal stack was used for the ohmic metallization
and a Ni/ Au metal scheme was used for both gate and Schottky
anode contacts. The source-to-gate distance, gate length, and
gate-to-drain distance were 3, 2, and 12 /-Lm, respectively, and the
ernbedded anode contact length was 2 p,rn. The fabricated device
worked as a normally-off switching transistor in forward transistor
operation and as a diode in reverse operation. The gate threshold
voltage was V in the transistor mode whereas the SBD turn-on
voltage was 1.2 V in the reverse conduction mode with the gate
voltage of 0 V. The rnaxirnurn drain current density in forward
operation was mA/mm with the gate voltage of 16 V. The
extracted on-resistance was 2.66 mncm2. An off-state breakdown
voltage of V was achieved for the anode- to-cathode distance of 8
/-Lm. The proposed device is very promising for use in high efficient
rnonolithic converter and inverter ICs; elirninating the need for an
external diode can dramatically reduce the chip si:z;e minimi:z;ing the
parasitic inductance and thus can allow the fast switching operation.
8:45 AM D6.02
Synchrotron-Based X-Ray Photoelectron Spectroscopy
Studies Of AIGaN and GaN Surface Oxide Chemistry,
Matthew Myers"
2
, Anna Podolska
3
,2, Farah L. Khir
3
, Leopold
Silberstein
3
, Tarun Sanders
3
, Brett D. Nener
3
, Murray V. Baker
2
and
Giacinta Parish
3
; lEarth Science and Resource Engineering, CSIRO,
Bentley, Western Australia, Australia; 2School of Chemistry and
Biochemistry, The University of Western Australia, Crawley, Western
Australia, Australia; 3School of Electrical, Electronic and Computer
Engineering, The University of Western Australi, Crawley, Western
Australia, Australia.
278
AIGaN/GaN-based transistors are a potentially robust solution to
Ininiatllriscd and reruate sensing of, for cxarnplc, ions and pH.
Numerous reports on AIGaN/GaN HEMT-based pH sensors have
shown a clear, linear dependence of ungated device response on
solution pH, but are conflicting in terms of the proposed mechanism.
However uncapped (no intentional oxide or GaN cap) AIGaN/GaN
devices arc not pH-sensitive, but anion-selective. To accurately
interpret sensor response, it is important that the surface chemistry of
oxides of AIGaN and GaN (native or formed by thermal or plasma
oxidation) with respect to various ions and varying pH is well
understood. We have undertaken X-ray Photoelectron Spectroscopy
(XPS) rncasurClncnts at the Australian Synchrotron to explore
differences in oxide for various cap layers and chemical exposure by
identifying oxygen and impurity levels in the near surface.
Synchrotron radiation significantly enhances the analytical sensitivity
of XPS, critical for experirnents close to the detection lirnit (i.e., 1
atomic%). Firstly, AIGaN/GaN heterostructures were compared with
two different compositions ( XAI = 0.15, 0.35) and three types of
capping (GaN, SixNy , uncapped), with and without 1) exposure to
KOH, NaCI, HCI and H 2S04 and 2) thermal annealing. The results
show distinct differences in native oxide layer depending on capping
and chemical exposure. The oxidation of the surface appears
dependent upon Ga concentration, but independent of Al
concentration. Additionally, the presence of Al at the surface serves to
stabilise the surface oxide layer with respect to chemical etching. A
second round of experirnents has recently been undertaken to COlnpare
GaN and AIGaN/GaN wafers with different oxidation (native oxide,
thermal, and sputtered GaxOy ) again with various chemical
treatments. Analysis of the high volume of data is currently underway.
We will present the combined results of both studies as a
cornprehensive, novel study into surface chelnistry of AIGaN and GaN.
9:00 AM D6.03
AIGaN/GaN HEMTs on 3" Si (111) with Regrown Ohmic
Contacts by RF-MBE. Satyaki Ganguly, Jai Verma, 130 Song, Huili
(. Xing and Debdeep Jena; Electrical Engineering. University of Notre
Darne, Notre Darne, Indiana.
Large-area and low-cost Si wafers have proven attractive as substrates
for GaN power electronics. Although the large lattice and thermal
mismatch makes the epitaxy of III-Nitrides on Si substrates
challenging, exciting device perforrnances have been reported recently
where both iT and 1max exceeds 120GH7, with DC output current
density To improve the device performance further
with ultra-scaled device geometries, it is highly desirable to minimize
contact resistance since it generally dorninates the total parasitic
resistance. In this work we report the MI3E regrown ohlnic contacts
with R, the best reported for metal polar
HEMTs. The growth and device characterization of AIGaN HEMTs
grown on Si (111) by RF-MBE is presented as follows.
AIGaNHEMTsGrowthandCharacterization : The M13E growth
of AIGaN HEMTs initiates with an AIN nucleation layer primarily to
prevent the 'melt back etching' problem and also to reduce the
thermally induced tensile stress to avoid cracking. The growth
conditions of the metal-polar Alo.32Gao.6sN (20nm)/GaN
(1.5/un)/ AIN (100nm)/Si (111) samples were properly optimized to
ensure smooth 2D layer by layer growth with a ""0.6nm rms roughness
over 2/lm x 2/lm AFM scans. All these HEMT structures were capped
with a 2-nm thin GaN layer and also Al pre-deposition prior to the
AIGaN growth was performed to enhance the 2DEG mobility. The
Hall-effect measurements at RT showed /V.s, 2DEG
charge density X 1O"
3
cm-
2
with The XRD
scan along the (002) direction showed GaN FWHM value of 900
arcsec, one of the best reported for GaN grown by MBE on Si.
HEMTsDeviceCharacteristics : The device fabrication process
initiated with patterning of Si02 mask for n+ GaN ohmic regrowth
by MBE. The pre-regrowth etch depth into the HEMT structure was
",,50 Inn, and regrown n+ GaN wasrv100 nrn with a Si doping level of
X 10
20
em-3. Following regrowth the poly-GaN on top of Si0
2
was lifted off by BHF. Non-alloyed ohmic contact of Ti/ Au
(20/100nm) was deposited. followed by mesa isolation using CIt based
plasma etching. Finally Ni/ Au (40/100 rnn) gate metal stacks were
deposited on this sarnple. FrOln the TLM patterns with HEMT
channel and regrown contacts, R
c
rv 0.11 O.mm and R8hrv4800/sq
were extracted. From the TLM patterns with regrown n+ GaN
channel and contacts. and R", were obtained.
The saturation drain current density of the HEMTs was rneasured to
be 1.13A/mm at Vy,=2V for The Run was extracted to be
1.6 O.mm. The DC transfer characteristics measurements
resulted 9m.,xt= 225mS/mm and Vth = -4V for V d.,=4V. ION/OFF>
10
5
was also measured. These values are very much comparable with
the current GaN HEMTs state of the art. With very low contact
resistance achieved in this work coupled with thinner barrier and
device scaling thus promises attractive DC and RF performances of
GaN HEMTs on Si.
9:15 AM D6.04
Optimization of AIGaN/GaN High Electron Mobility
Heterostructures on Silicon for Low Cost Power Devices
Operating at 40 GHz. Stephanie Rennesson"
2
, Magdalena
Chmielowska
1
, Sebastien Chenot
1
, Yvon Cordier
1
, Francois Lecourt
3
,
Nicolas Defrance
3
, Marie Lesecq3, Virginie Hoel
3
, Etienne Okada
3
and Jean Claude De Jaeger
3
; lCRHEA-CNRS, Valbonne, France;
2
p
hysics, University of Nice Sophia Antipolis, Valbonne, France;
3IEMN, Villeneuve d'Ascq, France.
In this work, we describe the optimbations completed on AIGaN/GaN
high electron rnobility transistor structures (HEMTs) on Silicon in
order to establish an optimum for high frequency Ipower performances
in transistors with 0.25 /lm gate length. The combination of such a
low cost material system with gate sizes accessible to a large number
of fabs and a recess-free process can enable the large scale deployrnent
of high perforrnance RF circuits. With subrnicron gate length, it is
necessary to improve the 2DEG confinement to limit short channel
effects. For this purpose, the insertion of a thin AIN spacer at the
barrierI channel interface is considered, as well as the growth of a
DH-HEMT structure on a 1.5 lun thick AIGaN buffer layer with 5%
Al content. Additionally, the distance d between the gate and the
2DEG has to be reduced in order to keep the aspect ratio Lg/d high
enough (typically larger than 15). Such a ratio necessitates the
reduction of the distance d below 17 nm for a transistor with a gate
length Lg of 250 nIll. Then, we exarnine how to deal with a high sheet
carrier density, an acceptable sheet resistance and a reduced barrier
thickness. The structures are grown by ammonia source MBE on 2 in.
Si(111) highly resistive substrates. They are composed with a GaN
cap with thicknesses varying from 5 nm down to 0.5 nm, an AIGaN
barrier layer (21 nrn, 18 rnn, 14 nrn and 10 nrn thick), 1 nrn of AIN
spacer and the buffer layer. The Al content is kept below 30% in order
to minimize the tensile stress in the barrier, as well as the risk of
degradation during electrical stress. Similar crystal quality and
mobility (2000 cm2/V.s) are achieved for different structures grown
on a 1. 7 rLIn thick GaN buffer. A slight degradation of quality and
mobility (>1700 cm2/V.s) but a noticeable increase of the buffer
resistivity (by more than 2 orders of magnitude) is obtained with the
AIGaN buffer layer. Thanks to the reduction of the cap layer thickness
down to 0.5 rnn, the increase of the sheet resistance is lirnited to 453
Ohms/sq for a 10 rnn thick AIGaN barrier, while it is 337 Ohms/sq
for a 14 nm barrier when grown on GaN buffer and 608 Ohms/sq on
AIGaN. All these considerations as well as output characteristics
behavior of 2 /lm gate length devices allow considering the formers as
the rnost prornising. DC, RF, pulsed and large signal rneasurelnents
have been achieved on 0.25 /lm gate devices. At 40 GH7, and VDS =
15 V, the 14 nm barrier devices produce an output power density of
1.5 W /mm, a power added efficiency of 10 % and a linear power gain
of 5.5 dB. For the 10 nm barrier devices. we observed a slight decrease
of the output power density (1.25 W /nlIn) mainly due to the larger
sheet resistance and the resulting lower current density. This work is
partly supported by the French national research agency under grant
ANR blanc-2010 STARGAN, the pole of competitiveness PEGASE,
the French MOD (Delegation Generale de l'Armement), RENATECH
network and the French Nord-Pas de Calais area.
9:30 AM D6.05
Self-Aligned Gate-Last Enhancement- and Depletion-Mode
AIN/GaN MOSHEMTs on Si with Enhanced RF
Perforlllance. Tongde Huang, Jun Ma, Xing Lu, Zhaojun Liu and
Kei May Lau; Hong Kong University of Sci&Tech, Hong Kong, Hong
Kong.
In this work, we demonstrate self-aligned AIN/GaN MOSHEMTs
fabricated with a gate-last process and investigate the effects of
post-gate annealing on threshold voltage (Vth). In comparison with
previously reported transistors [1, 2], parasitic capacitances (Cgsext
and Cgdext) were significantly reduced in this self-aligned
architecture by inserting a SiNx supporting layer and sidewall
between the gate metal and source/drain contact. The reduction of
parasitic capacitances greatly improved the RF performance. Using
the self-aligned gate-last process we developed for III-nitride devices,
both enhancement- and depletion-mode (E/D-mode) AIN barrier
MOSHEMTs were fabricated on a single chip with 6-nrn atolnic-Iayer
deposited- (ALD) Al203 as gate dielectric. To reali7,e the E-mode
MOSHEMTs, a post-gate annealing at 4000C was performed after
gate metal (Ni/ Au) deposition, which pushed the Vth towards the
positive directionto +0.2 V. Subsequently, D-rnode MOSHEMTs were
fabricated with TilAu as gate electrode, resulting in a Vth around -2
V. The AIN/GaN heterostructure used in this study was similar to
that described in [1, 2]. The E-mode transistor with a gate length of
210 nm shows current gain cutoff frequency (fT) of 39.6 GHz and
rnaxirnurn oscillation frequency (flnax) reaching 39.8 GHz. The
D-mode transistor with a gate length of 170 nm exhibits a IT/fmax of
26/30 GH7,. The Cgsext and Cgdext were significantly reduced by
about one order of magnitude than that in [1, 2]. The relationship
between the post-gate annealing and Vth was also analyzed.
279
Transmission electron microscopy (TEM) images showed no gate
metal sinking by comparing the Al203 thickness before and after
annealing. This was also confirrncd by the capacitance-voltage curves.
The maximum capacitance (Cmax) didn't increase after the
annealing. The shift of Vth is thought to be due to a reduction of
positive fixed charge at the AI203/III-nitride interface. The Vth did
not shift anymore with prolonged post-gate annealing time. [1] T.
Huang, X. Zhu and K. M. Lan, Electron Device Letters, IEEE, vol.
PP, pp. 1-3, 2012. [2] T. Huang, X. Zhu and K. M. Lau, in Solid-State
and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th
International Conference on, 2012, pp. 1-3.
9:45 AM D6.06
GaN Buffer Traps in GaN-on-Si Structure Studied by
Thermally Stimulated Current and Back-Gating
Measurements. Shu Yang
1
, Jianbiao Lu
2
, Sen Huang
1
, Chunhna
Zhou', Baoling Huang
2
and Kevin J. Chen'; 'Electronic and
Cornplltcr Engineering, Hong Kong University of Science and
Technology, Kowloon, Hong Kong; 2 Mechanical Engineering, Hong
Kong University of Science and Technology, Kowloon, Hong Kong.
In GaN-based power HEMTs/MIS-HEMTs implemented on
cost-effective GaN-on-Si platforrn, breakdown voltage and current
collapse are critical issues that need further improvement for
high-voltage power switching applications. It is suggested both
breakdown voltage and current collapse are associated with bulk traps
in GaN buffer, in addition to the surface traps. As a desirable method
to characterize the deep-level traps in high - re.'Jistivity sarnplcs,
thermally stimulated current (TSC) measurements have been
performed on high - resistivity GaN epilayers grown on sapphire with
contact-pairs on the top surface. However, the bulk traps distribution
is usually non-uniform through the GaN epilayers, making it necessary
to pcrforrn TSC rncasurcrncnts using vertical structures. This work
investigates the deep-level traps in GaN buffer, by combination of
TSC and high-voltage back-gating measurements performed on an
AIGaN/GaN-on-Si heterostructure with a lowresistivity Si substrate.
The back-gating IncaSllrcrIlcnt was pcrforrncd with low drain bias and
high substrate bias, to clirninatc the contribution froIn surface traps.
The normali7,ed drain current I D first decreased, followed by a flat
region, then decreased again. The decrease is attributed to the ionized
acceptor traps (negatively-charged) in the GaN buffer that can
partially deplete 2DEG, while the flat region is ascribed to the ionized
donor traps (positively-charged) that can compensate the increasing
negative V sub ' It is suggested that two acceptor traps and one donor
trap dominate the back-gating characteristics. TSC measurement was
conducted on a GaN-on-Si vertical structure, with the ohmic contact
on GaN and [o'WTesistivity Si substrate serving as the electrode-pair.
The GaN-on-Si was illuminated with white light at low temperature,
to fill up/neutralize the traps; then the traps are thermally emptied
when heating up the sample in the dark with various heating rates (3.
The TSC peaks T ='s shifted to high positions with higher (3. The
activation energies of traps Et's are extracted frorrl the Arrhenius plot
of T Tn 4 / (3 1000/ T m' Combined with the back-gating results, E
tl
0.538 eV and E'3 0.747 eV are most likely the activation energies
of two acceptor-like traps which are correlated to carbon-induced trap
and Ga vacancy, respectively; E t2 rv 0.651 eV is the activation energy
of a donor trap that is correlated to point defects.
10:30 AM *D6.07
High-power III-N HFETS on Si Substrates for Millimeter
Wave Applications. Farid Medjdoub, I.E.M.N - CNRS - CSAM,
Villeneuve d'Ascq, France.
Recently, nitride HEMTs on Silicon have been identified as an
attractive candidate for low-frequency power management
applications such as solar power inverters (i.e. DC-to-AC conversion),
compact and switched-mode power supplies, smart electric power
distribution grids, where one attraction is the lower cost from using
large-diameter silicon substrates (up to 8-inch/200mm at present).
Significant industrial and acadernic developrnents are on-going
worldwide to qualify galliurn nitride on silicon (GaN-on-Si) technology
in a range of different voltage ratings, such as 30-600V for IT and
consumer power management and 600-1200V for automotive and
power-switching applications. Furthermore, reliable RF GaN-on-Si
power transistors operating at drain bias as high as 48 V are now
available in the L-band for the defense, communications, cable TV,
and industrial and scientific markets. This reflects the importance and
the interest of the GaN-on-Si platform. Millimeter wave applications
could also benefit from the compatibility of RF GaN-on-Si HEMTs
already available up to 8-inch with well-established Si-based
technologies such as CMOS; which would allow to develop new chips
with higher functionalities and breakthrough performances. Many
challenges need to be overcome to make these types of devices
operating in the K-band and beyond. Major issues are the self-heating
under high bias due to the poor therrnal dissipation of the Si
substrate and the RF losses resulting from a conductive layer at the
epi/sub-interface between the GaN epitaxial structure and the Si
substrate which is related to the Ga diffusion into the Si substrate.
Recently, the improvement of the GaN-on-Si growth quality combined
with the use of ultrathin AI-rich barrier layers in order to rnitigate the
aspect ratio issues when using deep sub-micrometer gate length
allowed the demonstration of high frequency performance above 100
GHz, high power density at 40 GHz and low noise in the Ka band.
These results show that GaN-on-Si devices have an excellent potential
for rnillirneter-wave applications, and will enable low-cost highly
integrated circuits with unprecedented performance.
11:00 AM D6.08
Mobile-Ion Contamination and Its Impact on AIGaNjGaN
MOSHEMTs. Omair I. Saadat and Tomas Palacios; EECS,
Massachusetts Institute of Technology (MIT), Cambridge,
Massachusetts.
Gate dielectrics in GaN-based rnaterial systerns have attracted rnuch
attention as a mean of reducing gate leakage and increasing gate drive
in GaN MOSHEMT structures. However, as of yet, contamination due
to mobile ions such as K+ and Na+ have not been studied in these
devices. Historically, mobile ion contamination in Si02/Si MOS
devices had been identified as a key source of threshold voltage
instability and eliminated by targeted cleaning and the use of
contamination-free processing equipment [1]. In the Si industry,
contamination levels were determined by carrying out bias
temperature stress (BTS) measurements where mobile ions are drifted
by applying a 1 MV/em bias at 200C and looking at the resulting
change in threshold voltage. This abstract presents the first study of
the impact of mobile ion contamination in AIGaN/GaN based
MOSHEMTs and discusses how to eliminate this contamination.
AIGaN/GaN MOSHEMTs and GaN MOS capacitor structures with
20 rnn of Hf02 or 20 rnn of Ah 0
3
were processed. Two different
samples of each kind were processed using either borosilicate or
semiconductor grade quartz glassware. We performed BTS
measurements on all samples under varying bias conditions. Ah03 is
a diffusion barrier for rnobile ions [1] and thus rnobile ion rnovernent
was not seen. In Hf02 based MOSHEMT structures, the negative
shift of V t resulting from mobile ion drift was counterbalanced by
electron injection into the dielectric/ AIGaN interface and the AIGaN
layer [2] and thus the mobile ion concentration was underestimated to
be 1xlQ12 cm-
2
. On the other hand, Hf0
2
/n-GaN structures are not
as prone to electron trapping and thus the true mobile ion
concentration of 1 X10
13
crn-
2
was rneasured. The arnount of fixed
positive charge and the resulting threshold voltage are important
metrics for benchmarking gate dielectrics in AIGaN/GaN
MOS-HEMT structures [3]. Both parameters can be masked by mobile
ion contamination. By changing the polarity of the applied bias
during the TITS rneasurernent frorn positive bias to negative bias, it is
possible to reverse the drift of mobile ions. Therefore, the measured
carrier concentration present in Hf02 / AIGaN/GaN capacitor can
range from 8.2x10'2 down to 5.1x10'2 cm-
2
depending on the BTS
bias condition. Given that the bare AIGaN/GaN heterostructure has a
carrier concentration of 6.5 X 10
12
cm-2, it is clear that the mobile ion
contamination can mask whether Hf02 has positive or negative charge
in this case. The use of borosilicate (pyrex) glassware during device
fabrication is a key source of ion contamination, since it contains 4%
Na20 by weight. Acidic and alkaline solutions used in pre-ALD cleans
can leach sodium from borosilicate glass [4], [5]. By processing in
clean quartz labware, the mobile ion levels were reduced from 1 X 10
13
cm-
2
down to below 1x10
11
cm-
2
, according to BTS measurements
in n-GaN based MOS devices. Acknowledgements: This work has been
partially funded by the ONR Navy DEFINE MURI program,
monitored by Dr. Daniel Green. Fabrication was performed at the
MIT MTL and Harvard CNS facilities. Structures were grown by Dr.
R.. J. Molnar of MIT Lincoln Laboratories. [1] E.H Nicollian and J.R..
I3rews, MOS Physics and Technology, 2003 [2] C. Mizue et ai, .lap. .I
App!. Phys, 50, 021001, 2011 [3] T-H. Hung, App!. Phys. Lett, 102,
072105, 2013 [4] H. K . .lang et ai, J. Vac. Sci. Techno!. A, 18, 2563,
2000 [5] R.D. Long et aI, Appl Phys. Lett., 101, 241606, 2012
11:15 AM D6.09
Correlation of On- Wafer 400V Dynamic Behavior and Trap
Characteristics of GaN-HEMTs. Tadahiro Imada', Daniel
Piedra
2
, Toshihide Kikkawa1 and Tomas Palacios
2
; 1 Fujitsu
Laboratories Ltd., Atsugi, Kanagawa, Japan; 2Massadlusetts Institute
of Technology, Carnbridge, Massachusetts.
GaN power transistors are expected to significantly reduce the losses
of power electronics However, GaN based heterostructure device is
also well known for large defect density which results in the dynarnic
behavior degradation. In this paper, we report the first on-wafer
measurements of the dynamic behavior of GaN-HEMT at 400 V with
direct trap analysis. In addition, we also present a new approach to
correlate the dynamic characteristics of GaN HEMTs with the
rnaterials traps, by developing irnpedance transient characterization
method to GaN Schottky barrier diode (SBD). With this scheme, the
location where trapping phenomena happened can be estimated
280
laterally. Dynamic-on-state behavior was measured as below; voltage
clamping circuit was used in order to obtain accurate on-state drain
voltage of the device, preventing the saturation or inaccuracy of
oscilloscope by drain voltage swing of 400V. Time constants of
dynamic behavior of GaN-HEMT were extracted by Time-Constant
Spectrum Method to after 400 V off-state stress. To characterbe
traps, the impedance trap characterb'jation, including both
capacitance and scrics conductance transicnts, was done using the
comb type SBD in the same die as the AIGaN/GaN-HEMT.
Conductance, in addition to capacitance, was used for characterize
trapping phenomena. Because capacitance change by trapping is small
when on-state was Ineasured duc to largc alnount of 2DEG. On thc
contrary, conductance is proportional to carrier dcnsity even at
on-state as seen in the equation, G=WjL*qa,u, where G is
conductance, W is width, L is length and I-' is mobility of the device.
q is the charge amount of electron. GaN HEMT without any
passivation were fabricated on SiC substrates in MIT, of which gate
width, gate-drain length and threshold voltage were 50 I-'m, 25 I-'m
and -2.4 V respectively. After -5 V stress applied to Schottky
electrode for 1ms to SBD, several DC biases were applied to Schottky
electrode with probing C-V signal of 1 MHz while Ohmic electrode
was groundcd. With different DC biascs, we can indicate where the
traps are located, because lateral depletion behavior can be precisely
monitored by comb-type SBD, which also can reduce frequency
dispersion at 1MHz. Conductance transient measurement was used for
characterizing SBD at 0 V (on-state), which indicates the trap
characteristics of wholc device. Capacitance transient Incasurelnent
was used for that with -2.2 V bias (on-region near threshold), which
shows how trapped electrons behave near the gate. Access region
trapping affects the transient property at -3 V (off-state). In precise
dynamic behavior measurement after 400- Voff-state stress using our
devclopcd on-wafer IneasurClncnt Inethod for GaN-HEMT, donor-like
traps with 0.14 eV activation energy were found. Impedance transient
method using SBD with several biases showed O.lSeV donor-like traps
around the gate, 0.44 eV donor-like traps and 0.49 eV acceptor-like
traps in access rcgion. Correlation of both Incasurelnents indicated
that 0.18 eV donor-like traps arc identified as critical traps for
dynamic behavior which are located adjacent to the gate, which is
coincident with former literatures in this case. In this study,
un-passivated device was used, but this method is proven to be useful
to locate the trap position and activation cncrgy at thc saU1C tilne.
11:30 AM D6.10
Ron Collapse, Breakdown and Degradation of d-mode
MI5-HEMTs Based on GaN on 5i Technology.
Matteo Mcncghini
1
, Davide I3isi
1
, Denis Marcon
2
, Steve Stoffels
2
,
Marlcen van Hove
2
, Tian-Li Wu
2
, Stefaan Decoutere
2
, Gaudenzio
Meneghesso
1
and Enrico Zanoni
1
; IDepartment of Information
Engineering, University of Padova, Padova, Italy; 2 IMEC, Heverlee,
Belgium.
GaN-based MIS-HEMTs grown on silicon arc prolnising devices for
application in the power conversion field, due to the following aspects:
(i) the use of a silicon substrate allows to reduce fabrication costs,
thanks to the availability of large area wafers; (ii) these devices have a
vcry low gate leakage current, thanks to the usc of a dielectric layer
under the gate; this allows to reduce power dissipation in off-state
(thus increasing device efficiency), and to operate the devices with a
large gate voltage swing. Despite the importance of MIS-HEMTs on
silicon, very few data on the trapping and degradation mechanisms of
these dcvices have becn published so far. Thc ailn of this paper is to
present an extensive investigation of the trapping and degradation
mechanisms of GaN-based MIS-HEMTs grown on a 150 mm silicon
substrate. The results of trapping investigation indicate that: (i) the
analy:tied devices may suffer from a dynamic Ron collapse and from a
slight (dynalnic) variation in threshold voltage, as delnonstrated by
pulsed ID- VD and ID- VG characteri7,ation; (ii) Ron collapse is due to
the trapping of electrons in the gate-drain access region, as
demonstrated by measurements carried out on samples with different
gate-drain distances; (iii) Ron-transient investigation, carried out
froIll thc Il'S to the 100 s tilne scalc, delnonstrate the existencc of one
dominant deep level, with activation energy 1.03 0.09 eV; (iv) this
deep level is supposed to be located in the GaN or AIGaN epitaxial
material (as discussed in the paper based on the comparison with
previous literature reports), and to be responsible for both the
dynalnic Ron decrease and for the slight Vth shift Ineasured during
pulsed measurements. To evaluate the robustness of the devices, we
carried out both current-mode (i.e. non-destructive) breakdown
measurements and stress tests in the off-state. The results of
breakdown invcstigation indicated that by biasing the devices in the
off-state (with VG<Vth): (i) at moderate VDS levels drain current
mostly originates from leakage current components; (ii) at moderate
VDS levels, no significant bulk current is detected, indicating that the
double heterostructure effectively confines the carriers in the channel
region; (iii) with increasing VDS level, ID shows a sudden increase,
which is related to two different mechanisms, namely short-channel
effects (if VG is close to Vth), or gate-drain leakage (if VG is
significantly lower than Vth, so that short channel effects are
completely suppressed). Finally, off-state stress tests, carried out with
thc step-stress strategy, delnonstrated that the devices have a very
high robustness (with LGD=2 I-'m they can withstand an off-state
voltage of 260 V without reaching the failure). Failure (which occurs
for voltage levels higher than 260 V) consists in a rapid increase in
leakage current, followed by a permanent degradation. EL and
transicnt investigation indicatc that degradation occurs in proxilnity
of the sharp edges of the drain (i.e. in a high electric field region), and
that the dynamic RON collapse significantly increases after stress,
possibly due to the increase in trap density.
11:45 AM D6.11
Enhancement in AIGaN/GaN HEMT Performance with AIN
Passivation Layers Grown at 500C by Atomic Layer
Epitaxy. Andrew D. Koehler, Travis .T. Anderson, Neeraj Nepal,
Marko .T. Tadjer, Karl D. Hobart, Charles R. Eddy and Francis .T.
Kub; Power Electronics, Naval Research Laboratory, Washington,
District of Columbia.
AIGaN/GaN high electron mobility transistors (HEMTs) are
appealing for high power, high frequency and high power switching
applications, however trapped charge in the access region between the
gate and drain, depleting the two-dimensional electron gas (2DEG),
limits performance by increasing the dynamic on-resistance
(RON,DYN). AIN passivation capping layers, 4 nm thick, formed by
atolnic layer epitaxy (ALE) at tClnperatures up to 500C arc
implemented and qualified against standard plasma-enhanced
chemical vapor deposition (PECVD) SiN
x
passivation. These
passivation schemes were implemented on separate pieces of the same
AIGaN/GaN-on-Si HEMT wafer, after gate metal deposition, and
were charactcrized using DC and pulsed I-V Incasurelnents.
Preparation of the surface for ALE growth consisted of ex situ
UV-Ozone treatment for carbon contamination removal, followed by
HCI and HF treatments and low damage in situ nitrogen and hydrogen
plaslna pretrcatlnents for rClnoval of native surface oxidcs. AIN layers
are grown on prepared AIGaN surfaces by ALE, using pulses of high
purity trimethylaluminum (99.999%) and ultra high purity nitrogen
plasma over a range of temperatures (300 to 500 C) with a fixed
pulse sequence. The AIN capping layer grown at 500 C is shown to
ilnprove pcrforInance by providing the lowcst sheet resistance (Rsh),
off-state leakage, and subthreshold slope, with no degradation in the
Schottky gate. Pulsed I-V off-state stress was applied at a gate
quiescent point (VG,Q) of -4 V and drain quiescent biases (VD,Q) up
to 50 V (pulse width of 200 ns and pulse separation of 1 ms), while
thc device is pulsed to obtain thc on-state transfcr characteristics.
AIN passivation reduces degradation of RON,DYN during pulsed I-V
off-state stress compared to PECVD SiN
x
by approximately 50%. The
AIN passivated HEMTs exhibit lower off-state leakage current and
higher breakdown voltage than SiNx passivated HEMTs. Overall,
ALE AIN capping layers provide ilnproved perforInance cOlnpared to
standard SiN
x
passivation. Higher growth temperature AIN films (500
DC) show benefit over lower temperature (300C) AIN films.
281