Static Timing Analysis

What is Timing Analysis??

Before we start anything at least we should know what exactly we mean by Timing Analysis. Why these
days its so important?
There are a couple of reasons for performing timing analysis.
We want to verify whether our circuit meet all of its timing reuirements !Timing "onstraints#
o There are $ types of design constraints% timing& power& area. 'uring designing there is a
trade%offs between speed& area& power& and runtime according to the constraints set by the designer.
(owever& a chip must meet the timing constraints in order to operate at the intended clock rate& so timing
is the most important design constraint.
We want to make sure that circuit is properly designed and can work properly for all combinations
of components over the entire specified operating environment. "Every Time".
Timing analysis can also help with component selection.
o An example is when you are trying to determine what memory device speed& you should
use with a microprocessor. )sing a memory device that is too slow may not work in the circuit !or would
degrade performance by introducing wait states#& and using one that is too fast will likely cost more than it
needs to.
*o + can say Timing analysis is the methodical analysis of a digital circuit to determine if the timing
constraints imposed by components or interfaces are met. Typically& this means that you are trying to
prove that all set%up& hold& and pulse%width times are being met.
Note: Timing analysis is integral part of A*+",-.*+ design flow. Anything else can be compromised but
not timing/
Types of Timing Analysis:
There are 0 type of Timing Analysis%
*tatic Timing Analysis1
o "hecks static delay reuirements of the circuit without any input or output vectors.
'ynamic Timing Analysis.
o verifies functionality of the design by applying input vectors and checking for correct
output vectors
Basic Of Timing Analysis:
The basis of all timing analysis is the clock and the seuential component !here we will discuss with the
help of 2lip%flop# . 2ollowing are few of the things related to clock and flip%flop which we usually wants to
take care during Timing analysis.
"lock related1
+t must be well understood parametrically and glitch%free.
Timing analysis must ensure that any clocks that are generated by the logic are clean& are of
bounded period and duty cycle& and of a known phase relationship to other clock signals of interest.
The clock must& for both high and low phases& meet the minimum pulse width reuirements.
"ertain circuits& such as 3..s& may have other reuirements such as maximum 4itter. As the clock
speeds increase& 4itter becomes an increasingly important parameter.
When 5passing5 data from one clock edge to the other& ensure that the worst%case duty cycle is
used for the calculation. A freuent source of error is the analyst assuming that every clock will have a
678 duty cycle.
2lip%2lop related1
All of the flip%flops parameters are always met. The only exception to this is when synchroni9ers
are used to synchroni9e asynchronous signals
2or asynchronous presets and clears& there are two basic parameters that must be met.
All setup and hold times are met for the earliest,latest arrival times for the clock.
*etup times are generally calculated by designers and suitable margins can be demonstrated
under test. (old times& however& are freuently not calculated by designers.
When passing data from one clock domain to another& ensure that there is either known phase
relationships which will guarantee meeting setup and hold times or that the circuits are properly
synchroni9ed
"Timing Paths" : Static Timing Analysis STA! "asic
Part #!
Static Timing analysis is divided into several parts:
Part1 -> Timing Paths
Part2 -> Time Borrowing
Part3a -> Basic Concept O Set!p and "old
Part3# -> Basic Concept o Set!p and "old $iolation
Part3c -> Practical %&amples or Set!p and "old Time ' $iolation
Part(a -> )elay - Timing Path )elay
Part(# -> )elay - *nterconnect )elay +odels
Part(c -> )elay - ,ire -oad +odel
Part.a -> +a&im!m Cloc/ 0re1!ency
Part.# -> %&amples to calc!late the 2+a&im!m Cloc/ 0re1!ency3 or dierent circ!its4
Part 5a -> "ow to solve Set!p and "old $iolation 6#asic e&ample7
Part 5# -> Contin!e o "ow to solve Set!p and "old $iolation 68dvance e&amples7
Part 5c -> Contin!e o "ow to solve Set!p and "old $iolation 6more advance e&amples7
Part 9a -> +ethods or *ncrease')ecrease the )elay o Circ!it 6%ect o ,ire -ength On the Slew7
Part 9# -> +ethods or *ncrease')ecrease the )elay o Circ!it 6%ect o Si:e o the Transistor On the
Slew7
Part 9c -> +ethods or *ncrease')ecrease the )elay o Circ!it 6%ect o Threshold voltage On the Slew7
Part ; -> 1< ways to i& Set!p and "old $iolation4
As we have discussed in our last blog !about Basic of Timing analysis# that there are 0 types of timing
analysis.
*tatic Timing Analysis
'ynamic Timing Analysis.
:ote1 There is one more type of Timing analysis1 5;anual Analysis5. But now a days nothing is <778
;anual. =vey thing is more automated and less manual. *o that we are not discussing right now.
+n this Blog !and few next as a part of this# we will discuss about the *tatic Timing Analysis. We will
discuss 'ynamic Timing Analysis later on.
Static Timing analysis is divided into several parts as per the a#ove mentioned list4
Static Timing Analysis:
*tatic timing analysis is a method of validating the timing performance of a design by checking all
possible paths for timing violations under worst%case conditions. It considers the worst possible delay
through each logic element, but not the logical operation of the circuit.
+n comparison to circuit simulation& static timing analysis is
2aster % +t is faster because it does not need to simulate multiple test vectors.
;ore Thorough % +t is more thorough because it checks the worst%case timing for all possible logic
conditions& not 4ust those sensiti9ed by a particular set of test vectors.
>nce again :ote this thing 1 *tatic timing analysis checks the design only for proper timing& not for correct
logical functionality.
Static timing analysis seeks to answer the question, Will the correct data be present at the data input of
each synchronous device when the clock edge arrives, under all possible conditions?
+n static timing analysis& the word static alludes to the fact that this timing analysis is carried out in an
input%independent manner. +t locates the worst%case delay of the circuit over all possible input
combinations. There are huge numbers of logic paths inside a chip of complex design. The advantage of
*TA is that it performs timing analysis on all possible paths !whether they are real or potential false
paths#.
(owever& it is worth noting that *TA is not suitable for all design styles. +t has proven efficient only for fully
synchronous designs. *ince the ma4ority of chip design is synchronous& it has become a mainstay of chip
design over the last few decades.
The Way STA is performe$ on a given %irc&it:
To check a design for violations or say to perform *TA there are $ main steps1
'esign is broken down into sets of timing paths&
"alculates the signal propagation delay along each path
And checks for violations of timing constraints inside the design and at the input,output interface.
The *TA tool analy9es A.. paths from each and every startpoint to each and every endpoint and
compares it against the constraint that !should# exist for that path. All paths should be constrained& most
paths are constrained by the definition of the period of the clock& and the timing characteristics of the
primary inputs and outputs of the circuit.
Before we start all this we should know few key concepts in *TA method1 timing path& arrive time&
reuired time& slack and critical path.
.et?s Talk about these one by one in detail. +n this Blog we will mainly 2ocus over 'ifferent Types of
Timing 3aths.
Timing Paths:
Timing paths can be divided as per the type of signals !e.g clock signal& data signal etc#.
Types of 3aths for Timing analysis1
'ata 3ath
"lock 3ath
"lock @ating 3ath
Asynchronous 3ath
=ach Timing path has a 5*tart 3oint5 and an 5=nd 3oint5. 'efinition of *tart 3oint and =nd 3oint vary as
per the type of the timing path. =.g for the 'ata path% The startpoint is a place in the design where data is
launched by a clock edge. The data is propagated through combinational logic in the path and then
captured at the endpoint by another clock edge.
*tart 3oint and =nd 3oint are different for each type of paths. +t?s very important to understand this clearly
to understand and analysing the Timing analysis report and fixing the timing violation.
'ata path
o *tart 3oint
+nput port of the design !because the input data can be launched from some
external source#.
"lock pin of the flip%flop,latch,memory !seuential cell#
o =nd 3oint
'ata input pin of the flip%flop,latch,memory !seuential cell#
>utput port of the design !because the output data can be captured by some
external sink#
"lock 3ath
o *tart 3oint
"lock input port
o =nd 3oint
"lock pin of the flip%flop,latch,memory !seuential cell#
"lock @ating 3ath
o *tart 3oint
+nput port of the design
o =nd 3oint
+nput port of clock%gating element.
Asynchronous path
o *tart 3oint
+nput 3ort of the design
o =nd 3oint
*et,Aeset,"lear pin of the flip%flop,latch,memory !seuential cell#
'ata 3aths1
+f we use all the combination of 0 types of *tarting 3oint and 0 types of =nd 3oint& we can say that there
are B types of Timing 3aths on the basis of *tart and =nd point.
+nput pin,port to Aegister!flip%flop#.
+nput pin,port to >utput pin,port.
Aegister !flip%flop# to Aegister !flip%flop#
Aegister !flip%flop# to >utput pin,port
3lease see the following fig1
Timing 3ath% B types of 'ata 3ath
3AT(<% starts at an input port and ends at the data input of a seuential element. !+nput port to Aegister#
3AT(0% starts at the clock pin of a seuential element and ends at the data input of a seuential element.
!Aegister to Aegister#
3AT($% starts at the clock pin of a seuential element and ends at an output port.!Aegister to >utput
port#.
3AT(B% starts at an input port and ends at an output port. !+nput port to >utput port#
"lock 3ath1
3lease check the following figure
Timing 3aths% "lock 3aths
+n the above fig its very clear that for clock path the starts from the input port,pin of the design which is
specific for the "lock input and the end point is the clock pin of a seuential element. +n between the *tart
point and the end point there may be lots of Buffers,+nverters,clock divider.
"lock @ating 3ath1
"lock path may be passed trough a Cgated elementD to achieve additional advantages. +n this case&
characteristics and definitions of the clock change accordingly. We call this type of clock path as Cgated
clock pathD.
As in the following fig you can see that
Timing 3ath% "lock @ating path.
.' pin is not a part of any clock but it is using for gating the original ".E signal. *uch type of paths are
neither a part of "lock path nor of 'ata 3ath because as per the *tart 3oint and =nd 3oint definition of
these paths& its different. *o such type of paths are part of "lock gating path.
Asynchronous path1
A path from an input port to an asynchronous set or clear pin of a seuential element.
*ee the following fig for understanding clearly.
Timing 3ath% Asynchronous 3ath
As you know that the functionality of set,reset pin is independent from the clock edge. +ts level triggered
pins and can start functioning at any time of data. *o in other way we can say that this path is not in
synchronous with the rest of the circuit and that?s the reason we are saying such type of path an
Asynchronous path.
Other types of Paths:
There are few more types of path which we usually use during timing analysis reports. Those are subset
of above mention paths with some specific characteristics. *ince we are discussing about the timing
paths& so it will be good if we will discuss those here also.
2ew names are
"ritical path
2alse 3ath
;ulti%cycle path
*ingle "ycle path
.aunch 3ath
"apture 3ath
.ongest 3ath ! also know as Worst 3ath & .ate 3ath & ;ax 3ath & ;aximum 'elay 3ath #
*hortest 3ath ! Also Enow as Best 3ath & =arly 3ath & ;in 3ath& ;inimum 'elay 3ath#
"ritical 3ath1
+n short& + can say that the path which creates .ongest delay is the critical path.
"ritical paths are timing%sensitive functional paths. because of the timing of these paths is critical&
no additional gates are allowed to be added to the path& to prevent increasing the delay of the critical
path.
Timing critical path are those path that do not meet your timing. What normally happens is that
after synthesis the tool will give you a number of path which have a negative slag. The first thing you
would do is to make sure those path are not false or multicycle since it that case you can 4ust ignore them.
Taking a typical example !in a very simpler way#& the *TA tool will add the delay contributed from all the
logic connecting the F output of one flop to the ' input of the next !including the ".E%GF of the first flop#&
and then compare it against the defined clock period of the ".E pins !assuming both flops are on the
same clock& and taking into account the setup time of the second flop and the clock skew#. This should be
strictly less than the clock period defined for that clock. +f the delay is less than the clock period& then the
5path meets timing5. +f it is greater& than the 5path fails timing5. The 5critical path5 is the path out of all the
possible paths that either exceeds its constraint by the largest amount& or& if all paths pass& then the one
that comes closest to failing.
2alse 3ath1
3hysically exist in the design but those are logically,functionally incorrect path. ;eans no data is
transferred from *tart 3oint to =nd 3oint. There may be several reasons of such path present in the
design.
*ome time we have to explicitly define,create few false path with in the design. =.g for setting a
relationship between 0 Asynchronous "locks.
The goal in static timing analysis is to do timing analysis on all CtrueD timing paths& these paths are
excluded from timing analysis.
*ince false path are not exercised during normal circuit operation& they typically don?t meet timing
specification&considering false path during timing closure can result into timing violations and the
procedure to fix would introduce unnecessary complexities in the design.
There may be few paths in your design which are not critical for timing or masking other paths
which are important for timing optimi9ation& or never occur with in normal situation. +n such case & to
increase the run time and improving the timing result & sometime we have to declare such path as a 2alse
path & so that Timing analysis tool ignore these paths and so the proper analysis with respect to other
paths. >r 'uring optimi9ation don?t concentrate over such paths. >ne example of this. e.g A path between
two multiplexed blocks that are never enabled at the same time. Hou can see the following picture for this.
2alse 3ath
(ere you can see that 2alse path < and 2alse 3ath 0 can not occur at the same time but during
optimi9ation it can effect the timing of another path. *o in such scenario& we have to define one of the
path as false path.
*ame thing + can explain in another way !:ote% Took snapshot from one of the forum#. As we know that&
not all paths that exist in a circuit are 5real5 timing paths. 2or example& let us assume that one of the
primary inputs to the chip is a configuration inputI on the board it must be tied either to -"" or to @:'.
*ince this pin can never change& there are never any timing events on that signal. As a result& all *TA
paths that start at this particular startpoint are false. The *TA tool !and the synthesis tool# cannot know
that this pin is going to be tied off& so it needs to be told that these *TA paths are false& which the
designer can do by telling the tool using a 5falseJpath5 directive. When told that the paths are false& the
*TA tool will not analy9e it !and hence will not compare it to a constraint& so this path can not fail#& nor will
a synthesis tool do any optimi9ations on that particular path to make it fasterI synthesis tools try and
improve paths until they 5meet timing5 % since the path is false& the synthesis tool has no work to do on
this path.
Thus& a path should be declared false if the designer E:>W* that the path in uestion is not a real timing
path& even though it looks like one to the *TA tool. >ne must be very careful with declaring a path false. +f
you declare a path false& and there is A:H situation where it is actually a real path& then you have created
the potential for a circuit to fail& and for the most part& you will not catch the error until the chip is on a
board& and !not# working. Typically& false paths exists
from configuration inputs like the one described above
from 5test5 inputsI inputs that are only used in the testing of the chip&and are tied off in normal
mode !however& there may still be some static timing constraints for the test mode of the chip#
from asynchronous inputs to the chip !and you must have some form of synchroni9ing circuit on
this input# !this is not an exhaustive list& but covers the ma4ority of legitimate false paths#.
*o we can say that false paths should :>T be derived from running the *TA tool !or synthesis tool#I they
should be known by the designer as part of the definition of the circuit& and constrained accordingly at the
time of initial synthesis.
;ulti"ycle 3ath1
A multicycle path is a timing path that is designed to take more than one clock
cycle for the data to propagate from the startpoint to the endpoint.
A multi%cycle path is a path that is allowed multiple clock cycles for propagation. Again& it is a path that
starts at a timing startpoint and ends at a timing endpoint. (owever& for a multi%cycle path& the normal
constraint on this path is overridden to allow for the propagation to take multiple clocks.
+n the simplest example& the startpoint and endpoint are flops clocked by the same clock. The normal
constraint is therefore applied by the definition of the clockI the sum of all delays from the ".E arrival at
the first flop to the arrival at the ' of the second clock should take no more than < clock period minus the
setup time of the second flop and ad4usted for clock skew.
By defining the path as a multicycle path you can tell the synthesis or *TA tool that the path has : clock
cycles to propagateI so the timing check becomes 5the propagation must be less than : x clockJperiod&
minus the setup time and clock skew5. : can be any number greater than <.
2ew examples are
When you are doing clock crossing from two closely related clocksI ie. from a $7;(9 clock to a
K7;(9 clock&
o Assuming the two clocks are from the same clock source !i.e. one is the divided clock of
the other#& and the two clocks are in phase.
o The normal constraint in this case is from the rising edge of the $7;(9 clock to the
nearest edge of the K7;(9 clock& which is <Kns later. (owever& if you have a signal in the K7;(9 domain
that indicates the phase of the $7;(9 clock& you can design a circuit that allows for the full $$ns for the
clock crossing& then the path from flop$7 %G to flopK7 is a ;"3 !again with :L0#.
o The generation of the signal $7;(MJisJlow is not trivial& since it must come from a flop
which is clocked by the K7;(9 clock& but show the phase of the $7;(9 clock.
Another place would be when you have different parts of the design that run at different& but
related freuencies. Again& consider a circuit that has some stuff running at K7;(9 and some running on
a divided clock at $7;(9.
o +nstead of actually defining 0 clocks& you can use only the faster clock& and have a clock
enable that prevents the clocks in the slower domain from updating every other clock&
o Then all the paths from the 5$7;(95 flops to the 5$7;(95 flops can be ;"3.
o This is often done since it is usually a good idea to keep the number of different clock
domains to a minimum.
*ingle "ycle 3ath1
A *ingle%cycle path is a timing path that is designed to take only one clock cycle for the data to propagate
from the startpoint to the endpoint.
.aunch 3ath and "apture 3ath1
Both are inter%related so + am describing both in one place. When a flip flop to filp%flop path such as )22<
to )22$ is considered& one of the flip%flop launches the data and other captures the data. *o here )22< is
referred to 5launch 2lip%flop5 and )22$ referred to 5capture flip%flop5.
These .aunch and "apture terminology are always referred to a flip%flop to flip%flop path. ;eans for this
particular path !)22<%G)22$#& )22< is launch flip%flop and )22$ is capture flip%flop. :ow if there is any
other path starting from )22$ and ends to some other flip%flop !lets assume )22B#& then for that path
)22$ become launch flip%flop and )22B be as capture flip%flop.
The :ame 5.aunch path5 referred to a part of clock path. .aunch path is launch clock path which is
responsible for launching the data at launch flip flop.
And *imilarly "apture path is also a part of clock path. "apture path is capture clock path which is
responsible for capturing the data at capture flip flop.
This is can be clearly understood by following fig.
.aunch "lock 3ath !.aunch 3ath# and "apture "lock 3ath !"apture path#
(ere )227 is referred to launch flip%flop and )22< as capture flip%flop for 5'ata path5 between )227 to
)22<.*o *tart point for this data path is )227,"E and end point is )22<,'.
>ne thing + want to add here !which + will describe later in my next blog% but its easy to understand here#%
.aunch path and data path together constitute arrival time of data at the input of capture flip%flop.
"apture clock period and its path delay together constitute reuired time of data at the input of
capture register.
ote! +ts very clear that capture and launch paths are correspond to 'ata path. ;eans same clock path
can be a launch path for one data path and be a capture path for another datapath. +ts will be clear by the
following fig !source of 2ig is 2rom *ynopsys#.
*ame clock path behave like "apture and .aunch path for different 'ata path.
(ere you can see that for 'ata path< the clock path through B)2 cell is a capture path but for 'ata path0
its a .aunch 3ath.
.ongest and *hortest 3ath1
Between any 0 points& there can be many paths.
.ongest path is the one that takes longest time& this is also called worst path or late path or a max path.
The shortest path is the one that takes the shortest timeI this is also called the best path or early path or a
min path.
+n the above fig& The longest path between the 0 flip%flop is through the cells )B)2<&):>A0 and
):A:'$. The shortest path between the 0 flip%flops is through the cell ):A:'$.
"Time Borro'ing" : Static Timing Analysis STA! "asic
Part (!
+n a A*+" there are ma4orly two types of component. 2lip%flop and other is .atches. Basically (ere we will
discuss about .atched based timing analysis.
Before this we should understand the basic differences between the latch based design and flip%flop
based design.
=dge%triggered flip%flops change states at the clock edges& whereas latches change states as
long as the clock pin is enabled.
The delay of a combinational logic path of a design using edge%triggered flip%flops cannot be
longer than the clock period except for those specified as false paths and multiple%cycle paths. *o the
performance of a circuit is limited by the longest path of a design.
+n latch based design longer combinational path can be compensated by shorter path delays in
the sebseuent logic stages.*o for higher performance circuits deisgner are turning to latched based
design.
+ts true that in the latched based design its difficult to control the timing because of multi%phase clockes
used and the lack of 5hard5 clock edges at which events must occur.
The techniue of borrowing time from the shorter paths of the subseuent logic stages to the longer path
is called time borrowing or cycle stealing.
Lets talk about this. Please See the following fgure.
=xample of .atched based design.
There are 4 latches (positive level sensitive). L1 and L are controlled b! P"1 and L# and L4
are controlled b! P"#. $1% $#% $ and $4 are co&binational logic paths. 'or now assu&e a
librar! setup ti&e is (ero for the latches and (ero dela! in latch data)path in the transparent
&ode.
*ow if assu&e that if designs using edge)triggered +ip)+ops% the clock period has to be at
least , ns because the longest path in $1 is , ns. *ow as the clock pulse is -ns % there is a
voilation at L#. .n the other hand% if the design uses latches % L# latch is transparent for
another -ns and since the eighth (,th) ns is within the enabled period of L#% the signal
along path1 can pass through L# and continue on path#. Since the dela! along path# is #
ns% which is short enough to co&pensate for the overdue dela! of path1% this design will
work properl!. /n other word we can sa! that path1 can borrow so&eti&e (ns) fro& the
path#. Since the su& of path1 and path# is 10ns% which is the re1uired ti&e of L% there will
be no voilation in either of the Latches.
'or the sa&e reason% path can borrow so&e ti&e (1ns) fro& path4 without an! ti&ing
violation.
Note: A latch-based design completes the execution of the four logic stages in 20
ns, whereas an edge-triggered based design needs 32 ns.
Lets see this in a &ore co&ple2 design. /ts self e2planator!.
=xample >f Timing Borrowing
3ust wanted to conve! here that this Ti&ing borrowing can be &ultistage. 4eans we can
easil! sa! that for a latched based design% each e2ecuting path &ust start at a ti&e when
its driving latch is enabled% and end at a ti&e when its driven latch is enabled.
)e' *mportant things:
Time borrowing occur with in the same cycle. ;eans launching and capturing latches be using
the same phase of the same clock. when the clocks of the launching and capturing latches are out of
phase& time borrowing is not to happen. )sually it was disabled by ='A tools.

Time borrowing typically only affects setup slack calculation since time borrowing slows data arrival times.
*ince hold time slack calculation uses fastest data& time%borrowing typically does not affect hold slack
calculation.
Few mportant terminolog!:
;aximum Borrow time1
;aximum Borrow time is the clock pulse width minus the library setup time of the latch. )sually to
calculate the maximum allowable borrow time& start with clock pulse width and then substract clock
latency & clock reconvergence pessimism removal & library setup time of the endpoint latch.
:egative Borrow time1
+f the arrival time minus the clock edge is a negative number& the amount of time borrowing is negative !in
other way you can say that no borrowing#. This amount is know as :egative Borrow time.
"Set&p an$ +ol$ Time" : Static Timing Analysis STA!
"asic Part ,a!
+ts been long time& people are asking about *etup and (old time blog. 2inally time come for that. 1#
The way we will discuss this concept in the following manner
<. What is *et)p and (old time?
0. 'efinition of *etup and (old.
$. *etup and (old -iolation.
B. (ow to calculate the *etup and (old violation in a design?
+ saw that lots of people are confused with respect to this concept. And the reason of this are
<. They know the definition but don?t know the origin or say concept behind *etup and (old
timing.
0. They know the formula for calculating setup and hold violation but don?t know how this
formula come in picture.
$. They become confuse by few of the terminology like capture path delay& launch path
delay& previous clock cycle& current clock cycle& data path delay& slew& setup slew& hold slew& min
and max concept& slowest path and fastest path& min and max corner& best and worst case etc
during the explanation of *etup and (old Timings,-iolation.
+ hope + can clarify your confusion. .et me explain this and if you face any problem let me know.
What is Set&p an$ +ol$ time?
To understand the origin of the *etup and (old time concepts first understand it with respect to a *ystem
as shown in the fig. An +nput '+: and external clock ".E are buffered and passes through combinational
logic before they reach a synchronous input and a clock input of a ' flipflop !positive edge triggered#.
:ow to capture the data correctly at ' flip flop& data should be present at the time of positive edge of
clock signal at the " pin ! to know the detail 4ust read basis of ' flipflop#.
:ote1 here we are assuming ' flip flop is ideal so Mero hold and setup time for this.
Set=p and "old Time o a System
There may be only 0 condition.
Tp$ -*N . Tp$ %l/
o 2or capture the data at the same time when "lock signal !positive clock edge# reaches at
pin "& you have to apply the input 'ata at pin '+: 5Ts!in#L!Tpd '+:# % !Tpd "lk#5 time before the positive
clock edge at pin ".E.
o +n other word& at '+: pin& 'ata should be stable 5Ts!in#5 time before the positive clock
edge at ".E pin.
o This Time "Tsin!" is /no' as Set&p time of the System.
Tp$ -*N 0 Tp$ %l/
o 2or capture the data at the same time when clock signal !positive clock edge# reaches at
pin "& input 'ata at pin '+: should not change before 5Th!in#L !Tpd "lk# % !Tpd '+:#5 time. +f it will
change& positive clock edge at pin " will capture the next data.
o +n other word& at '+: pin& 'ata should be stable 5Th!in#5 time after the positive clock edge
at ".E pin.
o This time "Thin!" is /no' as +ol$ Time of the System.
2rom the above condition it looks like that both the condition can?t exist at the same time and you are
right. But we have to consider few more things in this.
Worst case and best case !;ax delay and min delay#
o Because of environment condition or because of 3-T& we can do this analysis for the
worst case ! max delay# and best case ! min delay# also.
*hortest 3ath or .ongest path ! ;in 'elay and ;ax delay#
o +f combinational logic has multiple paths& the we have to do this analysis for the shortest
path ! min delay# and longest path ! max delay# also.
*o we can say that above condition can be like this.
Tp$ -*N ma1! . Tp$ %l/ min!
o Set2p time 33 Tp$ -*N ma1! 4 Tp$ %l/ min!
Tp$ -*N min! 0 Tp$ %l/ ma1!
o +ol$ time 33 Tp$ %l/ ma1! 4 Tp$ -*N min!
2or example for combinational logic delays are
'ata path !max& min# L !6ns& B ns#
"lock path !max& min# L !B.6ns& B.<ns#
Then *etup timeL 6%B.<L7.Nns
(old time is L B.6%BL7.6ns
:ow similar type of explanation we can give for a ' flip flop. There is a combinational logic between "
and F & between ' and F of the 2lipflop. There are different delays in those conbinational logic and based
on there max and min value & a flipflop has *etup and (old time. >ne circuitry of the positive edge
triggered ' flip is shown below.
Positive %dge Triggered ) lip-lop
There are different ways for making the ' flip flop. .ike by OE flipflop& master slave flipflop& )sing 0 ' type
latches etc. *ince the internal circuitry is different for each type of 2lipflop& the *etup and (old time is
different for every 2lipflop.
-efinition:
*etup Time1
Set&p time is the minimum amount of time the data signal should be held steady "efore the
clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such
as the flip%flop.
>r +n short + can say that the amount of time the *ynchronous input !'# must be stable "efore the
active edge of the "lock.
The Time when input data is available and stable "efore the clock pulse is applied is called *etup
time.
(old time1
+ol$ time is the minimum amount of time the data signal should be held steady after the clock
event so that the data are reliably sampled. This applies to synchronous circuits such as the flip%flop.
>r in short + can say that the amount of time the synchronous input !'# must be stable after the
active edge of clock.
The Time after clock pulse where data input is held stable is called hold time.
Set&p an$ +ol$ 5iolation:
+n simple language%
+f *etup time is Ts for a flip%flop and if data is not stable before Ts time from active edge of the clock& there
is a *etup violation at that flipflop. *o if data is changing in the non%shaded area ! in the above figure#
before active clock edge& then it?s a *etup violation.
And +f hold time is Th for a flip flop and if data is not stable after Th time from active edge of the clock &
there is a hold violation at that flipflop. *o if data is changing in the non%shaded area ! in the above
figure# after active clock edge& then it?s a (old violation.
"Set&p an$ +ol$ Time 5iolation" : Static Timing
Analysis STA! "asic Part ,"!
"ere we will disc!ss how to calc!late the Set!p and "old $iolation or a design4
Till now we have discussed setup and hold violation with respect to the single flipflop& now lets extend this
to 0 flip flop. +n the following fig there are 0 flipflops !22< and 220#.
Single-Cycle Set!p and "old 0or 0lip-0lops
2ew important things to note down here%
'ata is launching from 22<,' to 22<,F at the positive clock edge at 22<,".
At 220,' & input data is coming from 22<,F through a combinational logic.
'ata is capturing at 220,'& at the positive clock edge at 220,".
*o + can say that .aunching 2lip%2lop is 22< and "apturing 2lip%2lop is 220.
*o 'ata path is 22<," %%G 22<,F %%G 220,'
2or a single cycle circuit% *ignal has to be propagate through 'ata path in one clock cycle. ;eans
if data is launched at timeL7ns from 22< then it should be captured at timeL<7ns by 220.
*o for Set&p analysis at ))(& 'ata should be stable 5Ts5 time before the positive edge at 220,". Where
5Ts5 is the *etup time of 220.
+f TsL7ns& then & data launched from 22< at timeL7ns should arrive at ' of 220 before or at
timeL<7ns. +f data takes too long ! greater then <7ns# to arrive !means it is not stable before clock edge at
220# & it is reported as *etup -iolation.
+f TsL<ns& then& data launched from 22< at timeL7ns should arrive at ' of 220 before or
at timeL!<7ns%<ns#LNns. +f data takes too long !greater then Nns# to arrive !means it is not stable before
<ns of clock edge at 220#& it is reported as *etup -iolation.
2or +ol$ Analysis at ))(& 'ata should be stable 5Th5 time after the positive edge at 220,". Where 5Th5
is the (old time of 220. ;eans there should not be any change in the +nput data at 220,' between
positive edge of clock at 220 at TimeL<7ns and TimeL<7nsPTh.
To satisfy the (old "ondition at 220 for the 'ata launched by 22< at 7ns& the data launched by
22< at <7ns should not reach at 220,' before <7nsPTh time.
+f ThL7.6ns& then we can say that the data launched from 22< at time <7ns does not get
propagated so soon that it reaches at 220 before time !<7P7.6#L<7.6ns ! >r say it should reach from 22<
to 220 with in 7.6ns#. +f data arrive so soon !means with in 7.6ns from 22< to 220& data can?t be stable at
220 for timeL7.6ns after the clock edge at 220#& its reported (old violation.
With the above explanation + can say 0 important points1
"# Setup is checked at ne$t clock edge#
%# &old is checked at same clock edge#
*etup "heck timing can be more clear for the above 2lip%flop combination with the help of following
explanation.
Set!p Chec/ Timing
+n the above fig you can see that the data launched by 22<,' ! at launch edge# reaches at 220,' after a
specific delay ! ".E%to%F delay P "onminational .ogic 'elay# well before the setup time reuirement of
2lip%2lop 220& so there is no setup violation.
2rom the 2ig its clear that if *lackL Aeuired Time % Arrival time Q 7 !%ive# & then there is a *etup violation
at 220.
(old "heck timing can be more clear with the help of following circuit and explanation.
"old Chec/ Timing
+n the above fig you can see that there is a delay in the ".E and ".EB because of the delay introduced
by the series of buffer in the clock path. :ow 2lip%flop 220 has a hold reuirement and as per that data
should be constant after the capture edge of ".EB at 2lip%flop 220.
Hou can see that desired data which suppose to capture by ".EB at 220.' should be at Mero !7# logic
state and be constant long enough after the ".EB capture edge to meet hold reuirement but because of
very short logic delay between 22<,F and 22<,'& the change in the 22<,F propagates very soon. As a
result of that there occurs a (old violation.
'his type of violation (&old )iolation* can be fi$ed by shortening the delay in the clock line or by
increasing the delay in the data path#
*etup and (old violation calculation for the single clock cycle path is very easy to understand. But the
complexity increases in case of multi%cycle path &@ated clock& 2lip%flop using different clocks& .atches in
place of 2lip%2lop. We will discuss all these later sometime.
"E1amples Of Set&p an$ +ol$ time" : Static Timing
Analysis STA! "asic Part ,c!
Till now we have discussed a lot of theor! about setup and hold ti&e (with
and without 52a&ple). *ow it6s ti&e to discuss the practical i&ple&entation
of that. 4eans in a circuit
"ow will !ou calculate the setup and hold values7
"ow will !ou anal!(e setup and hold violation in a circuit7
/f !ou have to i&prove ti&ing of a circuit then what can !ou do7
There are few for&ulas to calculate di8erent para&eter ( Theor! of those /
alread! e2plained in &! previous blogs). / a& not going to e2plain those right
now. 'irst we will solve few e2a&ples which will give !ou an basic idea about
these for&ulas% then in the last / will su&&ari(e all those in one place.
/ saw a lot of confusion with respect to setup and hold ti&ing calculation.
9ctuall! there are two things.
Ti&ing Specifcation of a :lock;<ircuit;Librar!=
o >ou have a block with input 9 and output >. So&e co&binational
logic is there between 9 and >. *ow !ou have to calculate following
para&eters for that block
Setup Ti&e ?alue at input 9
"old Ti&e value at input 9.
4a2i&u& operating <lock 're1uenc! or Ti&e Period for
that block.
<lock To > dela! value
/nput 9 to .utput > dela! value.
Ti&ing ?iolation of a circuit=
o >ou have to operate a circuit at a particular clock fre1uenc! and
now !ou have to fnd out whether this circuit has an! setup or "old ?iolation.
So in second case all the para&eters are given and !ou have to fnd out
whether this circuit has an! violation or not and /n frst case !ou have to fnd
out all the para&eters keeping in &ind that there should not be an!
violation.
Lets @iscuss in the reverse order.
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
""""""""
#roblem$: n the following %ircuit, Find out whether there is an!
&etup 'r (old )iolation*

&olution:
(old Anal!sis:
Ahen a hold check is perfor&ed% we have to consider two things)
4ini&u& @ela! along the data path.
4a2i&u& @ela! along the clock path.
/f the di8erence between the data path and the clock path is negative% then a
ti&ing violation has occurred. ( *ote= there are few 52ceptions for this) Ae
will discuss that so&e other ti&e)
@ata path is= <LB)C''1;<LB )C''1;D )C/nverter )C''#;@
@ela! in @ata path
E &in(wire dela! to the clock input of ''1) F &in(<lk)to)D dela! of ''1)
F&in(cell dela! of inverter) F &in(# wire dela!) GDof ''1)to)inverterG and
Ginverter)to)@ of ''#G)
+,d + $-.-/-0$-$1+$2ns
<lock path is= <LB)C bu8er )C ''#;<LB
<lock path @ela!
E &a2(wire dela! fro& <LB to :u8er input) F &a2(cell dela! of :u8er) F
&a2(wire dela! fro& :u8er output to ''#;<LB pin) F (hold ti&e of ''#)
+,cl3 + 3-.-3-2 + $4 ns
(old &lac3 + ,d - ,cl3 + $2ns -$4ns + $ns
&ince (old &lac3 is positi5e-6 No hold )iolation.
Note: f the hold time had been 7 ns instead of 2 ns, then there
would ha5e been a hold 5iolation.
TdE1,ns and Tclk E FHFF4E1Hns
So "old SlackETd ) Tclk E 1,ns ) 1Hns E )1ns (?iolation)
&etup Anal!sis:
Ahen a setup check is perfor&ed% we have to consider two things)
4a2i&u& @ela! along the data path.
4ini&u& @ela! along the clock path.
/f the di8erence between the clock path and the data path is negative% then a
ti&ing violation has occurred. ( *ote= there are few 52ceptions for this) Ae
will discuss that so&e other ti&e)
@ata path is= <LB)C''1;<LB )C''1;D )C/nverter )C''#;@
@ela! in @ata path
E &a2(wire dela! to the clock input of ''1) F &a2(<lk)to)D dela! of ''1)
F&a2(cell dela! of inverter) F &a2(# wire dela!) GDof ''1)to)inverterG and
Ginverter)to)@ of ''#G)
+,d + 2-$$-.-02-21 + 2/ns
Note: The frst part of the clock path delay (during setup calculation) is the
clock period, which has been set to 15 ns. ope !ou re"e"ber in last blog, #
ha$e "entioned $ery clearly that Setup is checked at the next clock
cycle. That%s the reason for clock path delay we ha$e to include clock period
also.
<lock path is= <LB)C bu8er )C ''#;<LB
<lock path @ela!
E (<lock period) F &in(wire dela! fro& <LB to :u8er input) F &in(cell dela!
of :u8er) F &in(wire dela! fro& :u8er output to ''#;<LB pin) ) (Setup ti&e
of ''#)
+,cl3 + $8-2-8-2-7+20ns
&etup &lac3 + ,cl3 - ,d + 20ns - 2/ns + -/ns.
&ince &etup &lac3 is negati5e -6 &etup 5iolation.
Note: A bigger cloc3 period or a less maximum dela! of the in5erter
sol5e this setup 5iolations in the circuit.
%4g
* Cloc/ period is 22ns then
Tcl/ > 22?2?.?2-(>31-(>29ns 8@) Td > 25ns
Set!p Slac/ > Tcl/ - Td > 29-25>1ns 6@o $iolation7
#roblem2: n order to wor3 correctl!, what should be the &etup and
(old time at nput A in the following %ircuit. Also 9nd out the
maximum operating fre:uenc! for this circuit. 0Note: gnore ;ire
dela!1. ;here ,su- &etup time< ,hd-(old ,ime< ,c2:- %loc3-to-=
dela!
&olution:
Step1= 'ind out the &a2i&u& Iegister to register @ela!.
4a2 Iegister to Iegister @ela!
E (clk)to)D dela! of J#) F (cell dela! of J) F (all wire dela!) F (setup ti&e
of J1)
E - F , F E 1K ns.
Note:
There are & register to register paths
o '& () '* ()'1 (+elay,5-.-*,1/ns)
o '1 () '0 () '& ( +elay,5-1-*,15ns)
2e ha$e to pick "a3i"u" one.
Step#= 'ind .ut Setup Ti&e=
9 setup ti&e E Setup ti&e of 'lip+op F 4a2 (@ata path @ela!) ) &in(<lock
path @ela!)
E (Setup ti&e of 'lip+op F 9#@ &a2 dela!) ) (<lk path &in dela!)
E Tsu F (Tpd JL F Tpd J F wire dela!) ) Tpd J,
E F (1F, ) ) # E 10 ns
Note:
ere we are not using the 4lock period. 5ecause we are not suppose
to calculate the 6etup $iolation. 2e are calculating 6etup ti"e. 7lease refer
the part*a for the referance.
8ll the wire dealy is neglected. #f 2ire delay present, we ha$e to
consider those one.
There are & +ata path
o 8 () '1 () '0 () + of '& (+ata path +elay , 1-1 ,.ns )
o 8 () '1 () '* () + of '1 ( +ata path +elay , 1-. ,9ns )
6ince for 6etup calculation we need "a3i"u" +ata path delay, we
ha$e choosen &nd for our calculation.
Step= 'ind .ut "old Ti&e=
9 hold ti&e E "old ti&e of 'lip+op F &a2(<lock path @ela!) ) &in( @ata path
dela!)
E( "old ti&e of 'lip+op F <lk path &a2 dela!) ) (9#@ &a2 dela!)
E Thd F Tpd J, ) (Tpd JL F Tpd J4Fwire dela!)
E 4 F # ) (1FL ) E )# ns
Note: 6a"e e3planation as for 6etup ti"e. :or hold ti"e we need "ini"u"
data path , so we ha$e picked frst +ata path.
Step4= 'ind out <lock to .ut Ti&e=
<lock to .ut
E <ell dela! of J, F <lk)to)D dela! of 'lip'lopF <ell dela! of J-F <ell dela!
of JKF (all wire dela!)
E Tpd J,F J# Tc#1 F J- Tpd F JK Tpd
E # F - F H F K E ## ns
Note:
There are & 4lock to ;ut path( one fro" :lip <op '1 and other fro"
'&.
6ince in this case the 4lk(to(= path for both :lip<op is sa"e, we can
consider any path. 5ut in so"e other 4ircuit where the delay is di>erent for
both the paths, we should consider ?a3 delay path.
Step-= 'ind Pin to Pine <o&binational @ela! (9 to > dela!)
Pin to Pin <o&binational @ela! (9 to >)
E JL Tpd F J- Tpd F JK Tpd
E 1 F H F K E 1K ns
Step-= 'ind .ut 4a2 <lock 're1uenc!=
4a2 <lock 're1 E 1; 4a2 (Ieg#reg% <lk#.ut% Pin#Pin)
E 1; 4a2 (1K% ##% 1K)
E 4-.- 4h(
So su&&er! is=
#arameter >escription ?in ?ax @nits
Tclk <lock Period ## ns
'clk <lock 're1uenc! 4-.- 4h(
9tsu 9 setup ti&e 10 ns
9thd 9 hold ti&e )# ns
9#> 9 to > Tpd 1K ns
<k#> <lock to > tpd ## ns
Note: Negati5e hold times are t!picall! speci9ed as 0 ns.
#roblem3: n the abo5e %ircuit, ,r! to impro5e the timing b! adding
an! AbuBerA or ACegisterA.
&olution:
:est wa! of doing this is MIegister all /nput and .utputN. Ae are adding @''
so sa&e specifcation (as J# and J1).
*ow follow all those - Steps onn b! one.
Step1=
4a2 Iegister to Iegister @ela!
J# Tc#1 F J- Tpd F JH Tsu E - F H F E 1L ns
Note:
8 lot of @egister to @egister path
o '. () '5 () '9 (+elay , 5-9-*,11ns)
o '. () '0 () '& (+elay , 5-1-*,15ns)
o '. () '* () '1 (+elay , 5-.-*,1/ns)
o '1 () '0 () '& (+elay, 5-1-*,15ns)
o '1 () '5 () '9 (+elay, 5-9-*,11ns)
o '& () '5 () '9 (+elay , 5-9-*,11ns)
o '& () '* () '1 (+elay , 5-.-*,1/ns)
?a3i"u" delay is 11ns, Aust picked anyone.
Step#=
9 setup ti&e E Tsu F 9#@ Tpd &a2 ) <lk Tpd &in
E Tsu F (Tpd JL) ) Tpd J,
E F (1) ) # E # ns
Note: ;nly ;ne path between 8 and + of ::(i.e '.)
Step=
9 hold ti&e E Thd F <lk Tpd &a2 ) 9#@ Tpd &in
E Thd F Tpd J, ) (Tpd JL)
E 4 F # ) ( 1) E - ns
Note: ;nly ;ne path between 8 and + of ::(i.e '.)
Step4=
<lock to out=
ETpd J,F JH Tc#1 F JK Tpd
E#F-FK E 1 ns
Step-=
*o direct link between 9 and >. So *ot 9pplicable.
StepK=
4a2 <lock 're1 E 1; 4a2 (Ieg#reg% <lk#.ut% Pin#Pin)
E 1; 4a2 (1L% 1)
E-,., 4h(
#arameter >escription ?in ?ax @nits
Tclk <lock Period 1L ns
'clk <lock 're1uenc! -,., 4h(
9tsu 9 setup ti&e # ns
9thd 9 hold ti&e - ns
<k#> <lock to > tpd 1 ns
Points to remem"er:
"# Setup is checked at ne$t clock edge#
%# &old is checked at same clock edge#
+# ,or &old -heck ( -hecking of hold )iolation*
o Minimum Delay along the data path.
o Maximum Delay along the clock path.
.# ,or Set/p -heck ( -hecking of Setup )iolation*
1. Maximum Delay along the data path.
2. Minimum Delay along the clock path.

sic 0 2lip2lop circuit.

Calculation of Setup Violation Check: -onsider above circuit of 0 22 connected to each other.
&etup &lac3 + Ce:uired time - Arri5al time 0since we want data to arri5e before it
is re:uired1
Ahere=
9rrival ti&e (&a2) E clock dela! ''1 (&a2) Fclock)to)D dela! ''1 (&a2) F co&b.
@ela!( &a2)
Ie1uired ti&e E clock adOust F clock dela! ''# (&in) ) set up ti&e ''#
<lock adOust E clock period (since setup is anal!(ed at ne2t edge)
Calculation of Hold Violation Check: -onsider above circuit of 0 22 connected to each other.
(old &lac3 + Arri5al ,ime - Ce:uired time 0since we want data to arri5e after it is
re:uired1
Ahere=
9rrival ti&e (&in) E clock dela! ''1 (&in) Fclock)to)D dela! ''1 (&in) F co&b.
@ela!( &in)
Ie1uired ti&e E clock adOust F clock dela! ''# (&a2) F hold ti&e ''#
<lock adOust E 0 (since hold is anal!(ed at sa&e edge)
Calculation of Maximum Clock Frequency:
?ax %loc3 Fre: + $D ?ax 0Ceg2reg dela!, %l32'ut dela!, #in2#in dela!1
;here:
Ceg2Ceg >ela! + %l3-to-= dela! of 9rst FF 0max1 - conb dela! 0max1 -
setup time of 2nd FF.
%l32'ut >ela! + %loc3 dela! w.r.t FF 0max1 - cloc3-to-= dela! of FF$
0max1 - comb. dela! 0max1
#in2#in dela! + %omb dela! between input pin to output pin 0max1
"-elay 4 Timing path -elay" : Static Timing
Analysis STA! "asic Part 6a!
This particular post is inspired by a uestion asked by .alit. And 2rankly speaking + am not able to resist
myself to write a blog on this. + was thinking to capture all this since long but every time because of work +
have to drop my thoughts.. But today after reading his uestion.. + am not able to control myself. 1#
*o the Fuestion is1 !original uestion#
I have a doubt regarding how delay is calculated along a path#i think there are two ways
"* to calculate ma$ delay and min delay, we keep adding ma$ delays and min delays of all
cells(buffer0inverter0mu$* from start point to end point respectively#
%*in other way, we calculate path delay for rising edge and falling edge separately# we apply a rise edge
at start point and keep adding cell delay# cell delay depends upon input transition and output fanout# so
now we have two path delay values for rise edge and falling edge# greater one is considered as 1a$
delay and smaller one is min delay#
which one is correct ?
*hort Ans is .. both are correct and you have to use both. ;ay be you all become confuse& so let me give
you few details.
As + have mention that for *etup and (old calculation & you have to calculate the 'elay of the Timing path
!capture path or launch path#. :ow in a circuit there are 0 ma4or type of 'elay.
<. "=.. '=.AH
o Timing 'elay between an input pin and an output pin of a cell.
o "ell delay information is contained in the library of the cell. e.g% .lef file
0. :=T '=.AH.
o +nterconnect delay between a driver pin and a load pin.
o To calculate the :=T delay generally you reuire $ most important information.
"haracteristics of the 'river cell !which is driving the particular net#
.oad characteristic of the receiver cell. !which is driven by the net#
A" !resistance capacitance# value of the net. !+t depends on several factor%
which we will discuss later#
Both the delay can be calculated by multiple ways. +t depends at what stage you reuire this information
with in the design. e.g 'uring pre layout or 3ost layout or during *ignoff timing. As per the stage you are
using this& you can use different ways to calculate these 'elay. *ometime you reuire accurate numbers
and sometime approximate numbers are also sufficient.
:ow lets discuss this with previous background and then we will discuss few new concepts.
:ow in the above fig% +f + will ask you to calculate the delay of the circuit& then the delay will be
-elay37.897.7697.:(97.(#97.;,97.#89#.7#97.#(97.8<36.78ns if all the $elay in ns!
:ow lets add few more value in this. As we know that every gate and net has max and min value& so in
that case we can find out the max delay and min delay. !on what basis these max delay and min delay we
are calculating .. we will discuss after that#
*o in the above example& first value is max value and 0nd value is min value. *o
-elayma1!3 7.897.7697.:(97.(#97.;,97.#89#.7#97.#(97.8<36.78ns
-elaymin!3 7.697.7,97.:97.#;97.;97.#97.;97.#97.83,.8#ns
Till now every one know the concept. :ow lets see what?s the meaning of min and max delay.
The delay of a cell or net depends on various parameters. 2ew of them are listed below.
.ibrary setup time
.ibrary delay model
=xternal delay
"ell load characteristic
"ell drive characteristic
>perating condition !3-T#
Wire load model
=ffective "ell output load
+nput skew
Back annotated 'elay
+f any of these parameter vary & the delay vary accordingly. 2ew of them are mutually exclusive. and +n
that case we have to consider the effect of only one parameter at a time. +f that?s the case & then for *TA&
we calculated the delay in both the condition and then categori9e them in worst !max delay# condition or
the best condition !min delay#. =.g% if a cell has different delay for rise edge and fall edge. Then we are
sure that in delay calculation we have to use only one value. *o as per their value & we can categori9e fall
and rise delay of all the cell in the max and min bucket. And finally we come up with max 'elay and min
delay.
*normation !sed in Cell and net delay calc!lation 6Pict!re So!rce - Synopsys7
The way delay is calculated also depends which tool are you using for *TA or delay calculation. "adence
may have different algorithm from *ynopsys and same is the case of other vendor tools like
mentor&magma and all. But in general the basic or say concepts always remain same.
+ will explain about all these parameter in detail in next of few blogs& but right now 4ust one example which
can help you to understand the situation when you have a lot of information about the circuit and you want
to calculate the delay.
+n the above diagram& you have 0 paths between )22< and )22$. *o when ever you are doing setup and
hold analysis& these path will be the part of launch path !arrival time#. *o lets assume you want to
calculate the max and min value of delay between )22< and )220.
*nformation#:
J.I4 J*9*@K J*9*@0 J:J'# J.I#
@5L9>(ns
)
- K K # -
"alculation1
'elay in 3ath< 1 6PKL<<ns&
'elay in 3ath01 KP0P6PKL<Nns&
*o
;ax 'elay L <Nns % 3ath0 % .ongest 3ath % Worst 3ath
;in 'elay L <<ns % 3ath< % *mallest 3ath % Best 3ath
*nformation(:
J.I4 J*9*@K J*9*@0 J:J'# J.I#
Iise @ela!
(ns)
- K 4 1 1
'all @ela!
(ns)
K L 1 1
"alculation1
'elay in 3ath< 1 Aise 'elay 1 6PKL<<ns& 2all 'elay1 KPRL<$ns
'elay in 3ath01 Aise 'elay 1 BP<P<PKL<0ns& 2all 'elay1 $P<P<PRL<0ns
*o
;ax 'elay L <$ns %3ath< !2all 'elay#
;in 'elay L <<ns % 3ath< !Aise 'elay#
:ote1 here there are lot of more concepts which can impact the delay calculation seuence& like unate.
We are not considering all those right now. + will explain later.
*nformation,:
Librar
!
@ela! J.I4 J*9*@K J*9*@0 J:J'# J.I#
4in
Iise @ela!
(ns)
- K 4 1 1
'all @ela!
(ns)
K L 1 1
4a2
Iise @ela!
(ns)
-.- K.- 4.- 1.- 1.-
'all @ela!
(ns)
-.- K.- #.- 0.- 0.-
"alculation1
2or ;in .ibrary1
'elay in 3ath< 1 Aise 'elay 1 6PKL<<ns& 2all 'elay1 KPRL<$ns
'elay in 3ath01 Aise 'elay 1 BP<P<PKL<0ns& 2all 'elay1 $P<P<PRL<0ns
2or ;ax .ibrary1
'elay in 3ath< 1 Aise 'elay 1 6.6PK.6L<0ns& 2all 'elay1 6.6PK.6L<Bns
'elay in 3ath01 Aise 'elay 1 B.6P<.6P<.6PK.6L<Bns& 2all 'elay1 0.6P7.6P7.6PK.6L<7ns
*o
;ax 'elay L <Bns% 3ath<!2all 'elay#,3ath0!Aise 'elay#
;in 'elay L <7ns % 3ath0!2all 'elay#
As we have calculated above& *TA tool also uses similar approach for finding the ;ax delay and ;in
'elay. >nce ;ax and ;in delay is calculated then during setup and hold calculation& we use
corresponding value.
>nce again + am mentioning that all these values are picked randomly. *o it may be possible that
practically the type,amount of variation in value is not possible.
+n next part we will discuss these parameter in detail one by one.
-elay 4 "*nterconnect -elay =o$els" : Static Timing
Analysis STA! "asic Part 6"!
+n the previous post we have discussed about the way tool calculate the max and min delay in a circuit.
:ow we will discuss other basics of the 'elay and delay calculation. 'uring your day to day work !in
*emiconductor 2ield# or say in different Books& you come across different terminology related to the
delays. There is a long list of that.
+nput 'elay
>utput 'elay
"ell 'elay
:et 'elay
Wire 'elay
*lope 'elay
+ntrinsic 'elay
Transition 'elay
"onnect 'elay
+nterconnect 'elay
3ropagation 'elay
;in,;ax 'elay
Aising,2alling 'elay
@ate 'elay
*tage delay
2ortunately or say luckily out of the above mention long list few are 4ust synonym of
other and few are interrelated to each other . .ike :et delay also know as Wire 'elay &
+nterconnect delay. Broadly we can divide this .ong .ist into 0 type of delay. :et 'elay
!Wire delay# and "ell 'elay. ! Note : *tage 'elay L :et delay P "ell 'elay. #
*o lets discuss these one by one. +n digital design& a wire connecting pins of standard
cells and blocks is referred to as a :=T. A net
(as only one driver
(as a number of fanout cells or blocks.
"an travel on multiple metal layers of the chip.
C:et 'elayD refers to the total time needed to charge or discharge all of the parasitic
!"apacitance , Aesistance , +nductance# of a given :et. *o we can say that :et delay is
a function of
:et Aesistance
:et "apacitance
:et Topology
:ow to calculate the :et delay& the wires are modeled in different ways and there are
different way to do the calculation. 3ractically& when you are applying a particular delay
model in a design & then you have to apply that to all cells in a particular library. Hou
cannot mix delay models within a single library. There are few recommendations
provided by experts or say experienced designer regarding the application of a
particular 'elay model in a design and that depends on
Technology of design.
At what stage you are ? >r say at what stage you want to apply a delay model.
(ow accurately you want to calculate the delay.
Note : +deally Till the physical wire is not present in you design& you cannot calculate the
:et delay. Aeason is ... +f wire is not present & you have no idea about the .ength,Width
of the wires. *> H>) "A::?T "A.").AT= T(= A"")AAT= -A.)=* >2 3AAA*+T+"
>A *AH '=.AH -A.)= >2 T(= W+A=. But here main point is accurate value& means
there is possibility of inaccurate or say approximate value of delay value before physical
laying of wire in a design.
There are several delay models. Those which can provide more accurate result& takes
more runtime to do the calculation and those which are fast provides less accurate
value of delay. .ets discuss few of them. ;ost popular delay models are %
.umped "apacitor ;odel
.umped A" model
'istributed A" model
o 3i A" network
o T A" network
A." model
Wire .oad model
=lmore 'elay model
Transmission .ine ;odel
>&mpe$ %apacitor =o$el.
;odel assume that wire resistance is negligible.
*ource driver sees a single loading capacitance which is the sum of total
capacitance of the interconnect and the total loading capacitance at the sink.
+n past !higher technology%$67nm and so#& capacitor was dominating and thats
the reason in the model we have only capacitance.
o >lder technology had wide wires&
o ;ore cross section area implies less resistance and more capacitance.
o *o Wire model only with capacitance.
+n the 2ig AL7
.umped "apacitor ;odel
>&mpe$ ?% ?esistance %apacitance! mo$el:
As the feature si9e decreases to the submicron dimensions& width of the wire
reduced.
Aesistance of wire is no longer negligible.
(ave to incorporate the resistance in our model. And thats the reason .umped
A" model !or say A" tree# comes into picture.
+n lumped A" model the total resistance of each wire segment is lumped into one single
A& combines the global capacitive into single capacitor ".
.umped A" ;odel
-istri"&te$ ?% mo$el:
'istributed means A" is distributed along the length of the wire. The total resistance
!At# and capacitance !"t# of a wire can be expressed as
At L Ap S .
"t L "p S .
Where
"p and Ap are "apacitance and Aesistance per unit length.
. is the length of the wire.
+deally& distributing the resistance and capacitance of a wire in very small portion of the
wire !say delta# give you the better performance. :ow to find out the total capacitance
and resistance we use the differential euation. 'istributed A" model provides better
accuracy over lumped A" model. But this type of model is not practically possible.
'istributed A" ;odel

The distributed A" model can be configured by 0 ways based on the structure or say
shape !pi and T#. 2ollowing is the pictorial view.
T model1
"t is modeled as a half way of the resistive tree.
At is broken into 0 sections !each being At,0 #
3i ;odel1
"t is broken into 0 sections !each being "t,0# are connected on either side of the
resistance.
At is in between the capacitances.
2or practical purpose& wire%models with 6%<7 elements,nodes are used to model the
wire. +t will provide the more accurate result. 2or : element section
2or T network1
+ntermediate section of resistance are eual to At,:.
+ntermediate section of "apacitance are modeled by "t,:
En$ section of ?esistance are e@&al to ?tA(N!.
This T :etwork is represented as T: model.
2or 3i network1
+ntermediate section of resistance are eual to At,:.
+ntermediate section of "apacitance are modeled by "t,:
En$ section of %apacitance are e@&al to %tA(N!.
This 3i :etwork is represented as 3i: model.
0 Types of 'istributed A" ;odel !3i% ;odel and T% ;odel#
Note: >&mpe$ 5s -istri"&te$ ?% 'ire:
2ollowing is the comparison between the .umped and distributed A" network. +t will
help you to understand in terms of uses of the both type of network in terms of accuracy
and runtime.
2ollowing is the *tep Aesponse of .umped -s 'istributed A" line.
*tep Aesponse >f .umped and 'istributed A" :etwork
Below comparison Table will give you more accurate picture.
O&tp&t Potential range
Time Elapse$
-istri"&te$ ?% Net'or/ >&mpe$ ?% net'or/
7 to N78 <.7A" 0.$A"
<78 to N78 !rise time# 7.NA" 0.0A"
7 to K$8 7.6A" <.7A"
7 to 678 7.BA" 7.RA"
7 to <78 7.<A" 7.<A"
?>% mo$el
+n the past since the design freuency was low so the impedance !w.# was dominated
by Aesistance !w. QQ A#. *o we are not caring C.D. (owever if you are operating at
higher freuency and use the wider wire that reduce the resistivity then we have to take
account the inductance into our modeling.
'istributed A." ;odel
-elay 4 "Wire >oa$ =o$el" : Static Timing Analysis
STA! "asic Part 6c!
Now the question is: What is Wire Load Models (WLM).
,ire loading models
=sed to estimate the interconnect wire delay d!ring pre-layo!t in a design
cycle4
,ire load inormation is #ased on statistics rom physical layo!t parasitic
o *normation rom the statistics is !sed in #oth conservative and
aggressive ta#les4
o The conservative ta#les are #ased on 2mean val!e3 pl!s 3-sigmaA the
aggressive ta#les on 2mean val!e3 pl!s 1-sigma4
)ierent or dierent technology4
o ,ire load models are appro&imated rom one technology to another
#ased on scaling actors4 )!e to these appro&imationsB the acc!racy o these
models diminish over m!ltiple technology nodes
)escri#es eect o wire length and ano!t on
o Cesistance
o Capacitance
o 8rea o the nets4
8ll attri#!tes 6CB C and 8rea7 are given per !nit length wire4
Slope val!e is !sed to characteri:e linear ano!t4
Basically a set o ta#les
o @et ano!t vs load
o @et ano!t vs resistance
o @et ano!t vs area
One e&ample o s!ch type o ta#le is:
@et
0ano!t
Cesistance
DE
Capacitance
p0
1 0.00498 0.00312
2 <4<12F. <4<<;12
3 <4<2<F2 <4<1312
( <4<2;;; <4<1;11
8s per this
*n a#ove circ!it - The CC val!e is estimated and represented as per ,-+4
The ollowing are ew snapshot o the dierent ormat o wire load model4
wireGload6H,-+1H7 I
resistance : <4<<<5 A------>C per !nit length
capacitance : <4<<<1 A------> C per !nit length
area : <41 A------> 8rea per !nit length
slope : 14. A------> =sed or linear e&trapolation
ano!tGlength61B <4<<27 A ------> at ano!t 213 length o the wire is <4<<2
ano!tGlength62B <4<<57A
ano!tGlength63B <4<<F7A
ano!tGlength6(B <4<1.7A
ano!tGlength6.B <4<2<7A
ano!tGlength69B <4<2;7A ------> at ano!t 293 length o the wire is <4<2;
ano!tGlength6;B <4<3<7A
ano!tGlength6FB <4<3.7A
ano!tGlength61<B <4<(<7A
J
wireGload6H,-+2H7 I
ano!tGlength6 1B 1 7A
ano!tGlength6 2B 2 7A
ano!tGcapacitance6 1B <4<<2 7A
ano!tGcapacitance6 2B <4<<( 7A
ano!tGcapacitance6 3B <4<<5 7A
ano!tGcapacitance6 (B <4<<; 7A
ano!tGcapacitance6 .B <4<1< 7A
ano!tGcapacitance6 5B <4<13 7A
ano!tGcapacitance6 9B <4<1. 7A
ano!tGcapacitance6 ;B <4<1F 7A
ano!tGcapacitance6 FB <4<23 7A
ano!tGcapacitance6 1<B <4<297A

ano!tGresistance6 1B <4<1 7A
ano!tGresistance6 2B <4<1. 7A
ano!tGresistance6 3B <4<22 7A
ano!tGresistance6 (B <4<25 7A
ano!tGresistance6 .B <4<3< 7A
ano!tGresistance6 5B <4<3. 7A
ano!tGresistance6 9B <4<3F 7A
ano!tGresistance6 ;B <4<(; 7A
ano!tGresistance6 FB <4<.9 7A
ano!tGresistance6 1<B <4<5 7A

ano!tGarea6 1B <411 7A
ano!tGarea6 2<B 242< 7A
J
"ere --
8reaB Cesistance and Capacitance are in per !nit length o the interconnect4
The slope is the e&trapolation slop to #e !sed or data points that are not speciied
in the an-o!t length ta#le4
*n generalB not all ano!ts are mentioned in a given ,-+ loo/!p ta#le4 0or
e&ampleB in a#ove ,-+1 and ,-+2 loo/!p ta#leB capacitance and resistance
val!es or ano!ts 1B 2B 3B (B .B 9B ;B FB 1< is given4 * we want to estimate the
val!es at ano!ts in the gaps 6e4g4 rom 57 or o!tside the ano!t range speciied in
the ta#le 6e4g 0ano!t 2<7B we have to calc!lated those val!e !sing 6linear7
interpolation and e&trapolation4
For WLM1
For Fanout20
Since its more than the ma& val!e o 0ano!t availa#le in ta#le 6i4e 1<7 B so we have
to perorm e&trapolation4
Net length = <length of net at fanout 10> + (20-10) x Slope
Resistance = <new calculated Net length at fanout > x Resistance o!
"apacitance #alue pe! unit length
"apacitance = <new calculated Net length at fanout > x "apacitance #alue pe!
unit length
@et length > <4<(< ? 1< & 14. 6slope7 > 1.4<( ----------> length o net with ano!t
o 2<
Cesistance > 1.4<( & <4<<<5 > <4<<F<2( !nits
Capacitance > 1.4<( & <4<<<1 > <4<<1.<( !nits
For Fanout!
Since itKs #etween . and 9 and corresponding ano!t $s length is availa#leB we can
do the interpolation4
Net length = ( (net length at fanout $) + (net length at fanout %) ) & 2
Resistance = <new calculated Net length at fanout 20> x Resistance #alue pe! unit
length
"apacitance = <new calculated Net length at fanout 20> x "apacitance #alue pe!
unit length
@et length > 6<4<<2< ? <4<<2;7'2><4<<(;'2><4<<2( ----------> length o net with
ano!t o 5
Cesistance > <4<<2( & <4<<<5 > <4<<<<<1(( !nits
Capacitance > <4<<2( & <4<<<1 > <4<<<<<<2( !nits
*n the similar way we can calc!late the ,-+ or any no o ano!t val!e4
,-+s are oten !sed in pre-placement optimi:ation to drive speed!ps o critical
paths4 Since timing-driven placement pla!si#ly ma/es nets on critical paths shorter
than averageB some optimism may #e incorporated into the ,-+4 Th!sB a ,-+
may act!ally consist o more than one loo/!p ta#leB with each ta#le corresponding
to a dierent optimism level4 There are several ways to incorporate the optimism
level4 * we !se the ,-+s that come rom the 68S*C vendorKs7 design li#raryB
!s!ally there are several ta#les rom which we can select4 ,e can also increase the
optimism level o a ,-+ #y m!ltiplying all val!es in the ,-+ #y some actor
less than 142 0or e&ampleB we can !se <42.B <4.B or <49.4
,-+ Types
0or lows that r!n timing-#ased logic optimi:ation #eore placementB there are
three #asic types o ,-+s that can #e !sed:
14 Statistical ,-+s
o 8re #ased on averages over many similar designs !sing the same or
similar physical li#raries4
24 Str!ct!ral ,-+s
o =se inormation a#o!t neigh#oring netsB rather than L!st ano!t and
mod!le si:e inormation4
34 C!stom ,-+s
o 8re #ased on the c!rrent design ater placement and ro!tingB #!t
#eore the c!rrent iteration o preplacement synthesis4
Now the "uestion is: Where do the wire load #odels $o#e %ro#&
@ormally the semicond!ctor vendors will develop the models4
8S*C vendors typically develop wireload models #ased on statistical inormation
ta/en rom a variety o e&ample designs4 0or all the nets with a partic!lar ano!tB
the n!m#er o nets with a given capacitance is plotted as a histogram4 8 single
capacitance val!e is pic/ed to represent this ano!t val!e in the wireload model4 *
a very conservative wireload model is desiredB the F<M decile might #e pic/ed 6i4e4
F<M o the nets in the sample have a capacitance smaller than that val!e74
*n this e&ample F<M o nets have a capacitance smaller then <41F;p4 So in the
,-+ ta#leB yo! will notice that ano!tGcapacitance6 3B <41F; 74
Similar statistics are gathered or resistance and net area4
=s!ally the vendor s!pplies a amily o wireload modelsB each to #e !sed or a
dierent si:e design4 This is called a!ea-'ased wi!eload selection
Few 'd(an$e $on$e)ts:
Till now we have disc!ssed that or a partic!lar @et yo! can estimate the CC val!e
as per the ,-+4 -et me as/ yo! one 1!estion4 ,hat i yo!r design is hierarchicalN
)o yo! thin/ even in that case yo! can !se the same ,-+ or a partic!lar net
which is crossing the hierarchical #o!ndariesN Short 8@S is: yo! can !se it #!t
yo! will lose the acc!racy4
O!st to solve this pro#lemB $endors !s!ally s!pplies m!ltiple ,-+s4 There are
dierent +odes or ,-+ analysis- ew important are:
,-+ analysis has three modes:
14 Top:
o Consider the design as it has no hierocracy and !se the ,-+ or the
top mod!le to calc!late delays or all mod!les4
o 8ny low level ,-+ is ignored4
24 %nclosed:
o =se the ,-+ o the mod!le which completely encloses the net to
comp!te delay or that net4
34 Segmented:
o * a net goes across several ,-+B !se the ,-+ that corresponds to
that portion o the net which it encloses only4
=a1im&m %loc/ )re@&ency : Static Timing Analysis
STA! "asic Part 8a!
This is a general uestion in most of the interview& whats the maximum clock freuency for a particular
circuit? >r +nterviewer will provide some data and they will repeat the same uestion. ;any of us know
the direct formula and after applying that we can come across the final CAnsD but if someone twist the
uestion. *ome %time we become confuse. + motivation of this blog is the same. *everal people asked me
how to calculate the max%clock freuency. *o + thought that its best if + can write something over this.
(ere + will discuss the same but from basic point of view. +t has $ ma4or sections.
<. +n <
st
section& we will discuss different definitions with respect to *euential and
combinational "ircuits.
0. 0
nd
*ection contains the basics of C;aximum "lock 2reuencyD. + will explain why and
how you can calculate the max "lock freuency.
$. + will take few examples and try to solve them. + will make sure that + can capture at least
0%B examples from easy one to difficult one.
As we know that now a days all the chips has combinational P seuential circuit. *o before we move
forward& we should know the definition of C3ropagation delayD in both types of circuits. 3lease read it once
because it will help you to understand the C;aximum "lock 2reuencyD concepts.
Propagation -elay in the %om"inational circ&its:
.ets consider a C:>TD gate and +nput,output waveform as shown in the figure
2rom the above figure& you can define
?ise Time tr!: The time reuired for a signal to transition from <78 of its maximum value to
N78 of its maximum value.
)all Time tf!: The time reuired for a signal to transition from N78 of its maximum value to <78
of its maximum value.
Propagation -elay tp>+B tp+>!: The delay measured from the time the input is at 678 of its
full swing value to the time the output reaches its 678 value.
+ want to rephrase above mention definition as
This value indicates the amount of time needed to reflect a permanent change at an output& if
there is any change in logic of input.
"ombinational logic is guaranteed not to show any further output changes in response to an input
change after tp.( or tp(. time units have passed.
*o& when an input T change& the output H is not going to change instantaneous. +nverter output is going
to maintain its initial value for some time and then its going to change from its initial value. After the
propagation delay !tp.( or tp(. % depends on what type of change% low to high or high to low#& the
inverter output is stable and is guaranteed not to change again until another input change ! here we are
not considering any *+,noise effect#.
Propagation -elay in the Se@&ential circ&its:

+n the seuential circuits& timing characteristics are with respect to the clock input. Hou can correlate it in
this way that in the combinational circuit every timing characteristic,parameter are with respect to the data
input change but in the seuential circuits the change +n the Cdata inputD is important but change in the
clock value has higher precedence. =.g in a positive%edged%triggered 2lip%flop& the output value will
change only after a presence of positive%edge of clock whether the input data has changed long time
ago.
*o flip%flops only change value in response to a change in the clock value& timing parameters can be
specified in relation to the rising !for positive edge%triggered# or falling !for negative%edge triggered# clock
edge.
Note1 *etup and hold time we have discussed in detail in the following blogs. *etup and (old
part<I *etup and (old part0I *etup and (old part$ . But 4ust to refresh your memories 1# & + have captured
the definition here along with Cpropagation delayD.
.ets consider the positive%edge flip%flop as shown in figure.
Propagation $elayB tp+> an$ tp>+ B has the same meaning as in combinational circuit U beware
propagation delays usually will not be eual for all input to output pairs.
Note1 +n case of flip%flop there is only one propagation delay i.e tclk%F !clockVF delay# but in case of
.atches there can be two propagation delays1 t"lk%F !clockVF delay# and t'%F !dataVF delay#. .ation
delay we will discuss later.
*o again let me rephrase the above mention definition
This value indicates the amount of time needed for a permanent change at the flip%flop output !F#
with respect to a change in the flip flop%clock input !e.g. rising edge#.
When the clock edge arrives& the ' input value is transferred to output F. After t"lkWF !here
which is euivalent to tp.(#& the output is guaranteed not to change value again until another clock edge
trigger !e.g. rising edge# arrives and corresponding +nput also.
Set&p time tsu! % This value indicates the amount of time "efore the clock edge that data
input 2 m&st be stable.
+ol$ time th! % This value indicates the amount of time after the clock edge that data input 2 m&st be
held stable.
The circuit must be designed so that the 2 flip flop input signal arrives at least Ctsu time units "efore the
clock edge and does not change until at least Cth time units after the clock edge. +f either of
these restrictions are violate$ for any of the flip4flops in the circ&itB the circ&it 'ill not operate
correctly. These restrictions limit the maximum clock freuency at which the circuit can operate !thats
what + am going to explain in the next section O #
The =a1im&m %loc/ )re@&ency for a circ&it:
+ hope you may be asking that why there is a need of explaining the combinational circuit propagation
delay here. "ombinational circuit is always independent of clock& so why combination circuit here. O
:ow the point is combinational circuit plays a very important role in deciding the clock freuency of the
circuit. .ets first discuss an example and try to calculate the circuit freuency& and then we will discuss
rest of the things in details. O
Note1 2ollowing diagram and numbers& + have copied from one of the pdf downloaded by me long time
back.
:ow lets understand the flow of data across these 2lip%flops.
.ets assume data is already present at input ' of flip%flop A and its in the stable form.
:ow "lock pin of 22 !2lip%2lop# A i.e "lk has been triggered with a positive clock edge !.ow to
high# at time C7nsD.
As per the propagation delay of the seuential circuit !tclk%F#& it will take at least <7ns for a valid
output data at the pin T.
o Aemember% +f you will capture the output before <7ns& then no one can give you the
guarantee for the accurate,valid value at the pint T.
This data is going to transfer through the inverter 2. *ince the propagation delay of C2D is 6ns& it
means& you can notice the valid output at the pin H only after <7nsP6nsL<6ns !with reference to the
positive clock edge% <7ns of 22 A and 6 ns of inverter#
o 3ractically this is the place where a more complex combinational circuit are present
between 0 22s. *o in a more complex design& if a single path is present between T and H& then the total
time taken by the data to travel from T to H is eual to the sum of the propagation delay of all the
combinational circuits,devices. !+ will explain this in more detail in the next section with more example#
:ow once valid data reaches at the pin H& then this data supposed to capture by 22 B at the next
clock positive edge !in a single cycle circuit#.
o We generally try to design all the circuit in such a way that it operates in a single clock
cycle. ;ultiple clock cycle circuit are special case and we are not going to discuss that right now !as
someone says U its out of scope of this blog O #
2or properly capturing the data at 22 B& data should be present and stable 0ns !setup time#
before the next clock edge as part of setup definition#.
*o it means between 0 consecutive positive clock edge& there should be minimum time difference of <7ns
P6ns P0ns L <Rns. And we can say that for this circuit the minimum clock period should be <Rns !if we
want to operate the circuit in single clock cycle and accurately#.
:ow we can generali9e this
;inimum "lock 3eriod L tclk%F !A# P tpd !2# P ts !B#
And C=a1im&m %loc/ )re@&ency 3 #A=in %loc/ Perio$!C
:ow at least we have some idea how to calculate the ;ax clock freuency or ;in "lock 3eriod. *o even
if we will forget the formula then we can calculate our self and we can also prove the logic behind that. .et
me use the same concept in few of the more complex design circuit or you can say the practical circuit.
=a1im&m %loc/ )re@&ency : Static Timing Analysis
STA! "asic Part 8"!
E1ample #: =&ltiple ))Ds Se@&ential %irc&it
+n a typical seuential circuit design there are often millions of flip%flop to flip%flop paths that need
to be considered in calculating the maximum clock freuency. This freuency must be
determined by locating the longest path among all the flip%flop paths in the circuit. "onsider the
following circuit.
There are three flip%flop to flip%flop paths !flop A to flop B& flop A to flop "& flop B to flop "#. )sing
an approach similar to whatever + have explained in the last section& the delay along all three
paths are1
TAB L t"lkWF!A# P ts!B# L N ns P 0 ns L << ns
TA" L t"lkWF!A# P tpd!M# P ts!"# L N ns P B ns P 0 ns L <6 ns
TB" L t"lkWF!B# P tpd!M# P ts!"# L <7 ns P B ns P 0 ns L <K ns
*ince the TB" is the largest of the path delays& the minimum clock period for the circuit is Tmin
L <Kns and the maximum clock freuency is <,Tmin L K0.6 ;(9.
E1ample (: %irc&it 'ith min an$ ma1 $elay Specification
.ets consider following circuit. :ow this circuit is similar to the normal 22 circuitry& only
differences are
=very specification has 0 values !;in and ;ax#.
There is a combinational circuit in the clock path also.
:ote1 if you are wondering why there are min and max value !or like from where these values
are coming& then you have to refer another blog#.
:ow lets understand the flow,circuit once again.
=very interconnect wire also has some delay& so you can see clock ".E will take some
time to reach the clock pin of the 22<.
Thats means with reference to original clock edge !lets assume at 7ns#& clock edge will
take minimum <ns and maximum 0ns to reach the clock pin of the 22<.
*o in the similar fashion& if we will calculate the total minimum delay and maximum
delay.
o +n data path 1 max delay L !0P<<P0PNP0#nsL0Kns
o +n data path 1 min delay L !<PNP<PKP<#nsL<Xns
o +n clock path1 max delayL !$PNP$#nsL<6ns
o +n clock path 1 min delay L !0P6P0#nsLNns
+n the last 0 example& there were no delays in the clock path& so it was easy to figure out
the minimum clock period. But in this example we have to consider the delay in the clock path
also.
*o for minimum clock period& we 4ust want to make sure that at 220& data should be
present at least CtsetupD time before positive clock edge !if its a positive edged triggered flipflop#
at the 220.
o *o "lock edge can reach at the 220 after Nns,<6ns !min,max# with the reference
of original clock edge.
o And data will take time <Xns,0Kns !min,max# with the reference of original clock
edge.
o *o clock period in all the B combinations are
"lock period !T<#L !;ax data path delay#%!max clock path delay#
PtsetupL0K%<6PBL<6ns
"lock period !T0#L !;in data path delay#%!max clock path delay#
PtsetupL<X%<6PBLRns
"lock period !T$#L !;ax data path delay#%!min clock path delay#
PtsetupL0K%NPBL0<ns
"lock period !TB#L !;in data path delay#%!min clock path delay#
PtsetupL<X%NPBL<<ns
*ince we want that this circuit should work in the entire scenario !all combination of data
and clock path delay#& so we have to calculate the period on the basis of that.
o :ow if you will see all the above clock period& you can easily figure out that if the
clock period is less than 0<ns& then either one or all of the scenarios,cases,combinations fail.
o So 'e can easily concl&$e that for 'or/ing of the entire circ&it properly
=inim&m %loc/ Perio$ 3 %loc/ perio$ T,! 3 =a1 $ata path $elay!4
min cloc/ path $elay!9tset&p3(:4E963(#ns
So in general:
=inim&m %loc/ Perio$ 3 =a1 $ata path $elay!4min cloc/ path $elay! 9 tset&p
And "=a1im&m %loc/ )re@&ency 3 #A=in %loc/ Perio$!C
E1ample ,: %irc&it 'ith m&ltiple %om"inational paths "et'een ( ))s:
:ow same scenario is with this example. + am not going to explain much in detail. Oust its like
that if you have multiple paths in between the 0%flipflops& then as we have done in previous
examples& please calculate the delays.
Then calculate the time period and see which one is satisfying all the condition. >r directly + can
say that we can calculate the "lock period on the bases of the delay of that path which has big
number.
=in %loc/ Time Perio$ 3 Tcl/4@ of 2))#! 9 ma1$elay of Path#B$elay of Path(! 9Tset&p
of 2)),!
E1ample 6: %irc&it 'ith -ifferent /in$ of Timing paths:
*ince + have mentioned that it has different kind of timing path& so you should know about the
timing paths. 2or that you can refer the !3ost link# post. After reading the Timing path& you can
easily figure out that in the above circuit there are B types of data paths and 0 clock paths
-ata path:
"# 3egister to register 4ath
o /% 56 /+ 56/" (2elay789:7"+ns*
o /" 56 /. 56 /% ( 2elay789;7"%ns*
%# Input pin0port to 3egister(flip5flop*
o /; 56 /. 56 /% ( 2elay7"9;7:ns*
o /; 56 /+ 56 /" ( 2elay7"9:7<ns*
+# Input pin0port to =utput pin0port
o /; 56 /8 56 /> (2elay7"9<9>7">ns*
.# 3egister (flip5flop* to =utput pin0port
o /" 56 /8 56 /> (2elay789<9>7%?ns*
o /% 56 /8 56 /> (2elay789<9>7%?ns*
%loc/ path:
/: 56 /" (2elay 7 %ns*
/: 56 /% (2elay 7%ns*
:ow few important points% This is not a full chip circuit. +n general& recommendation is that you
use registers at every input and output port. But for the time being& we will discuss this circuit&
considering this as full chip circuit. And you will how much analysis you have to do in this case.
:ext example& + will add the 22s !registers# at input and output port and then you come to know
the difference.
:ow lets *tudy this circuit in more details.
+n this circuit& we have to do the analysis in such a way that if we will apply an input at
3ort A& then how much time it will take to reach at output 3ort H. +t will help us to find out the
time period of clock.
>utput pin H is connected with a $input :A:' gate. *o if we want a stable out at H& we
have to make sure that all $ +nputs of :A:' gate should have stable data.
>ne input of :A:' gate is connected with +nput pin A with the help of )R.
o Time take by data to reach :A:' gate is <ns !gate delay of )R#
*econd input pin of :A:' gate is connected with output pin F of 2lip flop )0.
o Time take by data which is present at input ' of 22 U)0 to reach :A:' gate1
0ns!delay of )X#P6ns!Tc0 of 22 )0#LRns
Third input pin of :A:' gate is connected with the output pin F of 2lip 2lop )<.
o Time take by data which is present at input ' of 22 U)0 to reach :A:' gate1
0ns!delay of )X#P6ns!Tc0 of 22 )<#LRns
:ote1
+ know you may have doubt that why delay of )X comes in picture.
o With reference to the clock edge at ".E pin& we can receive the data at :A:'
pin after Rns only !'ont ask me% why we cant take reference in negative?#
;ay be you can ask why we havent consider the setup time of 22 in this calculation.
o +f in place of :A:' gate& any 22 would there then we will consider the setup. We
never consider the setup and Tc0 !"lk%0%F# values of same 22 in the delay calculation at the
same time. Because when we are considering "lk%0%F delay& we assume that 'ata is already
present at input 3in ' of the 22.
*o Time reuired for the data to transfer from input !A# to output !H# 3in is the maximum of1
3in03in 'elay L )RP)6P)K L <PNPKL<Kns
"lk0>ut !through )<# delay L )X P)<P)6P)KL0P6PNPKL00ns
"lk0>ut !through )0# delay L )X P)0P)6P)KL0P6PNPKL00ns.
So o&t of this %l/(O&t -elay is =a1im&m.
2rom the above *tudy& you can conclude that data can be stable after Rns at the :A:' gate and
maximum delay is 00ns. And you can also assume that this much data is sufficient for calculating the ;ax
"lock 2reuency or ;inimum Time 3eriod. But thats not the case. *till our analysis is half done in
calculating the ;ax%clock%freuency.
As we have done in our previous example& we have to consider the path between 0 flip%flops also. *o the
paths are1
2rom )< to )0 !Aeg<Aeg0#
o 3ath delayL 0ns !'elay of )X# P 6ns !Tclk0F of )<#PRns !'elay of )B#P$ns !*etup of )0#
U 0ns !'elay of )X#L<Rns%0nsL<6ns
2rom )0 to )< !Aeg0Aeg<#
o 3ath delay L 0ns !'elay of )X# P Tclk0F of )0 !6ns# P 'elay of )$ !Xns# P setup of )<
!$ns# U 'elay of )X !0ns# L<Xns %0ns L <Kns.
:ote1
+ am sure you will ask why did + subtract C'elay of )XD from the above calculation 1# because
'elay of )X is common to both the launch and capture path !+n case you want to know whats .aunch and
capture path please follow this post#. *o we are not supposed to add this delay in our calculation. But 4ust
to make it clear& + have added as per the previous logic and then subtracted it to make it clear.
*o now if you want to calculate the maximum clock freuency then you have to consider all the delay
which we have discussed above.
*o
;ax "lock 2re L <, ;ax !Aeg<Aeg0& Aeg0Aeg<& "lk0>utJ<& "lk0>utJ0& 3in03in#
L <, ;ax !<6& <K& 00& 00& <K#
L<,00 LB6.6;(9
E1ample 8: %irc&it 'ith -ifferent /in$ of Timing paths 'ith ?egister at *np&t an$
o&tp&t ports:

+n this example& we have 4ust added 0 22s )X at +nput pin and )N at output pin. :ow for this circuit& if we
want to calculate the max clock freuency then its similar to example <.
There are R 2lip flop to flipflop paths
"# /: 56 /. 56 /%
o 2elay 7 8ns9;ns9+ns7"8ns
%# /: 56 /+ 56 /"
o 2elay 7 8ns9:ns9+ns7">ns
+# /: 56 /8 56 /<
o 2elay 7 8ns9<ns9+ns7";ns
.# /" 56 /. 56 /%
o 2elay 7 8ns 9;ns 9+ns 7 "8ns
8# /" 56 /8 56 /<
o 2elay7 8ns9<ns9+ns7";ns
># /% 56 /8 56 /<
o 2elay78ns9<ns9+ns7";ns
;# /% 56 /+ 56 /"
o 2elay78ns9:ns9+ns7">ns
*ince the maximum path delay is <Rns&
The ;inimum clock period for the circuit should be Tmin L <R ns
And the ;aximum clock freuency is <,Tmin L 6X.X ;(9.
)i1ing Set&p an$ +ol$ 5iolation : Static Timing
Analysis STA! Basic Part :a!
Ae have discussed few basics about the MSetup and "old violationN in last few
posts. .nce designer6s fgured out the nu&ber of setup and hold violation then their
ne2t challenge is= M"ow to f2 these violationsN.
5@9 tools usuall! take care but still !ou have to provide the input (or sa! proper
switch) to f2 these violations. That &eans / can sa! that MTi&ing;Iouting Tools are
enough intelligent to solve &ost of the ti&ing violation% but still Tools never be &ore
intelligent than the hu&an brainN.
There are di8erent wa!s to f2 these issues and ever! wa! has the reason for that.
So designers should know what e2actl! the reason of /ssue and what are the
di8erent &ethods (priorit! wise) or at least di8erent 5@96s switch for f2ing those
violation.
/n this series we will discuss the following things one b! one.
:asic of 'i2ing the S5TJP and ".L@ violations.
o 4ore 52a&ples here. ?er! less theor!.
o 'ew shortcuts;for&ula;tricks to fnd out whether these violations are
f2able or not. 9nd /f f2able% then a rough idea where and how.
@i8erent wa!s to f2.
o Their basics or sa! ph!sics;5ngineering of using that &ethod for f2ing.
o Ahich &ethod is good and in what scenario !ou can use the&.
:efore that) /f still !ou have an! doubt regarding the Setup and "old then please
refer following post.
Ahat e2actl! is the setup and hold P please refer the previous blog.
Ahat are setup and hold violation P please refer the previous blog.
*asi$s o% Fi+in, the -./012 and 34L56 (iolations.
Let6s start with following @iagra& and consider this as co&&on for ne2t few
e2a&ples.
/n the following e2a&ples we will pick di8erent values of Setup;"old values of
<apture '' and <o&binational Path dela!. Through these e2a&ple we will stud! )
"ow the setup and hold violations are dependent to each other and on the dela! of
the circuit. /f these things are clear then it6s ver! eas! for !ou to understand )) how
can we f2 the violations and if we are using an! particular &ethods% then wh!7
Example 1:
&peci9cation of the FF %ircuit
Setup "old <lock period Tck#1 dela! *et @ela! <o&binational Logic @ela!
#ns 1ns 10ns 0ns (/deal) 0ns (/deal) 0.-ns
Let6s discuss the +ow of the data fro& ''1 to ''#
@ata is going to launch fro& ''1 at Five <lock 5dge at 0ns and it will reach to
''# after 0.-ns (co&binational logic dela! onl!).
This data is going to capture at ''# at Five <lock 5dge at 10ns.
As per the &etup de9nition% data should be stable #ns (Setup ti&e of ''#)
at ''# before the Five <lock 5dge (which is at 10ns)
o /n the above case P data beco&e stable H.-ns before the <lock edge at
10ns (10ns P 0.-ns). That &eans it satisf! the Setup condition. N' &E,@#
)'FA,'N.
9t the ''1 P second set of data is going to launch at tE10ns and it will reach
the ''# in another 0.-ns% &eans at tE10.-ns.
This second set of data is going to update;override the frst set of data.
As per the (old >e9nition% data should be stable till 1ns ("old ti&e of ''#)
at ''# after the clock edge (which is at tE10ns)
o /n the above case P frst set of data is going to override b! second set
of data at 10.-ns (&eans Oust after 0.-ns of the Five <lock edge at ''#). This &eans
it is not satisf!ing the hold condition.('F> )'FA,'N.
To f2 this "old violation P we have to increase the dela! of the @ata path so that the
second set of data should not reach before tE11ns (10nsF1ns). That &eans the
&ini&u& dela! of the <o&binational Logic Path should be 1ns for *. ".L@
?/.L9T/.*.
That &eans if !ou want to f2 the ".L@ violation% !ou can increase the @ela! of the
@ata path b! an! &ethod (we will discuss all those &ethods in detail P 3ust keep
s&all patience).
:ut it doesn6t &ean that !ou can increase the @ela! b! an! ?alue. Let6s assu&e that
!ou have increased the dela! of co&binational path b! adding e2tra bu8er (with
dela! of ,.-ns). *ow new specifcations are

&peci9cation of the FF %ircuit
Setup "old <lock period Tck#1 dela! *et @ela! <o&binational Logic @ela!
#ns 1ns 10ns 0ns (/deal) 0ns (/deal) E0.-nsF,.-nsEHns

As per the &etup de9nition% data should be stable #ns (Setup ti&e of ''#) before
the <lock 5dge (at ''# which is at 10ns) and with the updated specifcation P data
will be stable at tEHns% Oust 1ns before the <lock edge at tE10ns at ''#. That
&eans it is not satisf!ing the Setup condition. &E,@# )'FA,'N.
Since @ata path dela! is &ore than 1ns% there is N' ('F> )'FA,'N (Oust we
have discussed few paragraph above)
So it &eans that if we want to f2 the setup violation% the @ela! of the co&binational
path should not be &ore then ,ns (10ns P #ns). 4eans ,ns is the &a2i&u& value of
the @ela! of the <o&binational Logic path for *. S5TJP ?/.L9T/.*.
&o we can generaliGe this H
'or *. ".L@ and S5TJP ?/.L9T/.*% the dela! of the path should be in between 1ns
and ,ns.
'C
'or ?iolation free <ircuit=
?in dela! of %ombinational path 6 (old time of %apture FF.
?ax dela! of %ombinational path I %loc3 #eriod - &etup time of %apture
FF.
Example :
&peci9cation of the FF %ircuit
Setup "old <lock period Tck#1 dela! *et @ela! <o&binational Logic @ela!
Kns -ns 10ns 0ns (/deal) 0ns (/deal) 0.-ns
'low of the data fro& ''1 to ''#=
@ata is going to launch fro& ''1 at <lock 5dge at 0ns and it will reach to ''#
after 0.-ns (co&binational logic dela! onl!).
This data is going to capture at ''# at <lock 5dge at 10ns.
As per the &etup de9nition% data should be stable Kns (Setup ti&e of ''#)
before the <lock 5dge (which is at 10ns)
o /n the above case P data beco&e stable H.-ns before the <lock edge at
10ns (10ns P 0.-ns). That &eans it satisf! the Setup condition. N' &E,@#
)'FA,'N.
9t the ''1 P second set of data is going to launch at tE10ns and it will reach
the ''1 in another 0.-ns% &eans at tE10.-ns.
This second set of data is going to update;override the frst set of data.
As per the (old >e9nition% data should be stable till -ns ("old ti&e of ''#)
after the clock edge (which is at tE10ns) at ''#
o /n the above case P frst set of data is going to override b! second set
of data at 10.-ns (&eans Oust after 0.-ns of the <lock edge at ''#). This &eans it is
not satisf!ing the hold condition. ('F> )'FA,'N.
To f2 this "old violation P (9s per the previous e2a&ple) we &a! increase the dela!
of the @ata path% so that the second set of data should not reach before tE1-ns
(10nsF-ns). That &eans the &ini&u& dela! of the <o&binational Logic Path should
be -ns for *. ".L@ ?/.L9T/.*.
:ut *ow if !ou will verif! the Setup condition once again (with co&bination dela! of
-ns) which we have assu&ed for f2ing the hold violation) then !ou co&e to know
that data is going to stable onl! after -ns (&eans 10ns)-ns E -ns before the clock
edge at t)10ns). :ut as per the setup condition data should be stable before Kns. So
it &eans now it6s not satisf!ing Setup <ondition. 4eans S5TJP ?/.L9T/.*.
So in this scenario% we can6t f2 the setup and hold violation at the sa&e ti&e b!
adOusting the dela! in the co&binational logic.
Jou can also see it directl! with the help of minimum and maximum 5alue
of combinational dela!.
?in dela! 6 (old time of %apture FF 0means 8ns1
?ax >ela! I %loc3 #eriod H &etup time of capture FF 0?eans $0ns H /ns +
7ns1
&o ?in dela! 6 8ns and ?ax >ela! I 7ns which is not possible.
!o" the point is ho" to #x these $iolations% &ctually this is a non'#xa(le
issue until you )ust change the clock frequency or replace the FF "ith
lesser setup*hold $alue.
Let &e e2plain this.
4in dela! has dependence onl! on "old ti&e% which is f2ed for a particular ''.
4a2 dela! has dependence on # para&eters P <lock Period and Setup ti&e ) where
Setup ti&e is f2ed for a particular ''.
So if !ou can change the '' with lower setup;hold violation% then !ou can f2 this
issue. :ut in case if that6s not possible then we have to change the <lock period.
/n case we are changing the <lock period=
Keep -- ?in dela! 6+ 8ns 0 No ('F> )iolation1
Setup violation is b! Kns)-ns E1ns (KnsE Setup ti&e and -ns E co&binational
dela!). Ahat if we will increase the <lock period b! 1ns. 4eans *ew clock period
should be C 11ns.
So for <lock Period 11ns=
4a2 dela! QE <lock period (11ns) P Setup ti&e (Kns) E-ns.
*ow ) 4a2 @ela!E4in @ela! E -ns. (*either "old nor Setup ?iolation.)
;e can generaliGe-
'or ?iolation 'ree <ircuit
%loc3 #eriod 6+ &etup time - (old time.
*ummary of this 3ost1
?in dela! of %ombinational path 6 (old time of %apture FF.
?ax dela! of %ombinational path I %loc3 #eriod - &etup time of %apture
FF.
%loc3 #eriod 6+ &etup time - (old time.
/n the ne2t part we will discuss few &ore e2a&ples with &ore restrictions. Like)
Ahat if we can6t reduce the @ela! in the @ata path7
)i1ing Set&p an$ +ol$ 5iolation : Static Timing
Analysis STA! Basic Part :"!
/n the last part;post we have discussed # e2a&ples with di8erent
specifcations (:oth net dela! and Tck#D were ideal &eans 0ns) and co&e to
know that for ?iolation free <ircuit% following conditions should be satisfed.
?in dela! of %ombinational path 6 (old time of %apture FF.
?ax dela! of %ombinational path I %loc3 #eriod - &etup time of
%apture FF.
%loc3 #eriod 6+ &etup time - (old time.
/n this post we will discuss few &ore e2a&ples with &ore restrictions. Like
Ahat if we can6t reduce the @ela! of @ata path7
Let6s consider the following fgure co&&on to all e2a&ples until unless it6s
specifed
Example 3:
Speciication o the 00 Circ!it
Set!p "old Cloc/ period Tc/21 delay @et )elay Com#inational -ogic )elay
3ns 2ns 1<ns <ns 6*deal7 <ns 6*deal7 .ns 6canKt #e !rther red!ced74
.n the basic of last post Rlet6s start with checking few conditions directl!.
<lock Period <ondition= (Satisfed)
Setup ti&e F"old ti&e E -ns
<lock period E 10ns
<lock Period C Setup ti&e F"old ti&e (10C -)
4in dela! ; "old <ondition= (Satisfed)
<o&binational @ela! (-ns) C "old ti&e.
4eans ) *. ".L@ ?/.L9T/.*
4a2 @ela! ; Setup <ondition= (Satisfed)
<o&binational dela! (-ns) Q <lock period (10ns) P Setup (ns)
4eans ) *. S5TJP ?/.L9T/.*.
This e2a&ple is Oust to refresh !our &e&ories about the previous post.
Example 7=
Speciication o the 00 Circ!it
Set!p "old Cloc/ period Tc/21 delay @et )elay Com#inational -ogic )elay
(ns 3ns 1<ns <ns 6*deal7 <ns 6*deal7 ;ns 6canKt #e !rther red!ced74
<lock Period <ondition= (Satisfed)
Setup ti&e F"old ti&e E 4nsFns E Lns
<lock period E 10ns
<lock Period C Setup ti&e F "old ti&e (10 C L)
4in dela! ; "old <ondition= (Satisfed)
<o&binational @ela! (,ns) C "old ti&e (ns)
4eans ) *. ".L@ ?/.L9T/.*
4a2 @ela! ; Setup <ondition= (*ot Satisfed)
<o&binational dela! (,ns) s Not Fess ,han M<lock period (10ns) P Setup
(4ns)N
?eans - &E,@# )'FA,'N.
Since we can6t change this <o&binational dela! and also Setup ti&e for the
''% so we have to think so&ething else. 3. Since we can6t touch the data path%
we can tr! with clock path.
'low of the data fro& ''1 to ''#=
Let6s assu&e that !ou have added one bu8er of TScapture dela! in the
clock path between the ''1 and ''#.
@ata is going to launch fro& ''1 at <lock 5dge at 0ns and it will reach
to ''# after ,ns (co&binational logic dela! onl!).
This data is going to capture at ''# at <lock 5dge at 10nsFTScapture.
(because of @ela! added b! :u8er).
As per the &etup de9nition% data should be stable 4ns (Setup ti&e
of ''#) before the <lock 5dge at ''# and in the above case clock edge is at
tETScaptureF10ns.
&o, for No &etup 5iolation:
EC ,ns (<o&binational @ela!) Q TScaptureF10ns (clock period) P 4ns (Setup
Ti&e of ''#)
EC 1#ns P 10ns Q TScapture
EC ,Lcapture 6 2ns.
FetMs assume if m! ,Lcapture + 3ns. ,hen N' &E,@# )'FA,'N.
*ow% recheck the "old violation.
9t the ''1 P second set of data is going to launch at tE10ns and it will
reach the ''# in another ,ns% &eans at tE1,ns.
This second set of data is going to update;override the frst set of data
present at ''#.
As per the (old >e9nition% data should be stable till ns ("old ti&e
of ''#) after the clock edge at ''# (Ahich is at tE10nsFnsE1ns P where
ns is the TScapture).
That &eans @ata should be re&ain stable till tE1nsFnsE1Kns.
o /n the above case the second set of data is going to override onl!
after tE1,ns. That &eans frst set of data re&ain Stable till 1Kns. 4eans N'
('F> )'FA,'N.
Fet me NeneraliGe this concept:
/ a& sure% few people &a! have 1uestion that what will happen if we will add
the bu8er in the Launch path. Let6s discuss that. Please consider the
following @iagra& for this. /n this Launch <lock path has a bu8er with a dela!
of MTSlaunchN and <apture clock path has another bu8er of dela!
MTScaptureN.
&peci9cation of the FF %ircuit
&etup TSsetup
(old TShold
%loc3 #eriod <lkSperiod
,c32: >ela! 0 (/deal)
Net >ela! 0 (/deal)
%ombinational Fogic >ela!
0bDw 2FFs1
Td
Faunch %loc3 path >ela! TSlaunch
%apture %loc3 path >ela! TScapture
Let6s understand the data +ow fro& ''1 to ''#
@ata is going to launch fro& ''1 at <lock 5dge at TSlaunch and it will
reach to ''# after Td (co&binational logic dela! onl!) that &eans tE MTd F
TSlaunchN.
This data is going to capture at ''# at <lock 5dge at M<lkSperiod F
TScaptureN
As per the &etup de9nition% data should be stable MTSsetupN (Setup
ti&e of ''#) ti&e before the <lock 5dge at ''#
o 4eans data should reach at ''# before tE M<lkSperiod F
TScapture P TSsetupN.
&o For N' &E,@# )'FA,'N:
EC TSlaunch F Td Q <lkSperiod F TScapture P TSsetup
EC ,d I %l3L#eriod - 0,Lcapture - ,Llaunch1 H ,Lsetup
9t the ''1 P second set of data is going to launch at tE M<lkSPeriod F
TSlaunchN and it will reach the ''# in another Td% &eans at tEN <lkSPeriod F
Td F TSlaunchN.
This second set of data is going to update;override the frst set of data
present at ''#.
As per the (old >e9nition% data should be stable till MTSholdN ("old
ti&e of ''#) ti&e after the <lock edge (which is at tE M<lkSPeriod F
TScaptureN).
o 4eans *e2t set of data should not reach ''# before tE
M<lkSPeriod F TScapture F TSholdN
&o For N' ('F> )'FA,'N:
EC <lkSPeriod F Td F TSlaunch C <lkSPeriod F TScapture F TShold
EC ,d 6 0,Lcapture - ,Llaunch 1 - ,Lhold
&ummar! of this post:
<lock Period <ondition=
%loc3 period 6 &etup time - (old ,ime
4a2 @ela!; Setup <ondition=
,d I %l3L#eriod - 0,Lcapture - ,Llaunch1 H ,Lsetup
4in @ela! ; "old <ondition=
,d 6 0,Lcapture - ,Llaunch 1 - ,Lhold
)i1ing Set&p an$ +ol$ 5iolation : Static Timing
Analysis STA! Basic Part :c!
*n the last part'post we have disc!ssed 2 more e&amples with dierent speciications with more
restrictions 6Both net delay and Tc/2P were ideal means <ns7 and ig!re o!t that i yo! want to
i& the violation #y increasing'decreasing the delay in the data path then ollowing condition
sho!ld #e satisied4
Min dela7 o% 8o#9inational )ath : 3old ti#e o% 8a)ture FF.
Ma+ dela7 o% 8o#9inational )ath ; 8lo$< 2eriod = .etu) ti#e o% 8a)ture FF.
8lo$< 2eriod : .etu) ti#e > 3old ti#e.
B!t in case i yo! canKt to!ch the data path and yo! have to increase'decrease the delay in the
cloc/ path 6means #etween 2Cl/ pin to -a!nch 00 cloc/ pin3 Or #etween 2Cl/ pin and capt!re
00 cloc/ pin37B then ollowing conditions sho!ld satisied4
+a& )elay' Set!p Condition:
0d ; 8l<?2eriod > (0?$a)ture = 0?laun$h) @ 0?setu)
+in )elay ' "old Condition:
0d : (0?$a)ture = 0?laun$h ) > 0?hold
,here:
Td -> Com#inational path delay 6#etween the 2 00s7
TGcapt!re -> )elay o circ!it present #etween 2Cl/ pin and capt!re 00 cloc/ pin3
TGla!nch -> )elay o circ!it present #etween 2Cl/ pin to -a!nch 00 cloc/ pin3
*n this post we will disc!ss ew more e&amples with more restrictions4
-etKs consider the ollowing ig!re common to all e&amples !ntil !nless itKs speciied4
/+a#)le A:
Speciication o the 00 Circ!it
Set!p "old Cloc/ period Tc/21 delay @et )elay Com#inational -ogic )elay
3ns 2ns 1<ns <ns 6*deal7 <ns 6*deal7 11ns 6canKt #e !rther red!ced7

On the #asic o last post QletKs start with chec/ing ew conditions directly4
Cloc/ Period Condition: 6Satisied7
Set!p time ?"old time > .ns
Cloc/ period > 1<ns
Cloc/ Period > Set!p time ?"old time 61<> .7
+in delay ' "old Condition: 6Satisied7
Com#inational )elay 611ns7 > "old time4
+eans - @O "O-) $*O-8T*O@
+a& )elay ' Set!p Condition:
Com#inational delay 611ns7 Bs Not Less 0han 2Cloc/ period 61<ns7 R Set!p 63ns73
Means = ./012 CB4L'0B4N.
Since adding delay in the data path is not going to i& this violation and we canKt red!ce the
com#inational delay4 So as we have disc!ssed in o!r last postB we will try with Cloc/ path4
0rom the last postB i TGcapt!re is the delay o #!er which is inserted #etween the C-D and
Capt!reKs 00 and TGla!nch is the delay o #!er which is inserted #etween the C-D and
-a!nchKs 00B then
+a& )elay 'Set!p condition is :
0d ; 8lo$< 2eriod > (0?$a)ture = 0?laun$h) @ 0?setu)
>> 11ns S 1<ns R 3ns ? 6TGcapt!re - TGla!nch7
>> 11ns S 9ns ? 6TGcapt!re - TGla!nch7
>> (ns S 6TGcapt!re - TGla!nch7
@ow we can choose any com#ination o TGcapt!re and TGla!nch s!ch that their dierence
sho!ld #e less than (ns4
Note: Cemem#er in the design i yo! are i&ing the violation #y increasing or decreasing the
delay in the Cloc/ path then always preer not to play too m!ch with this path4
* never preer to !se TGla!nch in this case 60or set!p i&ingB * ignore to !se TGla!nch74
So letKs ass!me TGla!nch ><ns and TGcapt!re > .ns
Then
11ns S 9ns ? .ns #eans no .etu) Ciolation.
8he$< on$e a,ain the 3old $ondition.
+in delay ' "old Condition:
0d : (0?$a)ture = 0?laun$h ) > 0?hold
>> 11ns > 6TGcapt!re - TGla!nch 7 ? TGhold
>> 11ns > .ns ? 2ns
>> 11ns > 9ns R Means No 3old Ciolation.
/+a#)le !:
Speciication o the 00 Circ!it
Set!p "old Cloc/ period Tc/21 delay @et )elay Com#inational -ogic )elay
3ns .ns 1<ns <ns 6*deal7 <ns 6*deal7 2ns 6canKt #e !rther red!ced and
we canKt increase the delay in the
data path #y any methods7
-etKs chec/ the conditions directly4
Cloc/ Period Condition 6Satisied7:
Set!p time ?"old time > ;ns
Cloc/ period > 1<ns
Cloc/ Period > Set!p time ?"old time 61<ns > ;ns 7
Means we $an %i+ (iolationsD i% there is an7.
+a& )elay' Set!p Condition 6Satisied7:
0d ; 8l<?2eriod > (0?$a)ture = 0?laun$h) @ 0?setu)
Com#inational )elay > 2ns
There is no delay in the cloc/ path till nowB so TGcapt!re>TGla!nch><ns
>> Td 62ns7 S Cl/Gperiod 61<ns7 ? <ns R TGset!p 63ns7
>> 2ns S 9ns R Means N4 ./012 Ciolations
+in )elay ' "old Condition 6@ot Satisied7:
0d : (0?$a)ture = 0?laun$h ) > 0?hold
Com#inational )elay > 2ns
There is no delay in the cloc/ path till nowB so TGcapt!re>TGla!nch><ns
>> Td 62ns7 is not ,reater than <ns ? TGhold 6.ns7
Means 34L5 CB4L'0B4N
Since we canKt ma/e change in the delay pathB so we have to to!ch the cloc/ path4
0or "old i&ing -
>> Td > 6TGcapt!re - TGla!nch 7 ? TGhold
>> 2ns > 6TGcapt!re - TGla!nch 7 ? .ns
>> -3ns > 6TGcapt!re - TGla!nch 7
0or Satisying the a#ove e1!ation TGla!nch sho!ld have more val!e in comparison to TGcapt!re4
,e can choose any com#ination o TGcapt!re and TGla!nch4
Note: Cemem#er in the design i yo! are i&ing the violation #y increasing or decreasing the
delay in the Cloc/ path then always preer not to play too m!ch with this path4
* will never preer to !se TGcapt!re in this case 60or "old i&ingB * ignore to !se TGcapt!re74
So letKs ass!me TGcapt!re ><ns and TGla!nch > (ns
Then
TGla!nch ? Td > .ns 6hold time7
>> (ns ?2ns > .ns N4 34L5 Ciolation.
8he$< on$e a,ain the .etu) 8ondition:
Td S Cloc/ Period ? 6TGcapt!re - TGla!nch7 R TGset!p
>> 2ns S 1<ns ? <ns -(ns R 3ns
>> 2ns S 3ns Means No .etu) Ciolation.
Note: 6TGcapt!re - TGla!nch7 also /nown as C-OCD SD%,4 * will e&plain this later in this #log4
Cight nowB itKs O!st or yo!r ino4
/+a#)le E:
Speciication o the 00 Circ!it
Set!p "old Cloc/ period Tc/21 delay @et )elay Com#inational -ogic )elay
5ns .ns 1<ns <ns 6*deal7 <ns 6*deal7 <4.ns
Note: this is the same e&ample which we have disc!ssed in the part-5a4 -etKs chec/ all the
conditions one #y one4
Cloc/ Period Condition 6@ot Satisied7:
Set!p time ?"old time > 11ns
Cloc/ period > 1<ns
Cloc/ Period is not ,reater than Set!p time ?"old time
Means we $anFt %i+ (iolationsD i% there is an7.
*ut still we will tr7 on$e a,ain with all other $onditionsD Gust to )ro(e that a9o(e #ention
$ondition should 9e true %or %i+in, the (iolations.
+a& )elay' Set!p Condition 6Satisied7:
0d ; 8l<?2eriod > (0?$a)ture = 0?laun$h) @ 0?setu)
Com#inational )elay > <4.ns
There is no delay in the cloc/ path till nowB so TGcapt!re>TGla!nch><ns
>> Td 6<4.ns7 S Cl/Gperiod 61<ns7 ? <ns R TGset!p 65ns7
>> <4.ns S (ns R Means N4 ./012 Ciolations
+in )elay ' "old Condition 6@ot Satisied7:
0d : (0?$a)ture = 0?laun$h ) > 0?hold
Com#inational )elay > <4.ns
There is no delay in the cloc/ path till nowB so TGcapt!re>TGla!nch><ns
>> Td 6<4.ns7 is not ,reater than <ns ? TGhold 6.ns7
Means 34L5 CB4L'0B4N
* yo! want to i& the "old violationB then we have already seen that #y increasing'decreasing the
delay in the data path it canKt #e i&ed4 %ven i this will i&edB then Set!p violation will occ!r4
-etKs Try with TGcapt!re or TGla!nch4 +eans #y adding delay in the cloc/ circ!it4
8s per the a#ove e1!ations'conditions and corresponding val!es:
+a& )elay' Set!p Condition :
Td S Cloc/ Period ? 6TGcapt!re - TGla!nch7 R TGset!p
>> Td S 1<ns -5ns ? 6TGcapt!re - TGla!nch7
>> Td S (ns ? 6TGcapt!re - TGla!nch7
+in )elay ' "old Condition:
Td > 6TGcapt!re - TGla!nch 7 ? TGhold
>> Td > 6TGcapt!re - TGla!nch 7 ? .ns
Cemem#er all 3 varia#le TdBTGcapt!reBTGla!nch are positive n!m#er4
Possi#le val!es o 6TGcapt!re - TGla!nch7 > ?'-8 6where 8 is a positive n!m#er7
"ase 1( ()*captu!e - )*launch) = ++
>> Td S (ns?8 - Condition 6a7
>> Td> .ns?8 R Condition 6#7
Satisying #oth the conditions 62a3 and 2#3 7 not possi#le or any ?ive val!e o 84
"ase 1( ()*captu!e - )*launch) = -+
>> TdS (ns-8 >> Td?8 S (ns - Condition 6a7
>> Td> .ns-8 >> Td ?8 > .ns - Condition 6a7
Satisying #oth the conditions 62a3 and 2#37 not possi#le or any ?ive val!e o 84
That meansB * am s!ccess!lly a#le to prove that i ollowing condition is not satisied then yo!
canKt i& any type o violation #y increasing'decreasing delay in either dataGpath or cloc/Gpath4
Cloc/ Period > Set!p time ? "old time4
.u##ar7 o% this )ost:
Cloc/ Period Condition:
8lo$< )eriod : .etu) ti#e > 3old 0i#e
For %i+in, an7 t7)e o% (iolation (without $han,in, 8lo$< )eriod) = 0his $ondition should 9e
satis%ied.
+a& )elay' Set!p Condition:
0d ; 8l<?2eriod > (0?$a)ture = 0?laun$h) @ 0?setu)
For Fi+in, the .etu) Ciolation @ 'lwa7s )re%er 0?$a)ture o(er 0?laun$h
+in )elay ' "old Condition:
0d : (0?$a)ture = 0?laun$h ) > 0?hold
For Fi+in, the hold Ciolation @ 'lwa7s )re%er 0?laun$h o(er 0?$a)ture.
Till now we have disc!ssed almost all the necessary #asic o i&ing the violation o Set!p and
"old time4 To! have #een noticed that everywhere * have tal/ed a#o!t the increasing'decreasing
the delay4 * * have mentioned anywhere adding'removing the #!erB that also mean
increasing'decreasing the delay4
There are several other ways thro!gh which yo! can increase'decreasing the delay o the circ!it4
*n the ne&t post we will disc!ss
)ierent methods or increasing'decreasing the delay in a circ!it'path4
8lso try to capt!re the #asics #ehind a#ove said methods one #y one

Effect of Wire >ength On the Sle': Static Timing

Analysis STA! Basic Part4<a!
Till now we have discussed the /deal scenario for few of the cases. Like *o <lock)to)
D dela!% *o *et @ela!. :ut now we will discuss about those para&eter also.
'irst understand;revise what are the di8erent t!pes or for&s of @ela! into a circuit.
/n ''s=
<lock to D dela!
o Propagation dela! of se1uential +ip +op
Ti&e taken to charge and discharge the output load (capacitance) at Pin D.
o Iise ti&e and 'all ti&e dela!
<o&binational <ircuit=
<ell dela!
o @ela! contributed b! $ate itself.
o T!picall! defned as -0T input pin voltage to -0T output voltage.
o Jsuall! a function of :oth .utput Loading and /nput Transition ti&e.
o <an be divide into propagation dela! and transition dela!.
o Propagation dela! is the ti&e fro& input transition to co&pletion of a
specifc T (e.g 10T) of the output transition.
Propagation dela! is function of output loading and input
transition ti&e.
o Transition @ela! is the ti&e for an output pin to change the stage.
Transition dela! is function of capacitance at the output pin and
can also be a function of input transition ti&e.
o Ti&e taken to charge and discharge the output load (capacitance) of
the <ell output.
*et @ela!=
I< dela!.
o Long wire has &ore dela! in co&parison to short wire.
o 4ore coupling &eans &ore dela!.
*ow we will discuss di8erent techni1ues to increase or decrease the dela! in the
design. Ae will also discuss the basics of di8erent techni1ues% which will help us to
understand wh! we are using an! particular techni1ue.
*ow we have to see what best we can do to re&ove these violations or as e2plained
earlier P "ow can we increase or decrease the dela! of the clock or data path in the
design. /f / will ask !ou% then &ight be !ou can tell &e 10 wa!s to do so. :ut / don6t
want to e2plain in that wa!. Let6s start one b! one with basics and then in the last /
will brief all those points.
Let6s talk about the Transition dela! frst. There are # t!pes of transition dela!s. Iise
@ela! and 'all dela!. /n ter&s of defnition
Cise ,ime >ela! 0tr1: The ti&e re1uired for a signal to transition fro& 10T
of its &a2i&u& value to H0T of its &a2i&u& value.
Fall ,ime >ela! 0tf1: The ti&e re1uired for a signal to transition fro& H0T
of its &a2i&u& value to 10T of its &a2i&u& value.
:asicall! these ti&es (rise ti&e and fall ti&e) are related to the <apacitance
<harging and @ischarging ti&e.
So when capacitance is charging Oust because of an! change in the input voltage
then ti&e taken b! capacitance to reach fro& 10T to H0T of &a2i&u& value is
known as rise ti&e. Since this ti&e (rise ti&e) is going to introduce the dela! in the
circuit in co&parison to the /deal scenario (<apacitance charging ti&e is Uero P /t
can charge instantl!)% it6s known as Iise Ti&e @ela! also.
Si&ilarl!% during the discharging of the capacitance fro& H0T to 10T of its
&a2i&u& value% it6s going to add one &ore dela! P known as 'all Ti&e @ela!.
'ollowing fgure is Oust an e2a&ple of rise ti&e and fall ti&e.
Note: ,ransition time is also 3nown as &lew.
So we can sa! that <apacitance (and the associated Iesistance) is the
culprit. 9nd if we can pla! with capacitance;resistance% we can increase and
decrease Transition @ela!.
*ow% whenever we are talking about an! signal which is changing its state fro& M0N
to M1N or fro& M1N to M0N% we are sure that it can6t be ideal (/deal &eans its changing
its state in Uero M0N ti&e). /f !ou have an! doubt on this state&ent then defantl! /
have to ask !ou to read so&e ver! basic books once again.
5ver! Mstate changing signalN has a Slew *u&ber (co&&on na&e of Iise ti&e and
'all ti&e) associated with itself at an! given point of ti&e.
E+ect of ,ire length on the Sle" -transition time.:
/n the below fgure !ou can observe% how the step wavefor& (consider this as ideal
one) degrades fro& the start to the end of the wire (color coding can help !ou to
understand) and this is resulting a considerable a&ount of dela! for long wires. That
&eans if wire length is less% then degradation of wavefor& be less% &eans less
e8ective dela! and ?ice)versa. Ae can conclude fro& this)
Of we want to increase the dela!- we can increase the wire length and
5ice 5ersaP
4ore si&ulation results !ou can see fro& this pictureR ('ollowing picture / have
copied fro& book M@55P SJ:4/<I.* <4.S @5S/$*N written b! 5.Sicard% S. @el&as)
:endhia )
/ a& sure !ou can cross 1uestion &e that wh! this degradation is happing. Si&ple
9ns is ) !ou can &odel a wire into a series of Iesistance and <apacitance network.
'or &ore detail please refer following post /nterconnect @ela! 4odels.
Note: ,his dela! is also 3nown as Net dela!D;ire >ela!Dnterconnect >ela!.
Effect of TransistorFs SiGe On the Sle': Static Timing
Analysis STA! Basic Part4<"!
+n the .ast post we have discussed % how the wire length effects the slew? :ow lets discuss about the
effect of si9e of the transistors. Also before that let?s discuss few basics also.
SiGe of transistor:
There are 2 parameters R ,idth and -engthB #y which yo! can decide the si:e o the transistor4
0or a partic!lar technology R Channel - length is almost constant4 So it means ,idth is going to
decide the si:e o the transistor4 Below ig!re will reresh yo!r memory - a#o!t whichB parameter
* am tal/ing4
* yo! want to increase the width o the transistorB then yo! have 2 options4 One R O!st increase
the ,idth directlyB Second -connect m!ltiple transistors in parallel in s!ch a way that their
eective impact remains same4 0or e&ample R i yo! want to man!act!re a transistor with a
width o 2<!m and a length o <42!m then itKs similar 6not e&actly the same7 to having o!r
transistors connected in parallelB each with a width o .!m and a length o <42!m4 "ere * am not
going to disc!ss the dierence in #oth the way o representation o -ayo!t4 * yo! are interested
then yo! can chec/ any #asic #oo/ o C+OS design4 Below ig!re will reresh yo!r memory
6@ote: Below ig!re * have copied romwww.eda)utilities.co& 7
@ow since we are tal/ing a#o!t the transition time 'transition delay 'slewB we /now that it
depend on the capacitance and resistance4 So #eore we start to disc!ss how width 6means si:e o
the transistor7 impact on the transition delayB we sho!ld /now what all are the capacitance
associated with the transistor4 Below diagram help yo! in that4 6@ote: Below ig!re * have copied
rom www.eda)utilities.co& 7
"ow the capacitance are calc!lated 6means whole derivation and e&planation7B * will disc!ss
some other timeB right now * am writing'copying the val!e o these capacitance directly4
@ote: the reerence o a#ove orm!las is rom the #oo/ written #y 2O4P4!yem!ra3 - Cmos -ogic
Circ!it )esign %dition -2<<24
@ow rom the a#oveB yo! can see that Uate Capacitance 6this gate capacitance has 3 component
R Uate to BaseB Uate to So!rce and Uate to )rain7 has dependence on the ,idth o the Channel
6,74 So it meansB i yo! increase the widthB Uate Capacitance will increase and $ice-$ersa4
So!rce and )rain Capacitance has a m!ltiplying actor 8s and 8d 6which is e1!avilant to ,&-s
or ,&-d74 *t means so!rce and drain capacitance also increases with ,idth o the Channel and
$ice-$ersa4
@ow letKs tal/ a#o!t the Cesistance4 Below Cesistance orm!la is with respect to @+OS4 To!
can derive similar orm!la or P+OS also 6O!st replace s!#script 2n3 with 2p3 74
@ow here the Cesistance is inversely proportional to ,idth o the Transistor4
Effect of Device Size on the Slew (transition time) and Propogation Delay.:
* canKt write in a single line the eect o si:e o transistor on the slew #eca!se itKs not straight
orward 6* /now yo! might have do!#t on my statement74 There are some other actors which
we have to consider4 * hopeB #elow paragraph helps yo! to !nderstand the same4
Consider the a#ove circ!it4 Uate 283 is the )riving Uate and Uate 2B3 is the )riven Uate4 * we
will e&pand this with the act!al capacitanceB it will #e something similar toQ
Capacitance Cgd12 is the Uate Capacitance o )riving Uate 8 d!e to overlap in +1 and
+24
Cd#1 and Cd#2 are the di!sion capacitances d!e to the reverse-#iased pn-L!nction
Cw is the wiring capacitance 6ppB ringeB and interwire7 that depends on the length and
width o the connecting wire4 *t is a !nction o the ano!t o the gate and the distance to those
gates4
Cg3 and Cg( are the gate capacitance o the ano!t gate 6)riven gate74
* we increase the si:e o the transistor 6,idth o the Transistor7 itKs c!rrent carrying capa#ility
increase4 +eans 2larger is the si:e o a transistorB the larger is the driving capa#ility 6the a#ility to
so!rce or sin/ c!rrent7 o a transistor34 Th!s a larger transistor wo!ld normally ma/e its o!tp!t
transition aster 6when o!tp!t load is constant74 The o!tp!t load o a driving gate consists o the
so!rce'drain capacitance o the driving gateB the ro!ting capacitance o wireB and the gate
capacitance o the driven gate4
The larger is the o!tp!t loadB the longer is the time to charge or discharge it4 This wo!ld increase
the transition 6rise or all7 time and propagation delay4
-et me s!mmari:e ew important points4
On increasing the Si:e o Uate 8 R
o On Cesistance )ecreases 6C - inversely proportional to ,7
o +eans large )riving capa#ility 68#ility to so!rce or sin/ c!rrent7
o )ecrease the time to charge the o!tp!t load 6capacitance7 6Consists
o so!rce'drain capacitance o the driving gateB the ro!ting capacitance o wireB and the gate
capacitance o the driven gate7 VV
o +eans - O!tp!t Transition time o Uate 8 and *np!t Transition time or Uate B
decreases4
* am s!re yo! have noticed that * have mar/ed point 3 with VV #eca!se there are terms and
conditions4 :7
On increasing the Si:e o the Uate 8 R So!rce')rain Capacitance also increases which are the
part o o!tp!t load o Uate 84 +eans itKs going to increase the o!tp!t load4 That means as * have
mentioned in my point no 3 R that can #e possi#le only when S') Capacitance o )riving gate
are not dominating the rest o the Capacitance4 ,hich is only possi#le when either 2@et
capacitance is large3 6length o wire is large7 or 2Si:e o the driven gate 6Uate B7 is large3
6which increase the Uate capacitance o UateB7 or 2Both sho!ld #e tr!e34
So or +inimi:ing Propagation )elayB 8 ast Uate'Cell is re1!iredB which is only possi#le #y
14 Deeping the o!tp!t capacitance C- small 6it decreases the charging and
discharging time74 8nd or this
o +inimi:e the area o drain pn L!nctions4 6)ecrease ,7
o +inimi:e *nterconnect capacitance4 6)ecrease wire'net -ength7
o 8void large an-o!t4 +eans +inimi:e gate capacitance o )riven Cell4 6)ecrease
, o )riven cell7
24 )ecreasing the e1!ivalent Cesistance o the transistors
o )ecrease - 60or a partic!lar technology @ode *tKs almost constant7
o *ncrease ,
B!t this increases pn L!nction area and hence C-4
So i we want to !se the si:e o the transistor as one o the parameter to increase'decrease o the
propagation'transition delayB then we sho!ld have !nderstanding o the design and also it
depends on the property o )riven Cell and @et length also4
0ew last points:
1. H5ela7 redu$es with in$rease in in)ut transition and $onstant load
$a)a$itan$eH.
2. H5ela7 in$reases with in$rease in out)ut $a)a$itan$e and $onstant in)ut
transitionH
o *e$ause on in$reasin, the out)ut $a)a$itan$e @ $har,in, and dis$har,in,
ti#e will in$rease.
So we can say that
0he dela7 o% $ell dire$tl7 de)ends on in)ut transition and out)ut $a)a$itan$e.
Effect of Threshol$ voltage: Static Timing Analysis
STA! Basic Part4<c!
Effect of Threshold voltage on the propagation delay and transition delay:
/f !ou will see the below e1uations P / a& sure !ou can easil! fgure out how
threshold voltage e8ect the cell dela!. (*ote= :elow Iesistance for&ula is with
respect to *4.S. >ou can derive si&ilar for&ula for P4.S also (3ust replace
subscript MnN with MpN ).
'ro& above e1uation we have following points
.n Iesistance of 4.S is inversel! proportional to the M?@@)?TnN (where ?Tn is
Threshold ?oltage).
@ecreasing the threshold voltage (L.A ?Tn) increases M?@@)?TnN for constant
?@@.
/ncreasing M?@@)?TnN &eans decreasing M.n IesistanceN In.
@ecreasing In I< decreases.
o 4eans large @riving capabilit! (9bilit! to source or sink current)
o @ecrease the ti&e to charge the output load (capacitance) (<onsists
of source;drain capacitance of the driving gate% the routing capacitance of wire% and
the gate capacitance of the driven gate) VV
o 4eans M.utput Transition ti&e of $ate 9N and M/nput Transition ti&e for
$ate :N decreases.
@ecreasing the transition ti&e &eans decreases the propagation ti&e.
So we can sa! thatR
"Delay can be reduced by using low Vt cells, but the cost paid is high leakage power"
Direct effect is that low Vt cells are often more leaky i.e. leakage power increases.
If still you have any confusion below diagram should clarify your doubts.
I hope above diagram should clear your doubts about the effect of Threshold voltage on Delay.
In the next post we will summarize/list down all the methods of fixing the setup and hold violations.
#7 Ways to fi1 SET2P an$ +O>- violation: Static
Timing Analysis STA! Basic Part4;!
$0 ;a!s to 9x &E,@# and ('F> 5iolation:
Till now% Ae have discussed basic concepts of f2ing the Setup and "old violation
which include
@i8erent for&ulas F e2planation to identif! the t!pe of violation in design.
"ow to f2 those violations7
@i8erent &ethods of /ncreasing and @ecreasing the @ela! in the circuit to f2
these t!pe of violations7
9nd *ow it6s the ti&e to list down di8erent &ethods to f2 these violations. / have
also e2plained in brief each and ever! &ethod% which also referring previous post for
reference. .ne point to re&e&ber here that 'i2ing the Setup and "old ?iolation are reverse
in nature. 9ll the &ethods which are applicable to f2 one t!pe of &ethods % hold true and
can be appl! to f2 other t!pe of if we will do the opposite thing. 5.g ) if setup can be f2 b!
adding 1 bu8er in so&e path then "old can be f2 b! re&oving bu8er in that path. (>ou will
see these things below in the post)
/n the last !ou will also fnd @.s and @.*WTs and reco&&ended approach to f2
these violations. These Ieco&&endations helps designer in reducing iteration and
f2 the violations fast.
/ ,ays 0o Fix Setup $iolation:
Setup violations are essentiall! where the data path is too slow co&pared to the
clock speed at the capture +ip)+op. Aith that in &ind there are several things a
designer can do to f2 the setup violations.
?ethod $ = Ieduce the a&ount of bu8ering in the path.
/t will reduce the cell dela! but increase the wire dela!. So if we can reduce
&ore cell dela! in co&parison to wire dela!% the e8ective stage dela! decreases.
?ethod 2 = Ieplace bu8ers with # /nverters place farther apart
9dding # inverters in place of 1 bu8er% reducing the overall stage dela!.
o 9dding inverter decreases the transition ti&e # ti&es then the e2isting
bu8er gate. @ue to that% the I< dela! of the wire (interconnect dela!) decreases.
o 9s such cell dela! of 1 bu8er gate X cell dela! of # /nverter gate
o So stage dela! (cell dela! F wire dela!) in case of single bu8er Q stage
dela! in case of # inverter in the sa&e path.
o >ou will get the clear understanding b! following fgure and !ou can
refer the frst post to understand how transition ti&e varies across the wire.
?ethod 3 = "?T swap. 4eans change "?T cells into S?T;I?T or into L?T.
Low ?t decrease the transition ti&e and so propagation dela! decreases.
"?T;*?T;L?T t!pe cells have sa&e si(e and pin position. /n both leakage
current and speed% L?TC*?TC"?T. So replace "?T with *?T or L?T will speed up the
ti&ing without disturb la!out.
Negati5e eBect= Leakage current;power also increases.
?ethod 7 = /ncrease @river Si(e or sa! increase @river strength (also known as
upsi(e the cell)
52plained the basic and details in the previous post
Note: *or&all! larger cell has higher speed. :ut so&e special cell &a! have
larger cell slower than nor&al cell. <heck the technolog! librar! ti&ing table to fnd
out these special cells. /ncreasing driver is ver! co&&onl! used in setup f2.
Negati5e eBect: "igher power consu&ption and &ore area used in the
la!out.
/ have notice one e2planation in book Qbook na&eC. / a& cop!ing and
pasting (not 100T) that here because / like that one. 3 4arked the i&portant part b!
:old.
o The basic la!out techni1ue for reducing the gate dela! consists in
connecting 4.S devices in parallel.
o The e1uivalent width of the resulting 4.S device is the su& of each
ele&entar! gate width. :oth n4.S and p4.S devices are designed using parallel
ele&entar! devices.
o 4ost cell libraries include so)called 21% 2#% 24% 2, inverters.
o The 21 inverter has the &ini&u& si(e% and is targeted for low speed%
low power operations.
o ,he x2 in5erter uses two de5ices x$ in5erters, in parallel. ,he
resulting circuit is an in5erter with twice the current capabilities. ,he
output capacitance ma! be charge and discharged twice as fast as for the
basic in5erter 0see below 9gure1, because the Con resistance of the ?'&
de5ice is di5ided b! two. ,he price to pa! is a higher power consumption.
o The e1uivalent Ion resistance of the 24 inverter is divided b! four.
o The clock signals% bus% ports and long wires with severe ti&e
constraints use such high drive circuits.
?ethod 8 = /nsert :u8ers
So&e ti&e we insert the bu8er to decrease over all dela! in case of log wire.
/nserting bu8er decreases the transition ti&e% which decreases the wire
dela!.
/f% the a&ount of wire dela! decreases due to decreasing of transition ti&e C
<ell dela! of bu8er% over all dela! decreases.
Negati5e EBect= 9rea will increase and increase in the power consu&ption.
?ethod / = /nserting repeaters=
<oncepts of Iepeaters are sa&e as / have discussed in M/nserting the :u8erN
(above point). 3ust / a& tr!ing to e2plain this in a di8erent wa! but the over concept
are sa&e.
Long distance routing &eans a huge I< loading due to a series of I< dela!s%
as shown in fgure. 9 good alternative is to use repeaters% b! splitting the line into
several pieces. ;h! can this solution be better in terms of dela!* Qecause
the gate dela! is :uite small compared to the C% dela!.
/n case of /nterconnect driven b! a single inverter% the propagation dela!
beco&e
o Tdela!E tgateF nI.n< E tgate F n
#
I<
/f two repeaters are inserted% the dela! beco&es=
o Tdela!Etgate (dela! of inverter) F #tgate (dela! of repeater) FI< E
tgate F I<
So !ou can see how I< dela! is i&pacting in case of non)repeater in the
circuit.
<onse1uentl!% if the gate dela! is &uch s&aller than the I< dela!% repeaters
i&prove the switching speed perfor&ances% at the price of higher power
consu&ption.
:elow fgure helps !ou to understand the practical use of this.
?ethod 4 = 9dOust cell position in la!out.
Let6s assu&e there are # gate ($9T5 9 and $9T5 :) separated b! 1000u&.
There is another $9T5 < placed at the distance of H00u& fro& $9T5 9.
/f we re)position the $9T5 < at -00u& fro& $9T5 9 (center of $9T5 9 and :)%
overall dela! between $9T5 9 and : decreases.
>ou will get the clear understanding b! frst post and the following diagra&.
Note: The place&ent in la!out &a! prevent such &ove&ent. 9lwa!s
use la!out viewer to check if there are an! spare space to &ove the critical cell to
an opti&al location.
?ethod 2 = <lock skew=
:! dela!ing the clock to the end point can rela2 the ti&ing of the path% but
!ou have to &ake sure the downstrea& paths are not critical paths.
Ielated to clock skew basic P / will discuss that in S/ section.
2 ;a!s to Fix (old )iolations:
"old violation is the opposite of setup violation. "old violation happen when data is
too fast co&pared to the clock speed. 'or f2ing the hold violation% dela! should be
increases in the data path.
Note: "old violations is critical and on priorit! basis in co&parison are not f2ed
before the chip is &ade% &ore there is nothing that can be done post fabrication to
f2 hold proble&s unlike setup violation where the clock speed can be reduced.
The designer needs to si&pl! add &ore dela! to the data path. This can be done b!
?ethod . = :! 9dding dela!s.
9dding bu8er ; /nverter pairs ;dela! cells to the data path helps to f2 the hold
violation.
Note: The hold violation path &a! have its start point or end point in other
setup violation paths. So we have to take e2tra care before adding the bu8er;dela!.
o 5.$. if the endpoint of hold violation path has setup violation with
respect to so&e other path% insert the bu8er;dela! nearer to start point of hold
violation path. 5lse the setup violation increases in other path.
o if the start point of hold violation path has setup violation with respect
to so&e other path% insert the bu8er;dela! nearer to end point of hold violation
path. 5lse the setup violation increases in other path.
/ a& sure !ou &a! be asking what is this and wh!7
:elow fgure and e2planation can help !ou to understand this.
From below 9gure, !ou can also conclude that donMt add buBerDdela!
in the common segment of 2 paths 0where one path has hold 5iolation and
other setup 5iolation1.
?ethod $0 = @ecreasing the si(e of certain cells in the data path.
/t is better to reduce the cells closer to the capture +ip +op because there is
less likel! hood of a8ecting other paths and causing new errors.
Note: Following points are recommended while 9xing setup and hold
5iolations.
4ake &odifcation to the data path onl!.
o 9dOusting register location or re&oving;adding bu8ers to the clock path
will f2 the violation that but it &a! cause &ore violations for so&e other paths
which &a! not present before.
'irst tr! to f2 setup violation as &uch as possible. Then later on start f2ing
hold violation.
/n general% hold ti&e will be f2ed during back)end work (during P*I) while
building clock tree. /f u r a front)end designer% concentrate on f2ing setup ti&e
violations rather than hold violations.
'i2 all the hold violation% if !ou have to choose between setup and hold.
o /f a chip is done with so&e setup violations it can work b! reducing the
fre1uenc!.
o /f a chip is done with hold violations% we have M3JST @J4PN the chip.