1

Metal Oxide Semiconductor

Field Effect Transistor (MOSFET)
Structure:
metal
oxide
semiconductor
p+
n n
S
G
D
2
MOSFET operation
p+
n n
S
G
D
If V
G
=0
n
Assuming V
D
=high, V
S
=0
No current
3
p+
n n
S
G
D
If V
G
=high
n
+ + + +
An n type channel
is formed
Now if V
D
=high, there is a current
flow between D and S
Gate voltage attracts
electrons and pushes
holes away
MOSFET operation
4
MOSFET structures and circuit symbols
p- type substrate
Sour ce
Drai n
Gate
Substr ate
Si O
2
Drai n
Sour ce
Sour ce
Drai n
Gate
Sour ce
Drai n
Bul k
Channel
Depl eti on r egi on
n
+
n
+
(a)
(b)
(d)
(c)
(a) Schematic structure of n-channel MOSFET (NMOS) and
circuit symbols for (b) MOSFET, (c) n-channel MOSFET, and (d)
n-channel MOSFET when the bulk (substrate) potential has to
be specified in a circuit.
5
Complementary MOSFET pairs
Schematic structure of Complementary MOSFET (CMOS) and
circuit symbols for p-channel MOSFET (PMOS). Minuses and
pluses show the depletion regions.
p- type substr ate
n
+
Sour ce
Dr ai n
Gate
Substr ate
Si O
2
Sour ce
Dr ai n
Gate
Sour ce
Dr ai n
Bul k
p
+
n- channel
p- channel
n- type wel l
Si O
2
6
Sub-threshold mode of MOSFET operation
V
G
= 0; the MOSFET conducting channel
is not formed
E
c
E
F
E
F1
E
F2
Channel
Source
Drain
E
n
e
r
g
y
Distance
In the subthresholdregime, the MOSFET current is a small reverse current
through the source substrate and drain substrate p-n junctions;
Only a small number of electrons can pass over the potential barrier
separating the drain and the source.
V
G
= 0
higher V
G

B
( / )
B
kT
ST Source
n n e


7
In the sub-threshold regime, the channel current is very low and increases
exponentially with the gate bias.
Drain
Source
V
G1
V
G2
V
G3
V
G1
<V
G2
<V
G3
Gate-source voltage (V)
1.8 1.4 1.0 0.6 0.2 -0.2
0
-10
-8
-6
10
2
-4
-2
0.05 V
V
ds
=3.0 V
I
t
10
10
10
10
10
10
Sub-threshold mode of MOSFET operation
( / )
B
kT
ST Source
n n e


8
At certain gate bias called the threshold voltage, the conductivity type under
the gate inverts and the barrier between the Source and the Drain
disappears.
Electrons can enter the region under the gate to form a
conducting n-channel.
At the gate voltages above the threshold, the gate and the channel form a
Metal-Insulator-Semiconductor (MIS) capacitor.
Drain
Source
V
G1
V
G2
V
G3
V
G1
<V
G2
<V
G3
Gate-source voltage (V)
1.8 1.4 1.0 0.6 0.2 -0.2
0
-10
-8
-6
10
2
-4
-2
0.05 V
V
ds
=3.0 V
I
t
10
10
10
10
10
10
MOSFET threshold voltage
V
T
9
The free electron charge in the MOSFET channel (per unit area):
Q
1
= C
GATE
(V
G
V
T
)
(assuming that at V
G
= V
T
the free electron concentration is zero)
MOSFET above the threshold voltage
qn
s
= c
i
V
GS
V
T
( )
= c
i
V
GT
0
/ /
i i i ir i
c d d = =
The sheet electron concentration above the threshold, n
S
is given by:
In MOSFETs, the gate and channel form a MIS-capacitor,
hence the capacitance per unit gate area

i
=
ir

0
is the total dielectric permittivity of the gate dielectric
(usually, SiO
2
),
ir
is the relative dielectric permittivity of the gate dielectric.
Total gate capacitance C
G
= c
i
A, where A is the gate area
10
Above the threshold, the sheet electron concentration and hence
the channel current increase linearly with the gate bias V
G
.
Gate-source voltage (V)
1.8 1.4 1.0 0.6 0.2 -0.2
0
-10
-8
-6
10
2
-4
-2
0.05 V
V
ds
=3.0 V
I
t
10
10
10
10
10
10
MOSFET above the threshold voltage
qn
s
= c
i
V
GS
V
T
( )
= c
i
V
GT
11
MOSFET Threshold Voltage
semiconductor
metal
oxide
p+
n n
S
G
D
Drain
Source
12
Band Diagram at the MOS interfaces
metal
oxide
p+
n
n
Before Contact
E
C
E
V
E
Fs
E
i
Vacuum level
OXIDE METAL SEMICONDUCTOR
E
Fm
E
C
E
V
q
m
E
g
q
ox
q
s
q
s
q
s
13
p+
n
n
After Contact
OXIDE METAL SEMICONDUCTOR
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
Metal and semiconductor Fermi levels align by
electron transfer. Bending is the result of the
presence of transferred electron
14
V
G
>0
p
+
n
n
V
G
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
V
G
<V
FB
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
V
G
=V
FB
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
Flat band Voltage
Gate voltage making the band flat
V
FB
=
m
-
s
15
Conductivity conversion in MOSFET
E
C
E
V
E
Fs
E
i
V
G
=0
p
+
V
G
n
n
E
C
E
V
E
Fs
E
i
V
G

p
+
V
G
n
n
Less holes at the
interface, more
bending
p type Less p type
More depletion
16
E
C
E
V
E
Fs
E
i
V
G

p
+
V
G
n
n
p type Less p type
n type Inversion
E
C
E
V
E
Fs
E
i
V
G

p
+
V
G
n
n
p type Less p type
n type Strong Inversion
Onset of
Channel
creation
Channel
created
17
Inversion condition in MOSFET
E
C
E
V
E
Fs
E
i
q
b
qV
s
Surface potential V
s
is controlled by the gate voltage
Accumulation
V
s
<0
Depletion
V
s
<
b
Onset of inversion
V
s
=
b
Inversion
V
s
>
b
Strong Inversion
V
s
>2
b
b
q
kT
i
p n e

=
Equilibrium hole concentration in the bulk of semiconductor
q
b
is the Fermi level offset from
the mid-gap in the bulk material
When V
s
= 2
b
, n-concentration at the surface
is the same as p-concentration in the bulk
18
Surface potential required to reach
the MOSFET threshold
When V
s
= 2
b
, n-concentration at the surface
is the same as p-concentration in the bulk
b
q
kT
i
p n e

=
E
C
E
V
E
Fs
E
i
V
sT
=2
b

b
b
q
kT
i
n n e

=
19
Surface potential and gate voltage
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
V
i
V
s
V
G
is the gate voltage, as source is grounded,
V
G
=V
GS
V
i
is the voltage drop across the oxide/insulator
V
s
is the surface potential
GS FB s i
V V V V = + +
20
Voltage drop across the oxide layer
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
V
i
V
s
V
i
is the voltage drop across the oxide/insulator
GS FB s i
V V V V = + +
d
i
i
Q
V
C
=
where Q
d
is the capacitor charge and C
i
is the capacitance.
Since the charges on the metal and semiconductor plates are the same,
Q
d
can be calculated as the charge in semiconductor.
The semiconductor charge is formed by the charge of the depletion region
Gate electrode and semiconductor form the
plates of the MOS capacitor.
Voltage drop across the capacitor:
21
Voltage drop across the oxide layer
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
V
i
V
s
The relation between the depletion region width W and
the applied voltage V
s
:
2
d s a s
Q qN V =
2
2
a
s
s
q N W
V

=
2
s
a
V
W
qN

= Form this,
2
s
d a a
a
V
Q qN W qN
qN

= =
The depletion region charge (per unit area):
22
Voltage drop across the oxide layer
E
C
E
V
E
Fs
E
i
E
Fm
E
C
E
V
V
G
V
i
V
s
d
i
i
Q
V
c
=
is the depletion region charge per unit area,
c
i
is the MOS-capacitor capacitance per unit area:
s a s d
V qN 2 Q , where =
d
i
is the thickness of the oxide film under the gate
i
i
i
c
d

=
23
MOSFET threshold voltage (cont.)
2
s a s
GS FB s
i
qN V
V V V
c

= + +
At the onset of strong inversion:
( )
( )
2 2
2
s a b
T FB b
i
qN
V V
c

= + +
2 2
N
T FB b b
V V = + +
Finally, the threshold voltage,
2
N
s a i
qN c / =
where the body effect constant,
The MOSFET threshold voltage is defined as the Gate
voltage leading to the strong inversion, i.e. V
s
= 2
b
24
Effect of Body Bias
p+
n n
V
S
V
G
V
D
V
BS
0
( )
BS b N b FB T
V 2 2 V V + + =
the Threshold voltage,
25
Effect of Surface States
p+
n n
V
S
V
G
V
D
V
BS
0
( )
BS b N b
i
ss
FB T
V 2 2
C
Q
V V + + + =
the Threshold voltage,
During the oxide growth on Si, dangling
bonds are created that contributes to
wanted trapped charges at the interface
+ + + + + + + + + +
Q
ss
: surface state charges per unit area