National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 1

Review of 6T SRAM Cell

Review of 6T SRAM Cell
Ding-Ming Kwai
Intellectual Property Library Company
June 3, 2005
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 2
Why 6T SRAM Cell
Why 6T SRAM Cell
Embedded memory
Easy to implement in generic CMOS process
Easy to design as logic circuit
Easy to test by finite-state machine
Compilable design
Fixed cell size to allow us dedicating in
peripheral circuit design
Synchronous interface since 0.35 m
generation simplifies the design
A larger number of instances required
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 3
Outline
Outline
6T cell and its variants First we
generalize and then we derive
Peripheral circuits Utilization is the
key
Cell layout To be symmetric or to be
asymmetric: that is the question
Performance indices To judge is
human
Concluding remarks It does not end
here
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 4
8T SRAM Cell
8T SRAM Cell
Making it completely complementary
Making it completely complementary
Regenerative circuit
for storing a single
bit: two equal-sized
inverters
Access device to
transfer the bit: two
equal-sized
transmission gates
pass transistors
WL
WL
WL
BL BL
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 5
Intel, 1975 NEC, 1969
What Have Been Invented
What Have Been Invented
NEC, 1995
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 6
IBM, 1970
GE, 1985
IBM, 1976
MOSTEK, 1981
What Have Been Invented
What Have Been Invented
(Continued)
(Continued)
NEC, 1998
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 7

The World
The World

s Smallest
s Smallest

Myth
Myth
0
2
4
6
8
10
12
14
16
0.35 0.25 0.18 0.15 0.13 0.09
Technology Node ( m)
S
R
A
M

C
e
l
l

S
i
z
e

(

m
2
)

TSMC
UMC
10.95
7.56
5.6
4.0
2.43
2.14
4.17
3.15
Cell size as a competitive
Cell size as a competitive
edge
edge
C.-H. Hsiao and D.-M. Kwai, Measurement and characterization of 6T SRAM cell, Int. Workshop Memory Technology, Design, and Testing (MTDT), Taipei, Taiwan, Aug. 2005.
0.99
Reach a consensus at last!
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 8
Tradeoffs to Be Made
Tradeoffs to Be Made
Small but slow large but fast: area vs.
speed (read current and write voltage)
Small but hot large but cold: area vs.
leakage power (standby current)
Small but unstable large but stable:
area vs. stability (static noise margin)
Small but low-yield large but high-
yield: area vs. manufacturability
Small but expensive large but cheap:
area vs. cost (masking and process steps)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 9
Outline
Outline
6T cell and its variants First we
generalize and then we derive
Peripheral circuits Utilization is the
key
Cell layout To be symmetric or to be
asymmetric: that is the question
Performance indices To judge is
human
Concluding remarks It does not end
here
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 10
Utilization Is the Key
Utilization Is the Key
0.18
0.18
m single
m single
-
-
port compiler generated instances
port compiler generated instances
with peripheral circuits minimized for layout area
with peripheral circuits minimized for layout area
Capacity (log
2
N
)
A
r
e
a

S
a
v
i
n
g

(
%
)
Extra
Column
Mux
Divided Bit-Line Drive
50
7 9 11 13 15 17 19
0
10
20
30
40
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 11
What Is Column Mux and
What Is Column Mux and
Why It Is Important
Why It Is Important
C = n
R
n
C
= w
W
w
D
n
R
n
C
w
W
w
D
M
n
R
= w
D
/M, n
C
= w
W
M
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 12
P&R Can Easily Destroy It
P&R Can Easily Destroy It
0.18
0.18
m single
m single
-
-
port compiler generated instances
port compiler generated instances
added with redundant power/ground rings
added with redundant power/ground rings
10 m
25 m
40 m
0 m
SRAM
10
20
30
40
50
60
70
80
10 11 12 13 14 15 16 17 18 19
Capacity (log
2
N
)
U
t
i
l
i
z
a
t
i
o
n

(
%
)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 13
Outline
Outline
6T cell and its variants First we
generalize and then we derive
Peripheral circuits Utilization is the
key
Cell layout To be symmetric or to be
asymmetric: that is the question
Performance indices To judge is
human
Concluding remarks It does not end
here
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 14
M1
M2
V1
CO
OD
PO
How They Are Drawn
How They Are Drawn
D.-M. Kwai et al., Detection of SRAM cell stability by lowering array supply voltage, Proc. Asian Test Symp., Taipei, Taiwan, Dec. 2000, pp. 268-273.
(TSMC 0.18
(TSMC 0.18
m Symmetric Example)
m Symmetric Example)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 15
1.28m
1
.
7
7

m
CO
OD
PO
M1
M3
V2
V1
M2
How They Are Drawn
How They Are Drawn
(TSMC 0.13
(TSMC 0.13
m Asymmetric Example)
m Asymmetric Example)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 16
Asymmetry in cross-
coupled inverters can
degrade cell stability
by 100X [may be
exaggerated]
How They Are Drawn
How They Are Drawn
G. E. Sery, Approaching the one billion transistor logic product: process and design challenges, Proc SPIE, vol. 4692, Design, Process Integration, and Characterization for
Microelectronics, pp. 254-261, July 2002.
(Intel 0.18
(Intel 0.18
m Symmetric Example)
m Symmetric Example)
PO
NOD
CO
POD
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 17
S. S. Iyer et al., Embedded DRAM: technology platform for the Blue Gene/L chip, IBM J. Research & Development, vol. 49, no. 2/3, pp. 333-350, Mar./May 2005.
How They Are on Silicon
How They Are on Silicon
Poly and Diffusion for Devices
Poly and Diffusion for Devices
S. Thompson et al., 130nm logic technology featuring 60nm transistors, low-k dielectrics, and Cu interconnects, Intel Tech. J., vol. 6, iss. 2, pp. 5-12, May 2002.
Symmetric and Asymmetric Examples
Symmetric and Asymmetric Examples
Intel 1.22 1.64 m
2
0.13 0.13 m m
Fujitsu 0.9 1.1 m
2
90nm 90nm
IBM 1.2 1.7 m
2
0.13 0.13 m m
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 18
How They Are on Silicon
How They Are on Silicon
Metal
Metal
-
-
1 as Local Interconnect
1 as Local Interconnect
Symmetric and Asymmetric Examples
Symmetric and Asymmetric Examples
S. Nakai, T. Hosoda, and Y. Takao, Integration of high-performance transistors, high-density SRAMs, and 10-level copper interconnects into a 90nm CMOS technology,
Fujitsu Sci. Tech. J., vol. 39, no. 1, pp. 23-31, June 2003.
Intel 1.22 1.64 m
2
0.13 0.13 m m
Fujitsu 0.9 1.1 m
2
90nm 90nm
IBM 1.2 1.7 m
2
0.13 0.13 m m
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 19
How They Are Drawn
How They Are Drawn
IBM 0.13
IBM 0.13
m Example for ULP SRAM
m Example for ULP SRAM
1.3m
R. W. Mann, Ultralow-power SRAM technology, IBM J. Research & Development, vol. 47, no. 5/6, pp. 553-566, Sep./Nov. 2003.
Split Word Line Split Word Line
1
.
8

m
NPG
NPD
PPU
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 20
Disadvantages Related to
Disadvantages Related to
Complicated irregular patterns involving
corner rounding
Simplified rectangular pattern
Different orientation for access NMOS
transistors
Same orientation for all transistors
Pushed spacing rules for metal routing
Nominal spacing rules for metal routing
Conventional Cell Layout
Conventional Cell Layout
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 21
Variations by Inverter Layout
Variations by Inverter Layout
M. Ishida et al., A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 m generation and desirable for ultra high speed operation, Int.
Electron Device Meeting Tech. Digest, 1998, pp. 201-204.
A Reveal Close to Success
A Reveal Close to Success
It turns out
to be very
useful in
90nm and
below process
technologies
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 22
Can We Draw the Polygons
Can We Draw the Polygons
in Another Way?
in Another Way?
M3 M3 M2 VSS (V)
M3 M3 M2 BL (V)
M2 M2 M3 WL (H)
Symmetric Asymmetric Symmetric
Vertical VSS lines parallel to bit lines are required in the mem Vertical VSS lines parallel to bit lines are required in the memory array. ory array.
Metal
Metal
-
-
Layer Assignment for Routing
Layer Assignment for Routing
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 23
Can We Draw the Polygons
Can We Draw the Polygons
in Another Way?
in Another Way?
SRAM Cell Aspect Ratio
SRAM Cell Aspect Ratio
> 1.2
< 0.5
0
0.4
0.8
1.2
1.6
0.25 m 0.18 m 0.13 m 90nm 65nm
Technology Node
S
R
A
M

C
e
l
l

A
s
p
e
c
t

R
a
t
i
o
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 24
Extend Poly and Form Shared Contact Adjust Active Area Move Half Cell to Align Poly Mirror Half Cell Separate VDD/VSS Contacts Rotate Access Transistors Split Word Line Original Symmetric Layout
An Animation to Show Layout
An Animation to Show Layout
Changes to Rectangular Patterns
Changes to Rectangular Patterns
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 25
P. Bai et al., A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 m
2
SRAM cell, Int. Electron Device
Meeting Tech. Digest, San Francisco, CA, Dec. 2004.
Z. Luo et al., High performance and low power transistors integrated in 65nm bulk CMOS technology, Int. Electron Device Meeting Tech. Digest, San Francisco, CA, Dec. 2004.
TI 0.46 1.06 m
2
0.49 m
2
A. Chatterjee et al., A 65nm CMOS technology for mobile and digital signal processing applications, Int. Electron Device Meeting Tech. Digest, San Francisco, CA, Dec. 2004.
Photo Demonstrations
Photo Demonstrations
at 65nm Technology Node
at 65nm Technology Node
Intel 0.46 1.24 m
2
0.57 m
2
IBM 0.41 1.25 m
2
0.51 m
2
It seems that the layout style will pervade!
It seems that the layout style will pervade!
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 26
Disadvantages Related to
Disadvantages Related to
Longer and narrower wells
induce forward body bias
reduce static noise margin
require higher strapping frequency
lower array utilization
More irredundant contacts and via holes
10 contacts/cell 8.5 contacts/cell
3.5 via-1 holes/cell 2 via-1 holes/cell
2.5 via-2 holes/cell 0 via-2 holes/cell
Regular Pattern Cell Layout
Regular Pattern Cell Layout
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 27
Outline
Outline
6T cell and its variants First we
generalize and then we derive
Peripheral circuits Utilization is the
key
Cell layout To be symmetric or to be
asymmetric: that is the question
Performance indices To judge is
human
Concluding remarks It does not end
here
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 28
Cell (Read) Current
Cell (Read) Current
A B
I
cell0
VDD BL BL
WL WL
VSS
B A
I
cell1
VDD BL BL
WL WL
VSS
Bit
Bit
-
-
Line Discharge Current
Line Discharge Current
A = 0 and B = 1 A = 1 and B = 0
V
BL
= I
cell
t/C
BL
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 29
Bounds on Cell Current
Bounds on Cell Current
where Cell Ratio
where Cell Ratio

comes in
comes in
I
cel l
>
I
SD
+ 1
I
cel l
>
I
SA
I
SD
I
SA
+ I
SD
I
SA
+ 1
=
I
cel l
< I
SA
I
cel l
<
I
SD

I
cell
VDD
VDD
VDD
VSS
I
SA
VDD
VDD
VDD
VSS
VDD VSS
I
SD
= =
I
SD
I
SA
W
D
L
A
L
D
W
A
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 30
Saturation Current Monitor
Saturation Current Monitor
I
SA
I
SA
+ 1
I
SD

I
SD
+ 1
Is Not Good Enough
Is Not Good Enough
0.18 m SRAM Cell
0
25
50
75
100
125
150
1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
VDD (V)
C
e
l
l

C
u
r
r
e
n
t

(

A
)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 31
On
On
-
-
Chip Measurement
Chip Measurement
of Cell Current
of Cell Current
Cell Current ( A)
64
64
16 16 16 16
84 86 88 90 92 94 96 98
0
200
400
600
800
1000
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 32
Location Dependence
Location Dependence
Cells are divided into
two groups by their
discharge paths (half
cells) being next to a
strap of a sub-array
or not
Boundary cells tend
to have a smaller
mean and a larger
standard deviation
Boundary
Median = 90.68 A
Average = 90.75 A
Std Dev = 1.77 A
Interior
Median = 91.11 A
Average = 91.17 A
Std Dev = 1.68 A
Cell Current ( A)
of Cell Current
of Cell Current
84 86 88 90 92 94 96 98
4
3
2
1
0
1
2
3
4
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 33
Static Noise Margin (SNM)
Static Noise Margin (SNM)
Static noise is the DC
disturbance present in
logic gates
The worst case occurs
when the static noise
is adversely present in
all logic gates in the
same way
It is the most
important parameter
of an SRAM cell
f
g
+

v
ng
v
nf
0
1
+
0 1
+
0
f g
v
nf
v
ng
Every cell has to demonstrate
Every cell has to demonstrate
E. Seevinck, F. J. List, and J. Lohstroh Static noise margin analysis of MOS SRAM cells, IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 34
f(V
A
- v
n
)
g(V
B
+ v
n
)
V
A
V
B
V
A
V
B
V
LA
V
HA
V
LB
V
HB
f(V
A
)
g(V
B
)
V
A
V
B
V
LA
V
HA
V
LB
V
HB
f(V
A
)
g(V
B
)
f(V
A
+ v
n
)
g(V
B
- v
n
)
V
A
V
B
Shift of Meta
Shift of Meta
-
-
stable Point
stable Point
Maximum Squares in Butterfly Curves
Maximum Squares in Butterfly Curves
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 35
Static Noise Margin
Static Noise Margin
as a Function of Supply Voltages
as a Function of Supply Voltages
SNM (V)
CVDD
WL WL
CVSS
+ +
WL WL = = BL = BL BL = BL = = PVDD PVDD
BL BL
D.-M. Kwai et al., Detection of SRAM cell stability by lowering array supply voltage, Proc. Asian Test Symp., Taipei, Taiwan, Dec. 2000, pp. 268-273.
PVDD
C
V
D
D
(

V
D
D
) P
V
D
D
(

V
D
D
)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 36
V
B
L
(

V
D
D
)
Static Noise Margin
Static Noise Margin
as a Function of Precharge Voltages
as a Function of Precharge Voltages
SNM (V)
C
V
D
D
(

V
D
D
)
CVDD
BL BL
CVSS
+ +
WL WL = = VDD VDD, , BL = BL BL = BL
WL WL
K. W. Mai et al., Low-power SRAM design using half-swing pulse-mode techniques, IEEE J. Solid-State Circuits, vol. 33, pp. 1659-1671, Nov. 1998
VBL
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 37
SNM (V)
Static Noise Margin
Static Noise Margin
as a Function of Bit
as a Function of Bit
-
-
Line Voltages
Line Voltages
WL WL = = CVDD CVDD = = VDD VDD
V
B
L
T
(

V
D
D
)
CVDD
CVSS
+ +
WL WL
BL BL
V
B
L
B
(

V
D
D
)
VBLT VBLB
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 38
Static Noise Margin
Static Noise Margin
as a Function of Source Voltages
as a Function of Source Voltages
K. Osada et al., 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray induced multierrors, IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1952-
1957, Nov. 2003.
CVDD
CVSS
+ +
WL WL
BL BL
WL WL = = VSS VSS, , BL = BL = BL BL = = VDD VDD
SNM (V)
VSS VSS
C
V
D
D
(

V
D
D
) C
V
S
S
(

V
D
D
)
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 39
Outline
Outline
6T cell and its variants First we
generalize and then we derive
Peripheral circuits Utilization is the
key
Cell layout To be symmetric or to be
asymmetric: that is the question
Performance indices To judge is
human
Concluding remarks It does not end
here
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 40
What Revive 6T SRAM Cell
What Revive 6T SRAM Cell
Panel display driver/controller
Large wafer quantity that foundries
cannot refuse
Shrinking pad pitch that cell size
becomes an issue
Lag behind the most advanced
process at least three generations
Power, either static or dynamic, is the
concern
National Tsing Hua University IC Design Technology Center Review of 6T SRAM Cell 41
Challenges in the Future
Challenges in the Future
To many simulation works, too few
measurement results
Not only to show it functional, but
also to prove it manufacturable
To invent a new cell is costly, it will
be a pity to serve only one purpose
There are still some things we do
not know well (e.g., substrate noise)
M.-F. Chang, K.-A. Wen and D.-M. Kwai, Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs, Proc. IEEE Intl Symp. Quality Electronic Design, pp. 225-230,
Mar. 2004.