Neuromorphic Engineering 2, TSPICE 2/28/2012

http://avlsi.ini.uzh.ch/classwiki 1
Circuit simulation using SPICE
Neuromorphic Engineering 2
Lecture 2
(S-C. Liu)
Spring Semester 2012
Analog Chip CAD design tools
S-Edit
Schematic editor
T-Spice
Circuit simulator
L-Edit
Layout editor
DRC
Design rule checker
Extract
Netlist extractor
LVS
Layout vs. Schematic
Design
Verification
Outline
What is SPICE
How does SPICE work
Tanner Tools TSPICE
Live demo of L-Edit layout
SPICE packages
SPICE home page:
http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE/
Public Domain
Original Berkeley SPICE3f4 code:
ftp://ic.eecs.berkeley.edu/pub/Spice3/
NGSpice (mixed-level, mixed-signal simulator) based on
SPICE3f5: http://sourceforge.net/projects/ngspice
Commercial
HSPICE (Synopsys)
PSpice (Cadence)
SIMetrix
Tspice (Tanner Tools)
SPICE origins
SPICE is a computer program designed to simulate analog
electronic circuits. Its original intent was for the
development of integrated circuits, from which its name
was derived: Simulation Program with Integrated Circuit
Emphasis.
1967 Students of Prof. Ronald Rohrer of UC Berkeley
developed Computer Analysis of Nonlinear Circuits,
Excluding Radiation (CANCER)
1972 CANCER was rewritten by L. Nagel under
supervision of D. Pederson, renamed to SPICE1, and
released to the public domain.
1975 SPICE2 was released (Version 2g6)
1986 SPICE3 was rewritten in C (rather than
FORTRAN) and released to the public domain.
SPICE programming
SPICE is an interpreted language: In order for a computer
to understand the SPICE instructions, it must have the
SPICE program (interpreter) installed. SPICE source files
are commonly referred to as netlists (or decks) with each
line in the file called a card.
Writing a SPICE deck is like writing a good program
Plan: Sketch schematic on paper or editor. Modify
existing decks whenever possible.
Code: Strive for clarity. Start with name, email, date,
purpose. Generously comment.
Test: Predict what the results should be. Compare with
actual. Garbage in, Garbage out!
Neuromorphic Engineering 2, TSPICE 2/28/2012
http://avlsi.ini.uzh.ch/classwiki 2
Spice components and analysis
types
You can use SPICE to specify circuit components like:
Resistors, Capacitors, Inductors
Independent sources (V, I), Dependent sources (V,I)
Transmission lines
Active devices (diodes, BJTs, JFETs, MOSFETs)
You can use SPICE to perform the following circuit
analysis:
Non-linear DC
Non-linear transient
Linear AC
Noise and temperature
SPICE
elements and commands
Capacitor
Cx n1 n2 val
Resistor
Rx n1 n2 val
Current source
I ( V) x n1 n2 val
Bipolar transistor
Qx E B C mod
MOSFET
Mx D G S B mod
DC operating point
. op
DC sweep
. dc V1 0 5 . 01
AC analysis
. ac oct / dec/ l i n 10
1 5K
noise
Look on the Tanner cheat sheet for more
The MOSFET device models
All MOSFET devices in SPICE reference a model by its
instance name. Each model in SPICE has a keyword NMOS
or PMOS, as well as a Level parameter.
General form: .model [modelname] [nmos or pmos]
[parmtr1=x]
.model mod1 pmos level=49
.model mod2 nmos level=49 phi=0.65 rd=1.5
Device model levels
Levels 1, 2, 3 (Berkeley SPICE 2g6): Basic transistor
equations. Not very accurate by fast.
Level 4 (BSIM1): Accurate, based on the Berkeley Short-
channel IGFET Model.
Level 5 (Tanner, Maher-Mead): Accurate physically based
model, continuous over all regions of operation including
subthreshold
Levels 13, 28, 39, and 47: Based on Berkeley IGFET models
(BSIM, BSIM2, and BSIM3 models).
Levels 49 and 53 (BSIM3 Revision 3): Most accurate
models, supported by most foundries and SPICE simulation
engines.
SPICE analysis types
DC operating point analysis, .op: Computes a circuits DC
operating point values.
DC transfer analysis, .dc: Computes operating point values
for range of swept signal values.
Transient analysis, .tran: Computes how circuit values vary
over time.
Transient powerup analysis, .tran/powerup: Sets the entire
circuit to zero at t=0s. As simulation proceeds, voltage
sources are allowed to ramp up to their specified values.
Useful to define initial state of circuit which has no
definite DC steady-state condition.
AC analysis, .ac: Characterizes circuits behavior on small-
signal input frequency.
Why Tanner-Tools TSPICE
Integrated with L-Edit and S-Edit.
Affordable (<2K, low maintenance fees).
Optimized for subthreshold circuit simulations.
Table-based mode.
Neuromorphic Engineering 2, TSPICE 2/28/2012
http://avlsi.ini.uzh.ch/classwiki 3
A SPICE netlist
MP_1 out i n Vdd Vdd pmos L=10u W=10u
MN_1 out i n Gnd Gnd nmos L=10u W=10u
in out
Vdd
Gnd
MP_1
MN_1
D G S B model L W
MOS fet
Simulation commands
.options reltol=1e-7 abstol=1e-11 $ set some options, units are in pA,
abstol is the absolute current error tolerance
.options chargetol=1e-19, scale=1, maxmsg=1
.include ams_C35.md $include transistor models
vdd Vdd gnd 5 $ your 5 volt power supply
vin in gnd pwl( 0 0 5u 5 10u 0) $your input signal
.include inverter.sp $include your circuit
.tran/powerup 1u 10u $transient analysis, 1us max step for 10us,
default ramp period is 0.1% of transient
unless override with poweruplen
.print tran in out $ say what to print
SPICE simulation
Solving equations in SPICE
SPICE uses numerical techniques to solve nodal analysis of
circuits. The analysis is done by using Kirchhoffs current
law (KCL). The law specifies that the sum of currents
incident at a node must sum to zero.
The nature of the iterative process of SPICE allows it to
simulate many types of systems that can be modelled
through standard equations and differential equations.
Explanation of tolerance
T-Spice solve circuit equations using finite precision
arithmetic. This means numerical approximations are made
at several steps. The errors introduced by these
approximations are bounded by tolerance settings. For
relative tolerance, the approximation error may not exceed
trel x |v| where v is the value to be approximated. The
absolute tolerance is used when the v is close to zero, in
that case, the error may not exceed the absolute
tolerance. Error comes because T-spice attempts to find a
solution that causes KCL to be satisfied at all nodes. The
norm of the vector of the residual currents at all nodes
should be reduced for each iteration. Iteration is
considered to have converged if the residual current is
within the tolerances defined by abstol and reltol.
How does SPICE work?
Not very well! Dont ever believe it
completely models REALITY.
Problems
Very compute intensive
Doesnt model transistor mismatch
Doesnt model Early effects well
Doesnt model distributed characteristics like
resistance and capacitance
Makes you lazy about thinking