DEPARTMENT OF

ELECTRONICS &
COMMUNICATION
ENGINGEERING
LAB-MANNUALS
SYLLABUS
.
4EE8 DIGITAL ELECTORNICS LAB
1 Study of following combinational circuits:
Multiplexer, Demultimplexer and
Encoder. Verify truth tables of arious logic
functions.
! Study of arious combinational circuits
based on: "#D$#"#D %ogic bloc&s and
'($#'( %ogic bloc&s.
) *o study arious waeforms at di+erent
points of a transistor bistable multiibrator
and its
fre,uency ariation with di+erent
parameters.
- *o design a fre,uency diider using ./0111
timer.
1 *o study arious types of registers and
counters.
2 *o study Schmitt trigger circuit.
3 *o study transistor astable multiibrator.
4 Experimental study of characteristics of
/M'S integrated circuits.
5 .nterfacing of /M'S to **% and **% to
/M'S.
16 7/D to binary conersion on digital ./
trainer.
11 *esting of digital ./ by automatic digital ./
trainer.
1! *o study '80"M8 as /urrent to Voltage 9
Voltage to /urrent conerters 9 comparator.
DOS AND DONTS
DOS
Maintain strict discipline.
Proper handling of apparatus must be done.
Before switching on the power supply get it checked by the lecturer.
Switch off your mobile.
Be a keen observer while performing the experiment
DONTS
Do not touch or attempt to touch the mains power directly with bare hands.
Do not manipulate the experiment results.
Do not overcrowd the tables.
Do not tamper with equipments.
Do not leave the lab without prior permission from the teacher.
INSTRUCTIONS TO THE STUDENTS
GENERAL INSTRUCTIONS
Maintain separate observation copy for each laboratory.
bservations or readings should be taken only in the observation copy.
!et the readings counter signed by the faculty after the completion of the
experiment.
Maintain "ndex column in the observation copy and get the signature of the
faculty before leaving the lab.
BEFORE ENTERING THE LAB
#he previous experiment should have been written in the practical file$
without which the students will not be allowed to enter the lab.
#he students should have written the experiment in the observation
copy that they are supposed to perform in the lab.
#he experiment written in the observation copy should have aim$
apparatus required$ circuit diagram%algorithm$ blank observation table
&if any'$ formula &if any'$ programme &if any'$ model graph &if any'
and space for result.
WHEN WORKING IN THE LAB
(ecessary equipments%apparatus should be taken only from the lab
assistant by making an issuing slip$ which would contain name of the
experiment$ names of batch members and apparatus or components
required.
(ever switch on the power supply before getting the permission from
the faculty.
BEFORE LEAVING THE LAB
#he equipments%components should be returned back to the lab
assistant in good condition after the completion of the experiment.
#he students should get the signature from the faculty in the
observation copy.
#hey should also check whether their file is checked and counter
signed in the index.
LIST OF EXPERIMENTS
III SEM CS & IT
). Study of logic gates.
*. Design and implementation of adders and subtractors using logic gates.
+. Design and implementation of code converters using logic gates.
,. Design and implementation of ,-bit binary adder%subtractor and B.D adder
using ". /,0+.
1. Design and implementation of *-bit magnitude comparator using logic gates$
0-bit magnitude comparator using ". /,01.
2. Design and implementation of )2-bit odd%even parity checker% generator using
". /,)03.
/. Design and implementation of multiplexer and demultiplexer using logic gates
and study of ". /,)13 and ". /,)1,.
0. Design and implementation of encoder and decoder using logic gates and
study of ". /,,1 and ". /,),/.
4. .onstruction and verification of ,-bit ripple counter and Mod-)3%Mod-)*
ripple counter.
)3. Design and implementation of +-bit synchronous up%down counter.
)). "mplementation of S"S$ S"P$ P"S and P"P shift registers using flip-flops.
56P57"M5M# (o.-)
OBJECT: #o test digital ". by automatic digital ". #rainer kit.
APPARATUS REUIRED 8
S!N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). Digital ". #rainer
kit
- )
*. "... /,33
/,3,
111
*
*
)
THEORY 8
". testing can be done by ". trainer kit. #he automatic digital ". trainer kit work
on some modes. #he modes of operation of this kit are8
a' ". tester
b' Micro-computer
c' Programmer
d' .able tester
#he keyboard is divided in three modes for all above modes8
a' ,6+ matrix for fundamental keys.
b' ,6, matrix is for 9:P;9(<M57". =5>S.
c' 92 key block for MD5 S5:5.#"( =5>.
M"/( S(0(+*%") K(.18
". test8 #his is mode selection key. "t selects mode ).
.MP8 #his is mode selection key. "t selects mode *.
P!M78 #his is mode selection key. "t selects mode +.
.B: #est8 "t selects mode ,.
7S#8 #his key is hardware result. "n result system$ select ". test mode and
display on self-test.
#5S#% P!M8 #his is multiple function key.
;<(#8 #his key is used as ? ;<(# keys ? for identifying unknown ".@s $
when ". tester is displaying messages ". number.
M(11-2( %) IC *(1*(3 '"/(:
;5::- #his message flashes thrice if 79M test is =.
". (AA- #his message with flashing question makes and prompt user an ".
number.
". !D- #his message is displayed when ". that was being tested passed
functional test.
". B9D- #his message is displayed when ". that was being tested being fails
in anyone of the test.
Messages during ? ;<(#B Cauto searchD modes of ". tester. ?;<(#"(!-
E<(DB indicates system is hunting for an unidentified ". is not functioning.
CIRCUIT DIAGRAM:
OBSERVATION:
S!!N"! IC N"! P%) )"! C")/%*%")
42""/56-/7
S$61*%*$*( IC
).
*.
+.
PROCEDURE:
). ". testing mode is mode ) of system$ selected at power ( and hardware
result. #his mode can also be selected from other modes by pressing ?". #est
=eyB.
*. n selection of this mode by default self diagnostic 79M test message is
displayed followed by prompt ?". noF.AAB "f at power on self-diagnostic test
fails. System is waiting for number of ". to be tested.
+. 9t this stage #5S# S.=5# is potential free. <ser ". should be tested in test
socket properly.
,. Ghile inserting ". under test in test socket$ care should be taken to align
bottom edge of ". under test with bottom edge of test socket.
PRECAUTION:
). ". should be inserted carefully.
*. ;andle the ". carefully.
V%8- $%9:
).Draw the internal circuit for a DecoderA
*.Ghat are the applications of decodersA
+.Draw the internal circuit of an encoderA
,.Ghat are the applications of Priority encoderA
1.Design a +80 decoder using *8, decoders
RESULT:
Harious ".@s have been tested successfully using ". tester.
DISCUSSION:
9ny ". condition can be tested as well as ". no. can be found out by means of ".
tester.
56P57"M5M# (o.-*
OBJECT8 - Study of various combinational circuits based on8 9(D%(9(D logic
blocks and 7%(7 logic blocks.
APPARATUS REUIRED:
S!N"! A&&-3-*$1 S&(+%,%+-*%") $-)*%*.
). "ntegrated chips
&".'
(9(D gate-/,33
(7 gate-/,3*
(# gate-/,3,
)
)
)
*. .onnecting wires - -
+. Digital trainer kit - )
THEORY:
NAND GATE:
(9(D gate is complemented 9(D gate. utput of (9(D gate will be ) if anyone of
the input is a Iero and will be Iero only when all the inputs $re ). "f the inputs are 9 J
B of a (9(D gate then output is given as8
Y K (A. B)
NOR GATE:
(7 gate is complemented 7 gate. utput of (7 gate will be ) only when all
inputs are Iero and will be Iero if any input represents a ). "f the inputs are 9 J B of a
(7 gate then output is given as8
Y= (A+B)
(# !9#5
(9(D gate is physical realiIation of the complement operation. "t is an electronic
circuit that generates an output signal$ which is reverse of the input signal. 9 (#
gate is also known as inverter because it inverts the input. "f the input of (# gate is
9 then output is given as8
Y=A
AND GATE:
9(D gate is physical realiIation of the logical multiplication. utput of 9(D gate
will be) only when all the inputs are ). "f the inputs are 9 J B then 9(D gate
output is given as8
>K9.B
AND K NAND L NOT or NAND K AND L NOT
OR GATE:
7 gate is physical realiIation of the logical 9ddition. utput of 7 gate will be) if
any of the input signal is ). "f the inputs are 9 J B of a 7 gate then output is given
as8
>K9LB
OR=NOR+NOT or NOR=OR+NOT
S"'( IC1:
NAND :4;;:
"n this ". there are four nand gates. Pin no / is grounded and ), is connected to
power supply. "nput pins are &)$*'$ &,$1'$&4$)3'$&)*$)+' and output of these nand gates
is taken across pin +$2$0 and )* respectively.
NOR :4;<:
"t is also called quad-* input nor gate ".. "n this ". nor gate input is given from &*$+'$
&1$2'$&0$4'$&))$)*' and output pins are )$,$)3 and ), respectively.
NOT :4;4:
"t is also called not gate ". and is also called M<6 inverter as there are 2 not gates in
it. "f we give input M3@ then we get M)@ as output and vise versa.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
A B NOT
Y=A
AND
Y=A!B
OR
Y=A>B
NAND
Y=4A!B7
NOR
Y=4A>B7
3 3 ) 3 3 ) )
3 ) ) 3 ) ) 3
) 3 3 3 ) ) 3
) ) 3 ) ) 3 3
PROCEDURE:
). "nsert the ". on bread-board.
*. Make pin no / grounded and connect pin no ), to power supply.
+. (ow provide inputs as specified in circuit diagram.
,. #ake output across respective pins.
1. 9ny operation such as and$ or$ half adder etc. can be performed using these
".@s.
PRECAUTIONS:
). "nsert ". on bread-board tightly.
*. Don@t forget to ground pin no. /.
+. ;old the ". properly.
RESULT:
Study of various combinational circuits has been done using ". /,33 $/,3*
DISCUSSION:
<sing these ".@s we can realiIe other combinational circuits easily. Since (9(D and
(7 are universal gates so we generally use ". /,33 and /,3*.
V%8- $%9:
).Demorgan@s second theorem is
*.#he problem of logic race occurs in which logic.
+."n which function is each term known as min term.
,."n which function is each term known as max term.
1."n the expression 9LB.$ the total number of min terms will be.
2.9BL9B@K
/."n a four variable =arnaugh map eight adNacent cells give a
EXPERIMENT NO!?
OBJECT: - Study of Binary to !ray and gray to binary code converter and also
verify the truth table for all the possible combinations.
APPARATUS REUIRED:
S.(o. (ame of apparatus Specification Ouantity
). "ntegrated chips /,03 -
*. Patch .hords - -
+. !ray to binary
converter kit
- )
THEORY:
#he conversion of gray to binary code is according to the formula
!nKBn L BnL)
BINARY CODE:
Digital systems use signals that have two distinct values and circuit elements that
have two stable states. 9 binary number of "n@ binary circuit elements each having
an output signal equivalent to 3 or ). 9n "n@ bit binary code is a group of "n@ bits
that assume up to *n distinct combinations of )@s and @s.
GRAY CODE:
"n case of !ray code only one bit in the code group changes when going from
one number to the next e.g. on going from seven to eight$ the gray code changes from
3)33 to ))33 only$ the first bit remains same.
BINARY TO GRAY CONVERSION:
). #he first bit &MSB' of gray code will be same as the first bit of binary number$
so it will be noted as it is.
*. (ow the second bit of gray code will be the 67 of the first and second bit of
the binary number.
+. Similarly$ the third bit of gray code will be 67 of second and third digit of
binary number and thus the sequence will go on.
GRAY TO BINARY CONVERSION:
). #he first bit of binary code &MSB' will be same as first bit of gray code.
*. #he second bit of binary code is obtained by 67ing the second bit of the
gray code and the previous noted bit of binary code$ i.e. nth bit of binary K nth
bit of gray &nL) 'th bit of binary
+. Similarly$ the next bits are obtained by repeating the step * and thus sequence
will go on.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
Gray Code Binary Code
!+ !* !) !3 B+ B* B) B3
3 3 3 3 3 3 3 3
3 3 3 ) 3 3 3 )
3 3 ) 3 3 3 ) )
3 3 ) ) 3 3 ) 3
3 ) 3 3 3 ) ) )
3 ) 3 ) 3 ) ) 3
3 ) ) 3 3 ) 3 3
3 ) ) ) 3 ) 3 )
) 3 3 3 ) ) ) )
) 3 3 ) ) ) ) 3
) 3 ) 3 ) ) 3 3
) 3 ) ) ) ) 3 )
) ) 3 3 ) 3 3 3
) ) 3 ) ) 3 3 )
) ) ) 3 ) 3 ) )
) ) ) ) ) 3 3 3
PROCEDURE:
). Make connections as per the circuit diagram.
*. !ive binary input to the circuit and you will get the equivalent gray output.
+. (ote the output.
,. 7epeat the process with different inputs.
PRECAUTIONS:
). .onnections must be tight and clear.
*. :eads must be carefully pushed in ports.
+. utput should be recorded correctly.
,. switch off when equipment is not used.
RESULT:
Binary to gray and gray to binary code conversion has been done successfully.
DISCUSSION:
!ray code is that in which only one bit in the code group change when going from
one no to the next. "t belongs to the class of minimum-change codes. "t is a non-
weighted code. #he experiment is implemented by 5x-7 gate ".-/,02.
V%8- $%9:
).Ghich takes more areaA 7ipple counters or Synchronous countersA
*."n a + bit binary counter what is the frequency of MSB if the frequency of operation
is f ;IA
+."mplement all *input logic gates using *8) mux
,."mplement a ,8) mux using *8) muxA
1.;ow many *8) mux are required in order to construct a ++8) muxA
2.Ghat is the difference between 7S and P= flip flopA
/.Ghat is race around conditionA ;ow can it be avoidedA
EXPERIMENT N"!-4
OBJECT: Study and perform binary to decimal encoder.
APPARATUS REUIRED:
S!N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). Binary to decimal
encoder kit
/,,/ trainer )
*. Patch cordes - -
THEORY:
Binary number system-
#he binary number system is the system consists of only two digits i.e. 3 or ) with
base *. "n a binary number$ the weight of each successively higher position to the left
is an increasing power of *.
D(+%'-0 )$'6(3 1.1*('8
#he decimal number system has )3 digit &3-4 '. "t has base )3. "t is most common no
system is used in daily life.
S(8() 1(2'()* /%1&0-. 4::?;7 -)/ E)+"/(3 4:44:7:
9 seven-segment indicator is used for displaying any one of decimal digit 3-4.
<sually the decimal digit is available in B.D. 9B.D to seven-segment decoder
accepts a decimal digit in B.D and generator the code. #he figure shows necessary
connections between the decoder and display the ". /,,/ is a B.D to seven-segment
decoder driver.
"t has , input of B.D digit. "n input 3 is most significant and 9 is least significant
digit$ the ,-bit B.D is converted to a seven digit segment code with a to g. #he output
of the /,,/ is applied to the input of the //+3 seven-segment displays.
ther equivalent seven segment display ".@s may have additional anode terminals and
may require different resistors values.
BCD *" :- S(2'()* D(+"/(38
#he ". /,,2% /,,/ are a special ckt tha1t can accept the standard +,*) B.D input and
for /,,2% /,,/ are shown which is used to operate a /- segment read out.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
BINARY CODE DECIMAL CODE
D C B A
3 3 3 3 3
3 3 3 ) )
3 3 ) 3 *
3 3 ) ) +
3 ) 3 3 ,
3 ) 3 ) 1
3 ) ) 3 2
3 ) ) ) /
) 3 3 3 0
) 3 3 ) 4
PROCEDURE:
)' 9rrange the binary to decimal decoder kit.
*' Switch ( the power supply.
+' .heck the output by inserting the pin in their respective 3 and )places.
,' bserve the decimal output for the binary codes mentioned in the observation
table.
PRECAUTION:
)' 9ll the connections should be tight.
*' Do not touch the display.
+' Switch EE the kit $ if not being used.
RESULT:
Study of binary to decimal encoder kit has been done successfully.
DISCUSSION:
Binary to decimal encoder drive a common anode /-segment display. 5ach segment
consist of one :5D and the anode of all :5D@s are connected to LHcc. By forward
biasing different :5Ds the digits 3 through 4 can be displayed.
V%8- $%9:
). Ghat is gray code.
*. .onvert )333)3)))3 in to gray code.
+. .onvert gray 33))3)3)3)3 in to binary code.
,. Ghat is race around condition
56P57"M5(# (.-1
OBJECT: - Study of following combinational circuits8 Multiplexer$ Demultiplexer.
Herify truth tables of various logic functions.
APPARATUS REUIRED:
S!N"! N-'( ", *@( -&&-3-*$1 S&(+%,%+-*%") $-)*%*.
). "ntegrated chips&".' /,)1)$/,)+0$/,33$
/,)2+$/031
1
*. .onnecting wires - -
+. Digital trainer kit - )
THEORY:
MULTIPLEXERS:
Multiplexer is a digital circuit$ which has many inputs and single output. #he
function of Multiplexer is to select one of the input lines and connect it to the
output. "t is also known as data selector. Selection of desired input is done by
means of selection lines. !enerally there are *( input lines and ( select lines
whose bit combinations determine which input is to be selected. "t acts like a
digitally controlled switch. #he select input is controlled by the select inputs
applied.
DEMULTIPLEXER:
Demultiplexer is digital circuit$ which has one input line and many output lines. "t is
used to send a single input on one of the output lines and thus performs reverse
operation of the multiplexer. "t has one input and ( outputs. #he select input code
determines to which output line the data input will be transmitted. "n other words$
demultiplexer takes one input data source and selectively distributes it to ) of (
output channels. #he number of select lines is MS@ where$
( K *QS.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
8-*"-A M$0*%&0(B(3:
INPUTS OUTPUTS
S* S) S3
3 3 3 D3
3 3 ) D)
3 ) 3 D*
3 ) ) D+
) 3 3 D,
) 3 ) D1
) ) 3 D2
) ) ) D/
C-*"-8 D('$0*%&0(B(3:
D-*- %)&$* S(0(+* %)&$*1 O$*&$*1
S* S) S3 >
/
>
2
>
1
>
,
>
+
>
*
>
)
>
3
D 3 3 3 3 3 3 3 3 3 3 D
D 3 3 ) 3 3 3 3 3 3 D 3
D 3 ) 3 3 3 3 3 3 D 3 3
D 3 ) ) 3 3 3 3 D 3 3 3
D ) 3 3 3 3 3 D 3 3 3 3
D ) 3 ) 3 3 D 3 3 3 3 3
D ) ) 3 3 D 3 3 3 3 3 3
D ) ) ) D 3 3 3 3 3 3 3
PROCEDURE:
). Make connections as per the circuit diagram.
*. Provide input through input lines and obtain the multiplexed output.
+. (ote the corresponding output.
,. 7epeat the same process for demultiplexer.
PRECAUTIONS:
). 9ll connections must be tight.
*. .heck power supply circuit and other factors according to requirement.
RESULT:
Study of 0-channel digital multiplexer and demultiplexer has been done successfully.
DISCUSSION8
Multiplexer and demultiplexers have wide application in digital communication. "n
case of multiplexing several signals can be transmitted through a common
communication channel.
V%8- $%9:
a. Ghat is code comperator.
b. .onvert octal&*+12' to decimal.
c. .onvert hexadecimal&a2/b' to octal.
d. "mplement full adder using half adder
56P57"M5(# (.-2
OBJECT8 #o study the characteristics of .MS integrated circuit.
APPARATUS REUIRED:
S!N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). .MS kit - )
*. Multimeter Digital )
+. Power supply 3-)*H )
,. Patch cords - )3
THEORY:
.MS circuit takes the advantage of the fact that both n-channel and p-channel can be
fabricated on the same substrate. #he basic circuit is the inverter$ which consists of one p-
channel transistor and one n-channel transistor.
Ghen a .MS logic circuit is in a static state its power dissipation is very low. #his is
because there is always on-off transistor in the path when the state of circuit is not changing.
9s a result$ a typical .MS gate has static power dissipation on the 3.3) mG of order.
.MS logic is usually specified for a single power supply operation over a voltage range
from + to )0H with a typical H( value of 1H operating .MS at a larger power supply
voltage reduces the propagation delay time and improves the noise margin but the power
dissipation is increased. #he .MS fabrication process is simpler than ##: and provides a
greater packing family. #his means that more circuit can be placed on a given area of silicon
at a reduced cost per function.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
SD%*+@%)2 +@-3-+*(3%1*%+1:
S!N"! I)&$* 8"0*-2( 48"0*17 O$*&$* V"0*-2( 48"0*17
).
*.
+.
C$33()* 1"$3+%)2 +@-3-+*(3%1*%+1:
S!N"! R(1%1*-)+(
4"@'17
C$33()* 4'A7 V"0*-2( 48"0*17
).
*.
+.
TD" %)&$* NOR 2-*(:
INPUT OUTPUT
:ow :ow ;igh
:ow ;igh :ow
;igh :ow :ow
;igh high :ow
PROCEDURE:
)' SWITCHING CHARACTERISTICS:
a' Switch on the power to logic training board. .onnect the circuit.
b' #urn )3= pot meter slowly from low end to high end and note the output
voltage.
c' Stop turning the pot meter when the voltmeter shows a change approx. 4 volt.
Measure the input voltage at this time using the same voltmeter.
d' Design a graph for input voltage and output voltage.
e' Plot the curve for input and output voltage.
<7 CURRENT SOURCING CHARACTERISTICS OF A CMOS INVERTER:
a' Make the circuit connections as required.
b' Measure output voltages with 7 equal to ) = ohm and with 7 equal to )3=
ohms.
c' Disconnect 7 and measure current taken by the "..
d' Plot the curve.
PRECAUTIONS:
). 9ll connections must be tight.
*. .heck power supply circuit and other factors according to requirement.
+. #ake the observations carefully.
RESULT:
.haracteristics of switching and current sourcing have been obtained.
DISCUSSION:
Switching characteristics also show that the changeover point depends on supply
voltage. the circuit therefore automatically adNusts itself to supply voltage variations.
V%8- $%9:
). 5xplain hamming code.
*. Ghat is parity code.
+. )33))3 is code received at receiver what is correct code.
,. 5xplain de-morgen@s theorem.
EXPERIMENT N"!-:
OBJECT8 #o study P-9MP as current to voltage and voltage to current converter.
APPARATUS REUIRED8
S!N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). "ntegrated chips
&".'
/,) )
*. 7esistances )3=
)1=
,
)
+. Digital multimeter - -
,. 9mmeter )
THEORY:
9n operational amplifier abbreviated as P-9MP is basically a multi stage$ very high
gain$ direct coupled$ negative feedback amplifier that uses voltage shunt feedback to
provide a stabiliIed voltage gain. 9n P-9MP has high input impedence and low
output impedence and has capability of amplifying signal having frequency ranging
from Iero to )M;I i.e. p-amp can be used to amplify dc as well as ac input signals.
#he word operational stands for various mathematical operations such as
addition subtraction$ multiplication$ differentiation$ integration etc.$ and amplifier is
one which boosts or amplifies the signal. Since the circuit performs both
mathematical operation and amplification and that is why it is called the operational
amplifier.
"n voltage to current convertor for a single input the current in the load is given by-
"cKH%7:
#he output current "c is independent of load resistance. #his is due to virtual ground
or the converting input terminal to the p-amp. Ghen signals are to be compared a
comparator is used.
CIRCUIT DIAGRAM:
Holtage to current convertor
.urrent to voltage convertor8
OBSERVATION TABLE:
Holtage to current convertor
S!N" I5P V"0*-2(4V%)74V7 O5P +$33()*4I"74'A7
).
*.
+.
,.
.urrent to voltage convertor
S.(o "%P .urrent &m9' %P Holtage &H'
).
*.
+.
,.
PROCEDURE:
Holtage to current convertor
). Make connections as per the circuit diagram.
*. 9pply input voltage to the non inverting terminal of p-amp.
+. bserve the output current through ammeter reading.
,. 7epeat this process for different values of input voltage.
.urrent to voltage convertor
). Make connections as per the circuit diagram.
*. 9pply the input current to the non inverting terminal of p-amp .
+. bserve the output voltage through pin no.2 of p-amp on .7.
,. 7epeat this process for different values of input current.
PROCEDURE:
). .onnect the circuit carefully.
*. 7eadings should be taken carefully.
+. .onnections should be tight and clear.
,. Switch off the device$ if not being used.
RESULT:
Study of voltage to current and current to voltage convertor has been done
successively. Holtage is converted linearly to current
DISCUSSION:
#he output current is very small even with very large change in input voltage. #he
voltage to current characteristic is linear.
V%8- $%9:
). "mplement and gate using M<6.
*. "mplement or gate using M<6.
+. "mplement ,8) using *8) mux.
,. "mplement 08) using *8).
56P57"M5(# (o.-0
OBJECT: #o study Schmitt trigger using ". 111.
APPARATUS REUIRED:
S N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). ". 111 )
*. 7esistor
)33=
)=
)
)
+. .apacitor
)E
3.3)E
)
)
,. .7 - )
1. Eunction generator )3M;I-+M;I )
2. Bread-board - )
/. .7 probes B(. to crocodile )
0. .onnecting wires - -
THEORY:
Schmitt trigger is a wave shaping circuit used for generating square waveform with a
sine waveform input. #he ". 111 timer can be used to function as a variable threshold
Schmitt trigger. "n this circuit the two internal comparator input pins are connected
together and externally biased at &)%*' Hcc through 7) and 7* Since$ &*%+'Hcc and
the lower comparator at the bias provided by 7) and 7* is entered within these two
thresholds.
#he retrace level causes the internal flip flop to alternatively set to reset generating a
square wave output. 9s long as 7R K7*$ 111 timer will automatically be biased for
any supply voltage in the range of 1v to )2v. Erom curve it is a )03 phase shift.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
S!N"! I5P F3(#$()+. O5P
F3(#$()+.
I5P V"0*-2( O5P V"0*-2(
).
*.
+.
PROCEDURE:
). Make the circuit connections as per the circuit diagram$ on the bread-board.
*. 9pply input sine wave signal through pin *.
+. .onnect pin + to .7.
,. bserve the output on any of the channel on .7.9 square wave output will
appear on .7 screen.
1. (ote the time period of pulse and calculate the frequency. .ompare the input
signal and output signal frequency.
2. (ote the output signal voltage and compare it with input signal voltage.
PRECAUTIONS:
). ". should be properly inserted.
*. .onnections must be tight.
+. 7eading should be correctly observer.
,. Gires should not touch each other.
RESULT:
Study of Schmitt trigger has been done successfully. Erequency measured by output
waveform in .7 is SSSSSSSSS.
DISCUSSION:
Schmitt trigger is used for wave shaping circuits. "t can be used to generate
rectangular wave with sharp edges from a sine wave or any other waveform.
V%8- $%9:
). Ghat is 5ncoder.
*. 5xplain+80 decoder.
+. "mplement half adder usingencoder.
56P57"M5(# (o.-4
OBJECT: #o study the waveforms for 9stable Multivibrator using ".-111 timer.
APPARATUS REUIRED:
S N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). ". 111
*. 7esistor )3=
)=
*
)
+. .apacitor 3.3)
3.)
)
)
,. .7 - )
1. .7 probes B(. to crocodile )
2. .onnecting wires - -
THEORY:
".-111 timer is very popular and general purpose ".. "t can be used square wave
generator$ pulse generator$ time delay generator$ etc. initially$ when output is high$
capacitor . starts charging towards Hcc through 7) and 7*. ;owever as soon as the
voltage across the capacitor equals *%+ Hcc$ comparator trigger the flip-flop and
output switches to low. (ow capacitor starts discharging through 7* and O). when
the voltage across . equals )%+ Hcc$ comparator *@s output triggers the flip-flop and
the output goes high. #hen the cycle repeats.
#he capacitor is periodically charged and discharged between *%+ and )%+ Hcc
respectively. #he time during which the capacitor changes from )%+ Hcc and *%+ Hcc
is equal to the time$ the output is high and given by-
t) K 3.24+&7) L7*' .
Similarly$ the time during which the capacitor discharges from *%+ Hcc to )%+ Hcc is
equal to the time during which the output is low and is given by-
t* K 3.24+ 7*.
thus$ the total period of output waveform is $
# K t) Lt*
Erequency &f' K )%# K ).,2%&7) L 7*' .
#he duty cycle is the ratio of the time during which the output is high to total period #
$ is given by-
T Duty cycle K D K &tc%#' x )33
D K n time%#otal time
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
7esistance
&7)'
7esistance
&7*'
#( #EE #total #heoretical
Erequency
Practical
Erequency
Duty
cycle&theo.'
Duty
cycle
&prac.'
PROCEDURE:
). Make connections on the breadboard as per the circuit diagram.
*. .onnect pin 0 to supply LHcc.
+. .onnect pin + to .7 to observe the output.
,. bserve the output on any of the channel on .7.
1. 9 square wave output will appear on .7 screen.
2. (ote the time period of pulse and calculate the frequency.
/. .ompare the theoretical and practical frequency.
PRECAUTIONS:
). ". should be properly inserted.
*. .onnections must be tight.
+. 7eading should be correctly observer.
,. Gires should not touch each other.
RESULT:
Ge have observed the waveform for astable multivibrator and following results has
been obtained-
#heoretical frequency K SSSSSSSSS
Practical frequency KSSSSSSSSSS
Duty cycle &theoretical' KSSSSSSSS
Duty cycle &practical' KSSSSSSSSSS
DISCUSSION:
"n astable multivibrator external triggering is not required. Practical and theoretical
duty cycle is close to each other. Duty cycle can be adNusted by changing values of 7)
and 7*.
56P57"M5(# (o.-)3

OBJECT: #o study mono-stable multivibrator using ". 111.
APPARATUS REUIRED:
S N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). ". 111 )
*. Diode )(,33/ )
+. 7esistor
)=
*./=
*
)
,. .apacitor
2033E
)E
2.3)E
)
)
)
1. Eunction generator - )
2. .onnecting wires - -
/. .7 - )
THEORY:
"n monostable multivibrator$ there is only one stable state. ne transistor is in stable
and other is in quasi-stable state. #he time taken in storage of energy decides the pulse
width. 5xternal triggering does the transition of output from stable to quasi-stable
state.
"nitially$ capacitor . has no initial charge. utput of MMH goes high when triggering
pulse is applied. #his is the transition of output from stable to quasi-stable state. .
now rises exponentially with time constant 7. Ghen capacitor charges to reference
level of L*Hcc%+ $ output of op-amp goes high so O becomes high and output of
MMH becomes low. #hus the output transit back to stable state from quasi-stable
state. #ime during which output is high is U
T = 1.1 RC
Erequency K )%#
#he set flip-flop saturates discharge transistor shorting the capacitor to ground.
.apacitor discharges very rapidly and MMH reverts back to stable state and stays
there until triggering is applied. 9gain the cycle is repeated.
CIRCUIT DIAGRAM:
OBSERVATION TABLE:
R(1%1*-)+( 4R7 C-&-+%*-)+(
4C7
P$01( &(3%"/
4T7
T@("3(*%+-0
F3(#$()+.
P3-+*%+-0
F3(#$()+.
PROCEDURE:
). Make connections as per the circuit diagram$ on the bread-board.
*. #rigger input is provided through pin *.
+. .onnect pin 0 to supply LHcc and pin + to .7 to observe the output.
,. bserve the output on any of the channel on .7.9 square wave output will
appear on .7 screen.
1. (ote the time period of pulse and calculate the frequency. .ompare the
theoretical and practical frequency.
PRECAUTIONS:
). ". should be properly inserted.
*. .onnections must be tight.
+. 7eading should be correctly observer.
,. Gires should not touch each other.
RESULT:
Ge have observed the waveform for monostable multivibrator and following results
has been obtained-
#heoretical frequency K SSSSSSSSS
Practical frequency KSSSSSSSSSS
DISCUSSION:
By changing the value of 7 and . the gate width can be changed. #he monostable
multivibrator can be used to function as an adNustable pulse width generator. "t can
generate uniform width pulses from a variable width input pulse train.
56P57"M5(# (o.-))
OBJECT: #o study Bi-stable multivibrator using ". 111.
APPARATUS REUIRED:
S N"! E#$%&'()* S&(+%,%+-*%") $-)*%*.
). ". 111 )
*. Diode )(,33/ )
+. 7esistor
)=
)3=
)
*
,. .apacitor
)E
3.3)E
)
)
1. Eunction generator - )
2. .onnecting wires - -
/. .7 - )
THEORY:
Bistable multivibrator will remain in either state indefinitely. 9n external event or
trigger can clip circuit from one state to other. Such a circuit is important as the
fundamental building block of a register or a memory device. #his circuit is known as
flip flop. #aking the trigger input low makes the output of the circuit to go into the
high state. #aking the reset input low makes the output of the circuit go into the low
state.
"n bistable or flip-flop operation both the states are stable that is to make a transition
in output state a trigger is required externally. ;ence no capacitor is required to store
the energy for auto-triggering.
#o set the BMH i.e. to obtain output at pin + &O' high a negative pulse of amplitude
less than LHcc%+ is applied to set input &pin *'. "t gives high output &O output of BMH
at pin +'.
#o reset the BMH i.e. to obtain O at pin + low a positive pulse of amplitude greater
than L*Hcc%+ is applied at set input &pin 2'$ which resets BMH &O at pin + is
low'.Ghen both the input pulses are absent$ then there is no transition in the output.
#his type of circuit is ideal for use in an automated model railway system where the
train is required to turn back and forth over the same piece of track. 9 push button is
placed on each end of the track such that when the train hits one $ it will either trigger
or reset the bi-stable.
CIRCUIT DIAGRAM:
PROCEDURE:
). Make the connections as per the circuit diagram.
*. 9pply the negative trigger pulse through pin *.
+. (ow$ apply the positive trigger pulse through pin no 2.
,. btain the output on the .7 and observe the output waveform carefully.
PRECAUTIONS:
). ". should be properly inserted.
*. .onnections must be tight.
+. 7eading should be correctly observer.
,. Gires should not touch each other.
RESULT:
#he study of waveform for bi-stable multivibrator using ". 111 has been done
successively.
DISCUSSION:
9 bistable multivibrator is two cross-coupled inverting amplifiers consisting of two
transistors and four resistors. Ge obtain a square waveform of frequency dependant
on the circuit constant.