Chap09 2UP 5 2 04

Chapter 9 Switched Capacitor Circuits
5/2/04
CHAPTER 9 SWITCHED CAPACITOR CIRCUITS

Objective
The objective of this presentation is:
1.) Introduce the principles of switched capacitor circuits
2.) Illustrate the application of switched capacitor circuits to filter design
Outline
Section 9.0 - Introduction
Section 9.1 - Switched Capacitor Circuits
Section 9.2 - Switched Capacitor Amplifiers
Section 9.3 - Switched Capacitor Integrators
Section 9.4 - z-domain Models of Two-Phase, Switched Capacitor Circuits, Simulation
Section 9.5 - First-order, Switched Capacitor Circuits
Section 9.6 - Second-order, Switched Capacitor Circuits
Section 9.7 - Switched Capacitor Filters
Section 9.8 - Summary
CMOS Analog Circuit Design
P.E. Allen - 2004
Chapter 9 Section 1 (5/2/04)
Page 9.0-1
9.0 - INTRODUCTION
Organization
;;;
;;;
;;;
;;;;
;;;
;;;;;;;;;;
;;;
;;;
;;;;;;
Chapter 10
D/A and A/D
Converters
Chapter 9
Switched Capacitor Circuits
Systems
Chapter 6
Simple CMOS &
BiCMOS OTA's
Chapter 7
High Performance
OTA's
Chapter 8
CMOS/BiCMOS
Comparators
Complex
Simple
Chapter 4
CMOS/BiCMOS
Subcircuits
Chapter 5
CMOS/BiCMOS
Amplifiers
;;;
;;;;
;;;
;;;;;;;;;;
Circuits
Chapter10
1
Chapter
Introduction
D/ to Analog CMOS Design
Devices
Chapter
Chapter11
2
Analog
CMOS
Technology
Systems
Chapter 3
CMOS
Modeling
P.E. Allen - 2004
Page 9.0-2
Advantages of Switched Capacitor Circuits

1.) Compatibility with CMOS technology
2.) Good accuracy of time constants
3.) Good voltage linearity
4.) Good temperature characteristics
Disadvantages of Switched Capacitor Circuits
1.) Experience clock feedthrough
2.) Require a nonoverlapping clock
3.) Bandwidth of the signal must be less than the clock frequency
Philosophical Viewpoint
The implementation of switched capacitors in CMOS technology occurred in the early
1970s and represented a major step in implementing practical analog circuits and
systems in an integrated circuit technology.
Switched capacitor circuits are not new.
James Clerk Maxwell used switches and a capacitor to measure the equivalent
resistance of a galvanometer in the 1860s.
P.E. Allen - 2004
Page 9.1-1
SECTION 9.1 SWITCHED CAPACITOR CIRCUITS

RESISTOR EMULATION
Parallel Switched Capacitor Equivalent Resistor
i1(t)
v1(t)
vC (t)
i1(t)
i2 (t)
v2 (t)
v1(t)
i2 (t)
v2 (t)
Fig 9.1-01
Two-Phase, Nonoverlapping Clock:

1
1
t
0
2
1
0
0
T/2
3T/2 2T
Fig. 9.1-02
P.E. Allen - 2004
Page 9.1-2
Equivalent Resistance of a Switched Capacitor Circuit

Assume that v1(t) and v2(t) are changing slowly with respect to the clock period.
The average current is,
1T
1 T/2
i1(t)
i2 (t)
1
i1(average) = T i1(t)dt = T i1(t)dt
2
0
0
Charge and current are related as,
v (t)
v1(t)
vC (t)
C 2
dq1(t)
i1(t) = dt
Fig. 9.1-03
Substituting this in the above gives,
1 T/2
q1(T/2)-q1(0) CvC(T/2)-CvC(0)
i1(average) = T dq1(t) =
=
T
T
0
However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore,

C [v1(T/2)-v2(0)] C [V1-V2]
i1(t)
i2 (t)
R
T
T
For the continuous time circuit:
v1(t)
v2 (t)
V1-V2
T
i1(average) = R
RC
Fig. 9.1-04
For v1(t) V1 and v2(t) V2, the signal frequency must be much less than fc.
i1(average) =
P.E. Allen - 2004
Page 9.1-3
Example 9.1-1 - Design of a Parallel Switched Capacitor Resistor Emulation

If the clock frequency of parallel switched capacitor equivalent resistor is 100kHz,
find the value of the capacitor C that will emulate a 1M resistor.
Solution
The period of a 100kHz clock waveform is 10sec. Therefore, using the previous
relationship, we get that
T 10-5
C = R = 106 = 10pF
We know from previous considerations that the area required for 10pF capacitor is much
less than for a 1M resistor when implemented in CMOS technology.
P.E. Allen - 2004
Page 9.1-4
Power Dissipation in the Resistance Emulation

If the switched capacitor
i1(t)
i2 (t)
1
2
circuit is an equivalent
resistance, how is the power
v (t)
v1(t)
vC (t)
dissipated?
C 2
i1(t)
i2 (t)
v1(t)
v2 (t)
Fig 9.1-01
Continuous Time Resistor:

(V1 - V2)2
Power =
R
Discrete Time Resistor Emulation:

If the switches have an ON resistance of Ron, then power dissipated/clock cycle is,
(V1 -V2) T
Power = i1(aver.)(V1-V2) where i1 (aver.) = RonT e-t/(RonC)dt
0
(V1-V2)2 T
Power = TRon
e -t/(RonC)dt
(V1-V2)2
= (T/C)
-e -T /(RonC) + 1
(V1-V2)2
(T/C) if T >> RonC
Thus, if R = T/C, then the power dissipation is identical in the continuous time and
discrete time realizations.
P.E. Allen - 2004
Page 9.1-5
Other SC Equivalent Resistance Circuits

i1(t)
v1(t)
S1
S2
C
vC (t)
Series
i1(t)
i2 (t)
v2 (t)
C1
v1(t)
S1
vC1 (t)
i2 (t)
i1(t)
S2
v2 (t)
vC2(t)
C2
Series-Parallel
v1(t)
S1 C S2 i2 (t)
vC (t)
S1
S2
v2 (t)
Bilinear
Fig. 9.1-05
Series-Parallel:
The current, i1(t), that flows during both the 1 and 2 clocks is:
T
q1(T/2)-q1(0) q1(T)-q1(T/2)
1T
1 T/2
+
i1(average) = T i1(t)dt = T i1(t)dt + i1(t)dt =
T
T
0
0
T/2
Therefore, i1(average) can be written as,
C2 [vC2(T/2)-vC2(0)] C1 [vC1(T)-vC1(T/2)]
+
i1(average) =
T
T
The sequence of switches cause,vC2(0)=V2, vC2(T/2)=V1, vC1(T/2)=0, and vC1(T)= V1-V2.
Applying these results gives
C2[V1-V2] C1[V1-V2- 0] (C1+C2)(V1-V2)
+
=
i1(average) =
T
T
T
T
Equating the average current to the continuous time circuit gives: R = C1 + C2
P.E. Allen - 2004
Page 9.1-6
Example 9.1-2 - Design of a Series-Parallel Switched Capacitor Resistor Emulation

If C1 = C2 = C, find the value of C that will emulate a 1M resistor if the clock
frequency is 250kHz.
Solution
The period of the clock waveform is 4sec. Using above relationship we find that C
is given as,
T 4x10-6
2C = R = 106 = 4pF
Therefore, C1 = C2 = C = 2pF.
P.E. Allen - 2004
Page 9.1-7
Summary of the Four Switched Capacitor Resistance Circuits

Switched Capacitor
Schematic
Equivalent
Resistor Emulation
Resistance
Circuit
1
Parallel
v1(t) C
v2 (t)
Series
v1(t)
C
1
Series-Parallel
v1(t)
T
C
v2 (t)
T
C1 + C2
C1
C2
2
C
v1(t)
v2 (t)
Bilinear
T
C
v2 (t)
T
4C
P.E. Allen - 2004
Page 9.1-8
Accuracy of Switched Capacitor Circuits

Consider the following continuous time, first-order, lowpass
circuit:
R1
v2
v1
C2
The transfer function of this simple circuit is,
V2(j)
1
1
Fig. 9.1-06
H(j) = V (j) = jR C + 1 = j + 1
1
1 2
1
where 1 = R1C2 is the time constant of the circuit and determines the accuracy.
Continuous Time Accuracy
Let 1 = C. The accuracy of C can be expressed as,
dC dR1 dC2
C = R1 + C2 5% to 20% depending on the size of the components
Discrete Time Accuracy
T
1
Let 1 = D = C1 C2 = fcC1 C2. The accuracy of D can be expressed as,
dD dC2 dC1 dfc
D = C2 - C1 - fc 0.1% to 1% depending on the size of components
The above is the primary reason for the success of switched capacitor circuits in CMOS
technology.
P.E. Allen - 2004
Page 9.1-9
ANALYSIS OF SWITCHED CAPACITOR CIRCUITS

Analysis Methods for Two-Phase, Nonoverlapping Clocks
Sampled Data Voltage Waveforms for a Two-phase Clock:
v*(t)
v(t)
A sampled-data
voltage waveform
for a two-phase
clock.
1
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5
t/T
vO(t)
v(t)
A sampled-data
voltage waveform
for the odd-phase
clock.
1
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5
A sampled-data v (t)
voltage waveform
for the even-phase
clock.
t/T
v(t)
Fig. 9.1-065
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5
t/T
P.E. Allen - 2004
Page 9.1-10
Analysis Methods for Two-Phase, Nonoverlapping Clocks - Contd

Time-domain Relationships:
The previous figure showed that,
v*(t) = vo(t) + ve(t)
where the superscript o denotes the odd phase (1) and the superscript e denotes the
even phase (2).
For any given sample point, t = nT/2, the above may be expressed as
nT
nT
nT
v* 2 n=1,2,3,4,5,6, = v o 2 n=1,3,5, + v e 2 n=2,4,5,
z-domain Relationships:
Consider the one-sided z-transform of a sequence, v(nT), defined as
V(z) = v(nT)z- n = v(0) + v(T)z- 1 + v(2T)z- 2 +

n=0
for all z for which the series V(z) converges.

Now, this equation can be expressed in the z-domain as
V*(z) = V o(z) + V e(z) .
The z-domain format for switched capacitor circuits will allow the analysis of transfer
functions.
P.E. Allen - 2004
Page 9.1-11
Transfer Function Viewpoint of Switched Capacitor Circuits

Input-output voltages of a general switched capacitor circuit in the z-domain.
Vi (z) =
o
Vi (z)
Switched
Capacitor
Circuit
+ Vi (z)
Vo (z) = Vo (z) + Vo (z)
Fig. 9.1-07
z-domain transfer functions:

j
V o (z)
H ij (z) = i
V i(z)
e
where i and j can be either e or o. For example, Hoe(z) represents Vo (z)/ V i (z) .
Also, a transfer function, H(z) can be defined as
e
Vo(z) Vo(z) + Vo (z)

H(z) = Vi(z) = e
.
o
V i (z) + V i (z)
P.E. Allen - 2004
Page 9.1-12
Approach for Analyzing Switched Capacitor Circuits

1.) Analyze the circuit in the time-domain during a selected phase period.
2.) The resulting equations are based on q = Cv.
3.) Analyze the following phase period carrying over the initial conditions from the
previous analysis.
4.) Identify the time-domain equation that relates the desired voltage variables.
5.) Convert this equation to the z-domain.
6.) Solve for the desired z-domain transfer function.
7.) Replace z by ejT and examine the frequency response.
P.E. Allen - 2004
Page 9.1-13
Example 9.1-3 - Analysis of a Switched Capacitor, First-order, Low pass Filter

Use the above approach to find the z-domain transfer function of the first-order, low
pass switched capacitor circuit shown below. This circuit was developed by replacing
the resistor, R1, of the previous circuit with the parallel switched capacitor resistor circuit.
The timing of the clocks is also shown. This timing is arbitrary and is used to assist the
analysis and does not change the result.
1
v1
C1
C2
v2
Switched capacitor, low pass filter.
1
1
2
2
2
t
n- 23 n-1 n- 21 n n+ 21 n+1 T
Clock phasing for this example.
Fig. 9.1-08
Solution
1: (n-1)T< t < (n-0.5)T
Equivalent circuit:
C2
v1o(n-1)T C1
C2
v2e(n- 23 )T v2o(n-1)T
Equivalent circuit.
v1o(n-1)T C1
v2e(n- 23 )T v2o(n-1)T
Simplified equivalent circuit.
The voltage at the output (across C2) is vo2(n-1)T = ve2 (n-3/2)T

Fig. 9.1-09
(1)
P.E. Allen - 2004
Page 9.1-14
Example 9.1-3 - Continued

2: (n-0.5)T< t < nT
Equivalent circuit:
C1
e
v1(n-1/2)T
C2
C1 vo(n-1)T
1
v2e(n- 21 )T
v2o(n-1)T
Fig. 9.1-10
The output of this circuit can be expressed as the superposition of two voltage
sources, vo1 (n-1)T and vo2 (n-1)T given as
C1
C2
ve2 (n-1/2)T = C1+C2 vo1 (n-1)T + C1+C2 vo2 (n-1)T.
If we advance Eq. (1) by one full period, T, it can be rewritten as

vo2(n)T = ve2 (n-1/2)T.
Substituting, Eq. (3) into Eq. (2) yields the desired result given as
C1
C2
vo2 (nT) = C +C vo1 (n-1)T + C +C vo2 (n-1)T.
1
2
1
2
(2)
(3)
(4)
P.E. Allen - 2004
Page 9.1-15

z-domain Analysis:
The next step is to write the z-domain equivalent expression for Eq. (4). This can be
done term by term using the sequence shifting property given as
(5)
v(n-n1)T z-n1V(z) .
The result is
C1 -1
C2 -1
Vo2(z) = C +C z Vo1(z) + C +C z Vo2(z).
(6)
1
2
1
2
Finally, solving for V2o(z)/Vo1(z) gives the desired z-domain transfer function for the
switched capacitor circuit of this example as
C1
-1
o
z
V2(z)
z-1
C2
C1+C2
oo
-1 , where =
H (z) = o =
=
(7)
C2
1 + - z
C1 .
V 1(z)
-1
1 - z C1+C2
P.E. Allen - 2004
Page 9.1-16
Discrete-Frequency Domain Analysis

Relationship between the continuous and discrete frequency domains:
z = e j T
Illustration:
j
Continuous
time frequency
response
Discrete
time frequency
response
=0
-1
Imaginary Axis
+j1
r=1
=
= -
=0
+1 Real
Axis
= -
Continuous Frequency Domain
-j1
Discrete Frequency Domain
Fig. 9.1-11
P.E. Allen - 2004
Page 9.1-17
Example 9.1-4 - Frequency Response of Example 9.1-3

Use the results of the previous example to find the magnitude and phase of the
discrete time frequency response for the switched capacitor circuit of Example 3.
Solution
The first step is to replace z in Hoo(z) of Ex. 3 by e jT. The result is given below as
e-jT
1
1
Hooej = 1+- e-jT = (1+)ejT- = (1+)cos(T)- +j(1+)sin(T)
(1)
where we have used Eulers formula to replace e jT by cos(T)+jsin(T). The magnitude
of Eq. (1) is found by taking the square root of the square of the real and imaginary
components of the denominator to give
1
Hoo =
2
2
(1+) cos (T) - 2(1+)cos(T) + 2 + (1+)2sin2(T)
1
= (1+)2[cos2(T)+sin2(T)]+2-2(1+)cos(T)
1
1
(2)
= 1+2+2 -2(1+)cos(T) = 1+2(1+)(1-cos(T)) .
The phase shift of Eq. (1) is expressed as
(1+)sin(T)
sin(T)
(3)
ArgHoo = - tan-1(1+)cos(T)- = - tan-1

cos(T) - 1+
P.E. Allen - 2004
Page 9.1-18
The Oversampling Assumption

The oversampling assumption is simply to assume that fsignal << fclock = fc.
This means that,
2
1
fsignal = f << T 2f = << T T << 2.
The importance of the oversampling assumption is that is permits the design of switched
capacitor circuits that approximates the continuous time circuit until the signal frequency
begins to approach the clock frequency.
P.E. Allen - 2004
Page 9.1-19
Example 9.1-5 - Design of Switched Capacitor Circuit and Resulting Frequency

Response
Design the first-order, low pass, switched capacitor circuit of Ex. 3 to have a -3dB
frequency at 1kHz. Assume that the clock frequency is 20kHz Plot the frequency
response for the resulting discrete time circuit and compare with a first-order, low pass,
continuous time filter.
Solution
If we assume that T is less than unity, then cos(T) approaches 1 and sin(T)
approaches T. Substituting these approximations into the magnitude response of Eq. (2)
of Ex. 4 results in
1
1
(1)
Hoo(ejT) (1+) - + j(1+) = 1 + j(1+)T .
Comparing this equation to the simple, first-order, low pass continuous time circuit
results in the following relationship which permits the design of the circuit parameter .
1 = (1+)T
(2)
Solving for gives
1
c
fc
= T - 1 = fc1 - 1 = -3dB - 1 = 2-3dB - 1 .
(3)
Using the values given, we see that = (20/6.28)-1 =2.1831. Therefore, C2 = 2.1831C1.
P.E. Allen - 2004
Page 9.1-20

Frequency Response of the First-order, Switched Capacitor, Low Pass Circuit:
100
0.8
0.707
0.6
Phase Shift (Degrees)
Magnitude
oo jT
|H (e
)|
0.4
0.2
0
|H(j)|
= 1/1
0
0.2
0.4
/c
0.6
0.8
50
oo jT
Arg[H (e
= 1/1
0
-50
-100
)]
Arg[H(j)]
0
0.2
0.4
/c
0.6
0.8
Fig. 9.1-12
Better results would be obtained if fc > 20kHz.
P.E. Allen - 2004
Page 9.1-21
SUMMARY
Resistance emulation is the replacement of continuous time resistors with switched
capacitor approximations
- Parallel switched capacitor resistor emulation
- Series switched capacitor resistor emulation
- Series-parallel switched capacitor resistor emulation
- Bilinear switched capacitor resistor emulation
Time constant accuracy of switched capacitor circuits is proportional to the
capacitance ratio and the clock frequency
Analysis of switched capacitor circuits includes the following steps:
1.) Analyze the circuit in the time-domain during a selected phase period.
2.) The resulting equations are based on q = Cv.
3.) Analyze the following phase period carrying over the initial conditions from the
previous analysis.
4.) Identify the time-domain equation that relates the desired voltage variables.
5.) Convert this equation to the z-domain.
6.) Solve for the desired z-domain transfer function.
7.) Replace z by ejT and examine the frequency response.
P.E. Allen - 2004
Page 9.2-1
SECTION 9.2 SWITCHED CAPACITOR AMPLIFIERS

CONTINUOUS TIME AMPLIFIERS
Inverting and Noninverting Amplifiers
R2
R1
vIN
vOUT
vIN
R2
R1
vOUT
Fig. 9.2-01
Gain and GB = :
Vout R1+R2
Vin = R1
Gain , GB = :
Avd(0)R1
R1+R2
Vout(s) R1+R2
=
Avd(0)R1
Vin(s) R1
1 + R1+R2
Gain , GB :
GBR1
R1+R2 H
Vout(s) R1+R2 R1+R2
GBR1 = R1 s+H
Vin(s) = R1
s + R1+R2
Vout
R2
=
Vin
R1
R1Avd(0)
R2
Vout(s)
R1+R2
Vin(s)
Avd(0)R1
R1
1 + R1+R2
GBR1
R2 H
Vout(s) R2 R1+R2
=
=
GBR1 - R1 s+H
Vin(s) R1
s + R1+R2
P.E. Allen - 2004
Page 9.2-2
Example 9.2-1- Accuracy Limitation of Voltage Amplifiers due to a Finite Voltage

Gain
Assume that the noninverting and inverting voltage amplifiers have been designed for
a voltage gain of +10 and -10. If Avd(0) is 1000, find the actual voltage gains for each
amplifier.
Solution
For the noninverting amplifier, the ratio of R2/R1 is 9.
1000
Avd(0)R1/(R1+R2) = 1+9 = 100.
Vout
100
Vin = 10 101 = 9.901 rather than 10.
For the inverting amplifier, the ratio of R2/R1 is 10.
Avd(0)R1 1000
R1+R2 = 1+10 = 90.909
Vout
90.909
Vin = -(10)1+90.909 = - 9.891 rather than -10.
P.E. Allen - 2004
Page 9.2-3
Example 9.2-2 - -3dB Frequency of Voltage Amplifiers due to Finite UnityGainbandwidth

Assume that the noninverting and inverting voltage amplifiers have been designed for
a voltage gain of +1 and -1. If the unity-gainbandwidth, GB, of the op amps are
2Mrads/sec, find the upper -3dB frequency for each amplifier.
Solution
In both cases, the upper -3dB frequency is given by
GBR1
H = R1+R2
For the noninverting amplifier with an ideal gain of +1, the value of R2/R1 is zero.
H = GB = 2 Mrads/sec (1MHz)
For the inverting amplifier with an ideal gain of -1, the value of R2/R1 is one.
GB1 GB
H = 1+1 = 2 = Mrads/sec (500kHz)
P.E. Allen - 2004
Page 9.2-4
CHARGE AMPLIFIERS
Noninverting and Inverting Charge Amplifiers
C2
C1
vIN
vOUT
C2
C1
vOUT
Noninverting Charge Amplifier
Gain and GB = :
Vout C1+C2
Vin = C2
Gain , GB = :
Avd(0)C2
Vout C1+C2 C1+C2
Vin = C2
Avd(0)C2
1 + C1+C2
Gain , GB :
GBC2
Vout C1+C2 C1+C2
Vin = C2
GBC2
s + C1+C2
vIN
Inverting Charge Amplifier
Vout
C1
=
Vin
C2
Avd(0)C2
Vout C1 C1+C2
Vin = -C2
Avd(0)C2
1 + C1+C2
GBC2
Vout C1 C1+C2
Vin = -C2
GBC2
s + C1+C2
P.E. Allen - 2004
Page 9.2-5
SWITCHED CAPACITOR AMPLIFIERS

Parallel Switched Capacitor Amplifier
1
vin
+
C1
vC1
+
vC2
-
C2
vout
vin
C1
+
-
vC2
vout
+
C2
vC1
Modification to prevent open-loop operation
Inverting Switched Capacitor Amplifier
Analysis:
Find the even-odd and the even-even z-domain
transfer function for the above switched capacitor
inverting amplifier.
1: (n -1)T < t < (n -0.5)T
n- 23 n-1 n- 21
n+ 21 n+1 T
o
vC1
(n -1)T = vino (n -1)T
and
o
vC2(n -1)T = 0
P.E. Allen - 2004
Page 9.2-6
Parallel Switched Capacitor Amplifier- Continued

2: (n -0.5)T < t < nT
vC2 = 0 v e
t=0
- + out (n-1/2)T
Equivalent circuit:
+
C1
From the simplified

equivalent circuit we
write,
+ o
vin (n-1)T
-
C1
vino (n-1)T
Equivalent circuit at the moment 2 closes.
vC2 = 0 e
- + vout (n-1/2)T
C2
vC1 = 0
- +
+
C1
e
o
vout (n-1/2)T = - C2 vin (n-1)T
Converting to the z-domain gives,

C1
e
o
z -1/2 Vout
(z) = -C2 z -1 Vin
(z)
Multiplying by z1/2 gives,
C1
e
o
V out
(z) = -C z -1/ 2 Vin
(z)
2
Solving for the even-odd transfer function, Hoe (z), gives, Hoe (z) =
e
V out
(z)
o
Vin (z)
C1
= -C2 z -1/ 2
P.E. Allen - 2004
Page 9.2-7
Parallel Switched Capacitor Amplifier- Continued

Solving for the even-even transfer function, Hee (z).
o
Assume that the applied input signal, vin (n-1)T, was unchanged during the previous
2 phase period(from t = (n-3/2)T to t = (n-1)T), then
o
vin (n-1)T = vin (n-3/2)T

which gives
o
V in(z) = z -1/2 Vin(z) .

Substituting this relationship into Hoe(z) gives
C1
e
e
V out(z) = -C z -1 Vin(z)
2
or
e
Hee (z) =
V out(z)
e
Vin(z)
C1
= -C2 z -1
P.E. Allen - 2004
Page 9.2-8
Frequency Response of Switched Capacitor Amplifiers

Replace z by e jT.
e
Hoe (e jT)
V out( e jT)
e
Vout( e jT)
C1
= - C2 e -jT/2
and
e
Hee (e jT) =
V out(e jT)
o
Vout( e jT)
C1
= -C2 e -jT
If C1/C2 = R2/R1, then the magnitude response is identical to inverting unity gain amp.
However, the phase shift of Hoe(e jT) is
Arg[Hoe(e jT)] = 180 - T/2
and the phase shift of Hee(e jT) is
Arg[Hee(e jT)] = 180 - T.
Comments:
The phase shift of the SC inverting amplifier has an excess linear phase delay.
When the frequency is equal to 0.5fc, this delay is 90.
One must be careful when using switched capacitor circuits in a feedback loop
because of the excess phase delay.
P.E. Allen - 2004
Page 9.2-9
Positive and Negative Transresistance Equivalent Circuits

Transresistance circuits are two-port networks where the voltage across one port
controls the current flowing between the ports. Typically, one of the ports is at zero
potential (virtual ground).
i1(t) 1
i1(t)
vC(t)
vC(t)
i2(t)
i2(t)
Circuits:
2
2
2
C
v1(t)
CP
v1(t)
CP
C
2
CP
CP
Negative Transresistance Realization.
Positive Transresistance Realization.
Analysis (Negative transresistance realization):

v1(t)
v1
RT = i2(t) = i2(average)
If we assume v1(t) is constant over one period of the clock, then we can write
q2(T) - q2(T/2) CvC(T) - CvC(T/2) -Cv1
1 T
=
= T
i2(average) = T i2(t)dt =
T
T
T/2
Substituting this expression into the one above shows that
RT = -T/C
Similarly, it can be shown that the positive transresistance is T/C.

These circuits are insensitive to the parasitic capacitances shown as dotted capacitors.
P.E. Allen - 2004
Page 9.2-10
Noninverting Stray Insensitive Switched Capacitor Amplifier

Analysis:
1
1
2
2
2
t
T
1: (n -1)T < t < (n -0.5)T
1
3
1
n- 2 n-1 n- 2 n n+ 2 n+1
The voltages across each capacitor can be written as
o
o
vC1(n -1)T = vin(n -1)T
1
and
vC2
vC1(t)
vin 1
vout
2
o
o
- +
vC2(n -1)T = vout(n -1)T = 0 .
C2
C1
2: (n -0.5)T < t < nT
2
1
The voltage across C2 is
+
C
o
e
1
vout(n -1/2)T = C2 vin(n -1)T
Noninverting Switched Capacitor Voltage Amplifier.
C1
C1
o
e
V out(z) = C2 z -1/2 Vin(z) Hoe(z) = C2 z-1/2
If the applied input signal, vin(n -1)T, was unchanged during the previous 2 phase, then,
C1
e
e
V out(z) = C2 z-1 Vin(z)
C1
Hee(z) = C2 z-1
Comments:
Excess phase of H oe(e jT) is -T/2 and for H ee(e jT) is -T
P.E. Allen - 2004
Page 9.2-11
Inverting Stray Insensitive Switched Capacitor Amplifier

Analysis:
1: (n -1)T < t < (n -0.5)T
vC1(t)
The voltages across each capacitor can
vin 2
be written as
C1
vC1(n -1)T = 0
and
vC1(t)
o
o
vout(n
-1)T = 0 .
vC2(n -1)T =
2: (n -0.5)T < t < nT
The voltage across C2 is
C1 e
e
vout(n -1/2)T = - C2 vin(n -1/2)T
C1 e
e
V out(z) = - C2V in(z)
vC2
vout
+
C2
Inverting Switched Capacitor Voltage Amplifier.
C1
Hoe(z) = - C
Comments:
The inverting switched capacitor amplifier has no excess phase delay.
There is no transfer of charge during 1.
P.E. Allen - 2004
Page 9.2-12
Example 9.2-3 - Design of a Switched Capacitor Summing Amplifier

Design a switched capacitor summing
10C 2
1
amplifier using the stray insensitive transresistv1
ance circuits to gives the output voltage during
the 2 phase period that is equal to 10v1 - 5v2,
2
1
where v1 and v2 are held constant during a 2-1
period and then resampled for the next period.
5C 2
v2 2
Solution
A possible solution is shown. Considering
1
1
each of the inputs separately, we can write that
e (n-1/2)T = 10vo(n-1)T
vo1
1
and
e
vo2
(n-1/2)T = -5ve2(n-1/2)T .
vo
(1)
(2)
Because vo1(n-1)T = v1e (n-3/2)T, Eq. (1) can be rewritten as

e
(n-1/2)T = 10ve1(n-3/2)T .
vo1
Combining Eqs. (2) and (3) gives
e
e
(n-1/2)T + vo2
(n-1/2)T = 10ve1(n-3/2)T - 5ve2(n-1/2)T .
veo(n-1/2)T = vo1
or
Veo(z) = 10z-1Ve1(z) - 5Ve2(z) .
(3)
(4)
(5)
P.E. Allen - 2004
Page 9.2-13
NONIDEALITIES OF SWITCHED CAPACITOR CIRCUITS

Switches
Covered in Chapter 4.
Capacitors
Covered in Chapter 2.
P.E. Allen - 2004
Page 9.2-14
Example 9.2-4 Influence of Clock Feedthrough on a Noninverting Switched

Capacitor Amplifier
A
noninverting,
switched
capacitor voltage amplifier is
1
COL
COL
shown. The switch overlap
capacitors, COL are assumed to
2
1
be 100fF each and C1 = C2 =
COL
COL
COL
COL
M5
1pF. If the switches have a W
v
(t)
v
C
vout
= 1m and L = 1m and the vin
- C2 +
nonoverlapping clock of 0 to 5V
M4
M1
C2
C
COL
COL
amplitude has a rate of rise and
1
fall of 0.5x109 volts/second,
M3 M2
2
1
+
find the actual value of the
C
COL
OL
output voltage when a 1V
signal is applied to the input.
Fig. 9.2-9
Solution
We will break this example into three time sequences. The first will be when 1 turns
off (1off), the second when 2 turns on (2on), and the third when 2 turns off (2off).
P.E. Allen - 2004
Example 9.2-4 Continued

1 turning off
M1:
The value of VHT is given as
Page 9.2-15
COL
COL
COL
COL
COL
vC(t)
vin
VHT = 5V-1V-0.7V = 3.3V

C1
M3 M2
2
1
Therefore, the value of VHT2/2CL is found as
COL
COL
VHT2 110x10-6(3.3)2
= 0.599x109V/sec.
2CL =
2x10-12
This corresponds to the slow transition mode. Using the previous model gives
220x10-18+(0.5)(24.7)(10-16)
10910-12 220x10-18
Verror =
10-12
2110x10-6 - 10-12 (1+1.4+0)
M1
COL
M4
COL
COL
M5
vC2
+
C2
-
vout
+
Fig. 9.2-9
= (0.001455)(3.779) - 220x10-6(2.4) = 5.498mV-0.528mV = 4.97mV

M2:
The value of VHT for M2 is given as
VHT = 5V-0V-0.7V = 4.3V
2
The value of VHT /2CL is found as
VHT2 110x10-6(4.3)2
= 1.017x109V/sec.
2CL =
2x10-12
P.E. Allen - 2004
Page 9.2-16

Therefore, M2 is also in the slow transition mode. The error voltage is found as
10910-12 220x10-18
220x10-18+(0.5)(24.7)(10-16)
Verror =
2110x10-6 - 10-12 (0+1.4+0)

10-12
= (0.001455)(3.779) - 220x10-6(1.4) = 5.498mV-0.308mV = 5.19mV

Therefore, the net error on the C1 capacitor at the end of the 1 phase is
vC1(1off) = 1.0 - 0.00497 + 0.00519 = 1.00022V
1
COL
COL
We see that the influence of vin 0V is to cause the
2
1
M5
feedthrough from M1 and M2 not to cancel COL COL vC(t) COL COL
v
vin
vout
- C2 +
completely.
M4
M1
C
2
C1
COL
COL
M5:
M3 M2
2
1
+
COL
COL
We must also consider the influence of M5 turning
off. In order to use the previous model for M5, we will
Fig. 9.2-9
assume that feedthrough of M5 via a virtual ground is valid for the previous model given
for feedthrough. Based on this assumption, M5 will have the same feedthrough as M2
which is 5.19mV. This voltage error will left on C2 at the end of the 1 and is
vC2(1off) = 0.00519V.
P.E. Allen - 2004
Page 9.2-17

1
COL
COL
2 turning on
2
1
During the turn-on part of 2, M3 and M4 will COL COL
COL
COL
M5
vC(t)
v
feedthrough onto C1 and C2. However, it is easy to vin
vout
- C2 +
M4
M1
C
show that the influence of M3 and M4 will cancel
2
C1
COL
COL
each other for C1. Therefore, we need only consider
M3
M2
2
1
+
COL
COL
the feedthrough of M4 and its influence on C2.
Fig. 9.2-9
Interestingly enough, the feedthrough of M4 onto C2
is exactly equal and opposite to the previous feedthrough by M5. As a result, the value of
voltage on C2 after 2 has stabilized is
C1
vC2(2on) = 0.00519V-0.00519V + C2 vc1(1off) = 1.00022V
2 turning off
Finally, as switch M4 turns off, there will be feedthrough onto C2. Since, M4 has one
of its terminals at 0V, the feedthrough is the same as before and is 5.19mV. The final
voltage across C2, and therefore the output voltage vout, is given as
vout(2off) = vC2(2off) = 1.00022V + 0.00519V = 1.00541V
It is interesting to note that the last feedthrough has the most influence.
P.E. Allen - 2004
Page 9.2-18
NONIDEAL OP AMPS - FINITE GAIN

Finite Amplifier Gain
Consider the noninverting switched capacitor amplifier during 2:
C1
vino (n-1)T
+
C2
e
vout
(n-1/2)T
Avd(0)
+
e
vout
(n-1/2)T
Op amp with finite

value of Avd(0)
Fig. 9.2-11
The output during 2 can be written as,

e
C1+C2 vout(n -1/2)T

C1 o
v (n -1/2)T = C2 vin(n -1)T + C2 Avd(0)
Converting this to the z-domain and solving for the Hoe(z) transfer function gives
e
out
Vout(z) C1 -1/2
1
.
= C2 z
Hoe(z) = o
+
C
C
1
2
V in(z)
1 - Avd(0)C2
Comments:
The phase response is unaffected by the finite gain
A gain of 1000 gives a magnitude of 0.998 rather than 1.0.
P.E. Allen - 2004
Page 9.2-19
Nonideal Op Amps - Finite Bandwidth and Slew Rate

Finite GB:
In general the analysis is complicated. (We will provide more detail for integrators.)
The clock period, T, should be equal to or less that 10/GB.
The settling time of the op amp must be less that T/2.
Slew Rate:
The slew rate of the op amp should be large enough so that the op amp can make a
full swing within T/2.
P.E. Allen - 2004
Page 9.2-20
SUMMARY
Continuous time amplifiers are influenced by the gain and gainbandwidth of the op amp
Charge amplifiers are also influenced by the gain and the gainbandwidth of the op amp
Switched capacitor amplifiers replace the resistors of the continuous time amplifier with
switched capacitor equivalents
The transresistor SC amplifiers can be inverting and noninverting with the positive
input terminal of the op amp on ground
The nonidealities of the SC amplifier include:
- Switches
- Capacitors
- Op amp finite gain
- Op amp finite GB
P.E. Allen - 2004
Page 9.3-1
SECTION 9.3 SWITCHED CAPACITOR INTEGRATORS

Continuous Time Integrators
Vin
R1
C2
Vout
Vin
C2
R1
Vout
+
Inverter
(b.)
(a.)
(a.) Noninverting and (b.) inverting continuous time integrators.

Ideal Performance:
NoninvertingInvertingI -jI
1
Vout(j)
-1
- I j I
Vout(j)
=
=
=
=
=
Vin(j) j R 1C2 j
Vin(j) j R 1C2 j =
Frequency Response:
|Vout(j)/Vin(j)|
Arg[Vout(j)/Vin(j)]
40 dB
90
20 dB
0 dB
-20 dB
I I I
100 10
10I 100I
0
log10
log10
-40 dB
(a.)
(b.)
P.E. Allen - 2004
Page 9.3-2
Continuous Time Integrators - Nonideal Performance

Finite Gain:
Avd(s) (s/)
Avd(s) sR1C2
I
Vout 1 sR1C2 + 1
(s/) + 1
=
=
Vin
Avd(s) (s/)
Avd(s) sR1C2 s
sR1C2
1 + (s/) + 1
1 + sR1C2+1
Avd(0)a GB GB
where
Avd(s) = s+a = s+a s
Vout
Case 1: s 0 Avd(s) = Avd(0) Vin - Avd(0)
GB I
GB
Vout
Case 2: s Avd(s) = s
V - s s
in
Vout
I
V - s
Case 3: 0 < s < Avd(s) =
in
|Vout(j)/Vin(j)|
Avd(0) dB
Eq. (1)
0 dB
Eq. (3)
I
x1 = I
Avd(0)
(2)
(3)
Arg[Vout(j)/Vin(j)]
I
180
10Avd(0) 10I
135
Avd(0)
x2 = GB
log10
Eq. (2)
(1)
90
45
0
GB
10
10GB
I
Avd(0)
GB
log10
P.E. Allen - 2004
Page 9.3-3
Example 9.3-1 - Frequency Range over which the Continuous Time Integrator is
Ideal
Find the range of frequencies over which the continuous time integrator
approximates ideal behavior if Avd(0) and GB of the op amp are 1000 and 1MHz,
respectively. Assume that I is 2000 radians/sec.
Solution
The idealness of an integrator is determined by how close the phase shift is to
90 (+90 for an inverting integrator and -90 for a noninverting integrator).
The actual phase shift in the asymptotic plot of the integrator is approximately 6 above
90 at the frequency 10I/Avd(0) and approximately 6 below 90 at GB /10.
Assume for this example that a 6 tolerance is satisfactory. The frequency range can be
found by evaluating 10I/Avd(0) and GB/10.
Therefore the range over which the integrator approximates ideal behavior is from 10Hz
to 100kHz. This range will decrease as the phase tolerance is decreased.
P.E. Allen - 2004
Page 9.3-4
Noninverting Switched Capacitor Integrator

Analysis:
1: (n -1)T < t < (n -0.5)T
vC1(t)
vin 1
- 2
+
The voltage across each capacitor is
S1
S4
o
o
C1
vc1(n-1)T = vin(n-1)T
S2
S3
2
1
and
o
vC2
vout
+
C2
vc2(n-1)T = vout(n-1)T .
2: (n -0.5)T < t < n T
Equivalent circuit:
Noninverting, stray insensitive integrator.
o
vC2 = vout
(n-1)T e
vout (n-1/2)T
- +
C2
- o2
vin (n-1)T
+
+
t=0
vC1 = 0
+ -
t=0
C1
2
Equivalent circuit at the moment the 2 switches close.
vino(n-1)T
C1
o
vout
(n-1)T C e
2 vout (n-1/2)T
+
- +
vC2 = 0
-
C1 o
e
o
We can write that, vout(n -1/2)T = C2 vin(n -1)T + vout(n -1)T
P.E. Allen - 2004
Page 9.3-5
Noninverting Switched Capacitor Integrator - Continued

1: nT < t < (n + 0.5)T
If we advance one more phase period, i.e. t = (n)T to t = (n+1/2)T, we see that the
voltage at the output is unchanged. Thus, we may write
o
e
vout(n)T = vout(n-1/2)T .
Substituting this relationship into the previous gives the desired time relationship
expressed as
C1 o
o
o
vout(n)T = C2 vin(n -1)T + vout(n -1)T .
Transferring this equation to the z-domain gives,
o
C1
Vout(z) C1 z-1 C1 1
o
o
o
-1
-1
V out(z) = C2 z Vin(z) + z Vout(z) Hoo(z) = o = C2 1-z-1 = C2 z-1
V in(z)
Replacing z by ej gives,
o
C1
Vout( e j) C1 1
e-j/2
j
oo
H (e ) = o j = C2 e j -1 = C2 e j/2 - e-j/2
V in( e )
Replacing ej/2 - e-j/2 by its equivalent trigonometric identity, the above becomes
o
Hoo(e
T
C1
V out(e j) C1
e-j/2
T/2
) = o j = C2 j2 sin(T/2) T = jTC2 sin(T/2) e-j/2
V in( e )
Hoo(ejT) = (Ideal)x(Magnitude error)x(Phase error) where I = C1/TC2 Ideal = I/j

P.E. Allen - 2004
Page 9.3-6
Example 9.3-2 - Comparison of a Continuous Time and Switched Capacitor

Integrator
Assume that I is equal to 0.1c and plot the magnitude and phase response of the
noninverting continuous time and switched capacitor integrator from 0 to c.
Solution
Letting I be 0.1c gives
1 /c
1
H(j) = 10j/ and Hoo(e j) = 10j/ sin(/ ) e-j/c
c
c
c
Plots:
0
5
Magnitude
-50
Arg[H(j)]
-100
3
oo j T
|H (e
)|
2
1
-200
|H(j)|
Arg[H oo(ej T)]
-150
-250
-300
0
0
0.2
0.4
/ c
0.6
0.8
0.2
0.4
0.6
/
c
0.8
P.E. Allen - 2004
Page 9.3-7
Inverting Switched Capacitor Integrator

Analysis:
1: (n -1)T < t < (n -0.5)T
The voltage across each capacitor is
vin
vC1(t)
S1
o
c1
v (n -1)T = 0
C1
S2
S4
S3
vC2
+
C2
vout
and
3
o
o
e
vc2(n -1)T = vout(n -1)T = vout(n -2)T.
Inverting, stray insensitive integrator.
2: (n -0.5)T < t < n T
Equivalent circuit:
C1
t=0
t=0
2 vC1 = 0 2
vine(n-1/2)T
vC2 =
e
vout
(n-3/2)T e
- + vout (n-1/2)T
C2
+
Equivalent circuit at the moment the 2 switches close.
vine (n-1/2)T
e
vC1 = 0 vout (n-3/2)T C2 e
vout (n-1/2)T
+
- + - +
vC2 = 0
+
C1
-
Now we can write that,

C1 e
e
e
vout(n-1/2)T = vout(n-3/2)T - C2 vin(n-1/2)T . (22)
P.E. Allen - 2004
Page 9.3-8
Inverting Switched Capacitor Integrator - Continued

Expressing the previous equation in terms of the z-domain equivalent gives,
e
C1
C1 1
C1 z
Vout(z)
e
e
-1 e
V out(z) = z Vout(z) - C2 Vin(z) Hee(z) = e = - C2 1-z-1 = - C2 z-1
V in(z)
j
To get the frequency response, we replace z by e giving,
e
j
j
out( e
C1 e
C1
)
V
e j/2
j
ee
j
H (e ) = e j = - C2 e -1 = - C2 e j/2 - e-j/2
V in( e )
j/2
Replacing e - e-j/2 by 2j sin(T/2) and simplifying gives,
e
j
out(e )
C1
V
T/2
j
ee
H (e ) = e j = - jTC2 sin(T/2) e j/2
V in( e )
Same as noninverting integrator except for phase error.
Consequently, the magnitude response is identical but the phase response is given as
Arg[Hee(e j)] = 2 + 2 .
Comments:
The phase error is + for the inverting integrator and - for the noninverting integrator.
The cascade of an inverting and noninverting switched capacitor integrator has no
phase error.
P.E. Allen - 2004
Page 9.3-9
A Sign Multiplexer
A circuit that changes the 1 and 2 of the leftmost switches of the stray insensitive,
switched capacitor integrator.
1
2
x
VC
To switch connected
to the input signal (S1).
VC
To the left most switch

connected to ground (S2).
Fig. 9.3-8
This circuit steers the 1 and 2 clocks to the input switch (S1) and the leftmost switch
connected to ground (S2) as a function of whether Vc is high or low.
P.E. Allen - 2004
Page 9.3-10
Switched Capacitor Integrators - Finite Op Amp Gain

Consider the following circuit which is equivalent
of the noninverting integrator at the beginning of
the 2 phase period.
vino (n-1)T
e
out
o
vout
(n-1)T
Avd(0)
e
C2 vout (n-1/2)T
+
- +
vC2 = 0
-
o
vout
(n-1)T -
vC1 = 0
- +
e
C1 vout (n-1/2)T
Avd(0)
+
-
The expression for v (n-1/2)T can be written as

o
e
C1 o
vout(n-1)T vout(n-1/2)T C1+C2
e
o
vout(n-1/2)T = C2 vin(n-1)T + vout(n-1)T - Avd(0) + Avd(0) C2
o
Fig. 9.3-10
Substituting vout(n)T = vout(n -0.5)T into this equation gives

o
o
C1 o
vout(n-1)T vout(n)T C1+C2
o
o
vout(n)T = C2 vin(n-1)T + vout(n-1)T - Avd(0) + Avd(0) C2
Using the previous approach to solve for the z-domain transfer function results in,
o
Vout(z)
(C1/C2) z-1
oo
H (z) = o =
z -1
z-1
C1
1 z-1
V in(z)
-1
1 - z + Avd(0) - Avd(0)C2 z-1 + Avd(0) z-1
or
o
Vout(z) (C1/C2) z-1

HI(z)
1
=
oo
-1
H (z) = o = 1 - z
C1
C1
1
1

V in(z)
1 - Avd(0) - Avd(0)C2(1-z-1) 1 - Avd(0) - Avd(0)C2(1-z-1)
P.E. Allen - 2004
Page 9.3-11
Finite Op Amp Gain - Continued

Substitute the z-domain variable, z, with ejT to get
H I(e jT)
j
T
Hoo(e ) =
1
C1
C1/C2
1 - Avd(0) 1 + 2C2 - j
T
2Avd(0) tan 2
where now HI(e jT) is the integrator transfer function for Avd(0) = .
The error of an integrator can be expressed as
HI(j)
H(j) = [1-m()] e-j()
where
m() = the magnitude error due to Avd(0)
() = the phase error due to Avd(0)
If () is much less than unity, then this expression can be approximated by
HI(j)
H(j) 1 - m() - j()
Comparing Eq. (1) with Eq. (2) gives m() and ()due to a finite value of Avd(0) as
1
C1/C2
C1
m(j) = - A (0) 1 + 2C and (j) = 2A (0) tan(T/2)
vd
2
vd
(1)
(2)
P.E. Allen - 2004
Page 9.3-12
Example 9.3-3 - Evaluation of the Integrator Errors due to a finite value of Av d(0)
Assume that the clock frequency and integrator frequency of a switch capacitor
integrator is 100kHz and 10kHz, respectively. If the value of Avd(0) is 100, find the value
of m(j) and (j) at 10kHz.
Solution
The ratio of C1 to C2 is found as
C1
210,000
=
T
=
I
100,000 = 0.6283 .
C2
Substituting this value along with that for Avd(0) into m(j) and (j) gives
0.6283
m(j) = - 1 + 2 = -0.0131
and
0.6283
(j) = 2100tan(18) = 0.554 .
The ideal switched capacitor transfer function, HI(j), will be multiplied by a value of
approximately 1/1.0131 = 0.987 and will have an additional phase lag of approximately
0.554.
In general, the phase shift error is more serious than the magnitude error.
P.E. Allen - 2004
Page 9.3-13
Switched Capacitor Integrators - Finite Op Amp GB

The precise analysis of the influence of GB can be found elsewhere . The results of
such an analysis can be summarized in the following table.
Noninverting
Integrator
C2
m() -e-k C1+C2
() 0
1
Inverting Integrator
C2
m() -e-k 1 - C +C cos(T)

1
2
1
C2
() -e-k C +C cos(T)
1
2
1
C2 GB
k1 C1+C2 fc
If T is much less than unity, the expressions in table reduce to

f
m() -2 fc e-(GB/f )
c
K. Martin and A.S. Sedra, Effects of the Op Amp Finite Gain and Bandwidth on the Performance of Switched-Capacitor Filters, IEEE Trans. on
Circuits and Systems, vol. CAS-28, no. 8, August 1981, pp. 822-829.
P.E. Allen - 2004
Page 9.3-14
Switched Capacitor Circuits - kT/C Noise

Switched capacitors generate an
Ron
inherent thermal noise given by
+
+
+
+
kT/C. This noise is verified as
vin
vin
vout
vout
C
C
follows.
(a.)
(b.)
An equivalent circuit for a switched Figure 9.3-11 - (a.) Simple
switched capacitor circuit. (b.) Approximation of (a.).
capacitor:
The noise voltage spectral density of Fig. 9.3-11b is given as
2kTRon
Volt2/Rad./sec.
(1)
eR2on = 4kTRon Volts2/Hz =
The rms noise voltage is found by integrating this spectral density from 0 to to give
vR2on
12d 2kTRon1 kT
2kTRon
= 2+2 = 2 = C Volts(rms)2
1
(2)
where 1 = 1/(RonC). Note that the switch has an effective noise bandwidth of
1
fsw = 4RonC Hz
which is found by dividing Eq. (2) by Eq. (1).
(3)
P.E. Allen - 2004
Page 9.3-15
SUMMARY
The discrete time noninverting integrator transfer function is
o
V out(e j) C1 T/2 -j/2

oo
H (e ) = o j = jTC2 sin(T/2) e
V in( e )
The discrete time inverting integrator transfer function is
j
C1
V out(e j)
T/2
j
ee
H (e ) = e j = - jTC sin(T/2) ej/2
2
V in( e )
In general the integrator transfer function can be expressed as
H(ejT) = (Ideal)x(Magnitude error)x(Phase error)
Note that the cascade of an noninverting integrator with a inverting integrator has no
phase error
A capacitor C and a switch (or switches) has a thermal noise given as kT/C where T is
the clock period
P.E. Allen - 2004
Page 9.4-1
SECTION 9.4 z-DOMAIN MODELS OF TWO-PHASE SWITCHED

CAPACITOR CIRCUITS
Introduction
Objective:
Allow easy analysis of complex switched capacitor circuits
Develop methods suitable for simulation by computer
Will constrain our focus to two-phase, nonoverlapping clocks
General Two-Port Characterization of Switched Capacitor Circuits:
vin(t)
vout(t)
Dependent
Switched
Independent
Unswitched Voltage
Capacitor
Voltage
Capacitor
Source
Circuit
Source
Figure 9.4-1 - Two-port characterization of a general switched capacitor circuit.
Approach:
Four port - allows both phases to be examined
Two-port - simplifies the models but not as general
P.E. Allen - 2004
Page 9.4-2
Independent Voltage Sources

v*(t)
v(t)
Ve(z)
Phase Dependent
Voltage Source
Vo(z)
1
t/T
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

vO(t)
v(t)
z-1/2Vo(z)
Phase Independent
Voltage Source for
the Odd Phase
Vo(z)
1
t/T
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

ve(t)
v(t)
Ve(z)
Phase Independent
Voltage Source for
the Even Phase
z-1/2Ve(z)
2
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5
t/T
P.E. Allen - 2004
Page 9.4-3
Switched Capacitor Four-Port Circuits And Z-Domain Models
+
v1(t)
-
C
2
+
v2(t)
-
Negative SC Transresistance
C
+ 2
v1(t)
1
-
2 +
1 v2(t)
-
Positive SC Transresistance
C
+
v1(t)
-
+
v2(t)
-
Capacitor and Series Switch
+
o
V1
e
V1
+
+
o
V1
-e
V1
+
+
o
V1
-e
V1
+
C(1-z-1)
-Cz-1/2
Cz-1/2
C
Cz-1/2
Parallel Switched Capacitor
-Cz-1/2
-Cz-1/2
+
v2(t)
-
Cz-1/2
+
v1(t)
-
+
o
V1
e
V1
+
Switched Capacitor, Two-Port Circuit Four-Port, z-domain Equivalent Model Simplified, Two-Port z-domain Model
+
o
V2
e
V2
+
+
o
V2
e
V2
+
+
o
V1
-
Cz-1/2
+
e
V2
-
(Circuit connected between

defined voltages)
+
o
V1
-
-Cz-1/2
+
e
V2
-

defined voltages)
+
o
V2
-e
V2
+
C
+
+
e
e
V1
V2
defined voltages)
+
o
V2
-e
V2
+
C(1-z-1)
+
+
e
e
V1
V2
defined voltages) Fig. 9.4-3
K.R. Laker, Equivalent Circuits for Analysis and Synthesis of Switched Capacitor Networks, Bell System Technical Journal, vol. 58, no. 3,
March 1979, pp. 729-769.
P.E. Allen - 2004
Page 9.4-4
Z-Domain Models for Circuits that must be Four-Port
C
+
+
v2(t)
v1(t)
1
Capacitor and
Shunt Switch
C
+
o
V1
-e
V1
+
+
o
V2
e
V2
+
+
o
V1
e
V1
+
+
o
V1
-e
V1
+
+
o
V2
-e
V2
+
+
o
V2
e
V2
+
-Cz-1/2
Cz-1/2
-Cz-1/2
V1
+
-Cz-1/2
+
+
v2(t)
v1(t)
Unswitched
Capacitor
+
o
V1
-
Cz-1/2
Simplified Four-port
z-domain Model
Four-port z-domain Model
-Cz-1/2
Switched Capacitor
Circuit
+
o
V2
-e
V2
+
Fig. 9.4-4
P.E. Allen - 2004
Page 9.4-5
Z-Domain Model for the Ideal Op Amp
+
vi(t)
-
+
vo(t) = Avvi(t)
-
Time domain op amp model.
+
Vio(z)
-
+
Voo(z) = AvVio(z)
-
Vie(z)
+
Voe(z) = AvVie(z)
+
z-domain op amp model

Figure 9.4-5
P.E. Allen - 2004
Page 9.4-6
Cz-1/2
-Cz-1/2
Cz-1/2
Example 9.4-1- Illustration of the Validity of the z-domain Models

Show that the z-domain four-port model for the negative switched capacitor
transresistance circuit of Fig. 9.4-3 is equivalent to the two-port switched capacitor
circuit.
+
+
o
o
Solution
V1
V2
For the two-port switched capacitor circuit, we
observe that during the 1 phase, the capacitor C is
e
e
V2
V
1
charged to v1(t). Let us assume that the time reference
+
+
for this phase is t - T/2 so that the capacitor voltage is
Negative SC Transresistance Model
vC = v1(t - T/2).
During the next phase, 2, the capacitor is inverted and v2 can be expressed as
v2(t) = -vC = -v1(t - T/2).
e
Next, let us sum the currents flowing away from the positive V 2 node of the fourport z-domain model in Fig. 9.4-3. This equation is,
e
-Cz-1/2(V 2 - V 1 ) + Cz-1/2V 2 + CV 2 = 0.
e
This equation can be simplified as

V 2 = -z-1/2V 1
which when translated to the time domain gives
v2(t) = -vC = -v1(t - T/2).
Thus, the four-port z-domain model is equivalent to the time domain.
P.E. Allen - 2004
Page 9.4-7
Z-Domain, Hand-Analysis of Switched Capacitor Circuits

General, time-variant,
switched capacitor circuit.
v1
v2
1
v1
v3
vo
v4
2
1
+
Fig. 9.6-4a
Four-port, model of the

above circuit.
V2(z)
V3(z)
V4(z)
Vo(z)
V1(z)
1
2
2
2
1
V1(z)
e
V2(z)
V4(z)
V3(z)
+
-
Vo(z)
Fig9.4-6b
Simplification of the above

circuit to a two-port, timeinvariant model.
V2(z)
V3(z)
V4(z)
e
1
o
V1(z)
2
2
Vo(z)
2
1
+
Fig. 9.4-7
P.E. Allen - 2004
Page 9.4-8
Example 9.4-2 - z-domain Analysis of the Noninverting SC Integrator

o
Find the z-domain transfer function V oe(z)/V i (z) and

Voo(z)/Voi(z) of the noninverting switched capacitor
integrator using the above methods.
Solution
First redraw Fig. 9.3-4a as shown in Fig. 9.4-8a.
We have added an additional 2 switch to help in
using Fig. 9.4-3. Because this circuit is timeinvariant, we may use the two-port modeling
approach of Fig. 9.4-7. Note that C2 and the
indicated 2 switch are modeled by the bottom row,
right column of Fig 9.4-3. The resulting z-domain
model for Fig. 9.4-8a is shown in Fig. 9.4-8b.
Since z-domain models use admittance, we get
-C1
z-1/2V
o
i (z)
e
C2(1-z-1)V o (z)
=0
Hoe(z)
C1
C2
2
2
vi(t)
vo
2
-
+
-C1z-1/2
(a.)
C2(1-z-1) V e(z)
o
Vo(z)
Vi(z)
z-1/2Vo(z)
(b.)
Figure 9.4-8 - (a.) Modified equivalent circuit
of Fig. 9.3-4a. (b.) Two-port, z-domain model
for Fig. 9.4-8a.
e
o
(V o (z)/V i (z))
C1z-1/2
= C2(1-z-1) .
Hoo(z) is found by using the relationship that V o (z) = z-1/2V o (z) to get
C1z-1
o
o
Hoo(z) = (V o (z)/V i (z)) = C2(1-z-1)
which is equal to z-domain transfer function of the noninverting SC integrator.
P.E. Allen - 2004
Page 9.4-9
Example 9.4-3 - z-domain Analysis of the Inverting Switched Capacitor Integrator

e
Find the z-domain transfer function V o (z)/V i (z) and

o
C1
2
V o (z)/V i (z) of Fig. 9.3-4a using the above methods.

Solution
Fig. 9.4-9a shows the modified equivalent
circuit of Fig. 9.3-4b. The two-port, z-domain
model for Fig. 9.4-9a is shown in Fig. 9.4-9b.
Summing the currents flowing to the inverting node
of the op amp gives
e
C1V i (z)
e
C2(1-z-1)V o (z)
+
=0
which can be rearranged to give
e
Hee(z) =
V o (z)
e
vi(t)
C2
2
vo
2
+
C1
e
Vi(z)
(a.)
C2(1-z-1) V e(z)
o
Vo(z)
z-1/2Vo(z)
(b.)
Figure 9.4-9 - (a.) Modified equivalent circuit of
inverting SC integrator. (b.) Two-port, z-domain
model for Fig. 9.4-9a
-C1
= C (1-z-1) .
2
V i (z)
which is equal to inverting, switched capacitor integrator z-domain transfer function.
o
Heo(z) is found by using the relationship that V o (z) = z-1/2V o (z) to get
o
Heo(z)
V o (z)
e
V i (z)
C1z-1/2
= C (1-z-1) .
2
P.E. Allen - 2004
Page 9.4-10
Example 9.4-4 - z-domain Analysis a Time-Variant Switched Capacitor Circuit

o
Find V o (z) and V o (z) as function of V 1 (z)
C1
1
o
V 2 (z)
and
for the summing, switched capacitor
integrator of Fig. 9.4-10a.
Solution
This circuit is time-variant because C3 is
charged from a different circuit for each phase.
Therefore, we must use a four-port model. The
resulting z-domain model for Fig. 9.4-10a is
shown in Fig. 9.4-10b.
v1(t)
C3
vo
2
-
+
C1
1
1
2
v2(t)
Fig. 9.4-10a - Summing Integrator.
P.E. Allen - 2004
Page 9.4-11

-C3z-1/2
Summing the currents flowing away from the V i (z) node

gives
o
C2V 2 (z) + C3V o (z) - C3z-1/2V o (z) = 0
(1)
e
Summing the currents flowing away from the V i (z) node,

o
o
C2V 2 (z)
o
o
o
+ C3V o (z) - C1z-1V 1 (z) - C3z-1V o (z) = 0 (3)
o
Solving for V o (z) gives,
o
o
C1z-1V 1 (z) C2V 2 (z)
o
V o (z) = C3(1-z-1) - C3(1-z-1)
Multiplying Eq. (1) by z-1/2 and adding it to Eq. (2) gives
o
Vo(z)
Vi(z)
- C3
V1(z)
-C1z-1/2V 1 (z) - C3z-1/2V o (z) + C3V o (z) = 0 (2)

Multiplying (2) by z-1/2 and adding it to (1) gives
-C1z-1/2
V2(z)
C2
e
Vi(z)
C3
Voe(z)
-C3z-1/2
Fig. 9.4-10b - Four-port, z-domain
model for Fig. 9.4-10a.
C2z-1/2V 2 (z) - C1z-1V 1 (z) - C3z-1V o (z) + C3V o (z) = 0

e
Solving for V o (z) gives,

o
e
V o (z)
C1z-1/2V 1 (z) C2z-1/2V 2 (z)

= C3(1-z-1) - C3(1-z-1) .
P.E. Allen - 2004
Page 9.4-12
Frequency Domain Simulation of SC Circuits Using Spice Storistors

A storistor is a two-terminal element that has a current flow that occurs at some time
after the voltage is applied across the storistor.
I(z)
I(z)
z-domain:
V1(z)
V2(z)
Cz-1/2
I(z) = Cz-1/2 [V1(z) - V2(z)]
Fig. 9.4-11a
i(t)
Time-domain:
+
v1(t)
-
T
T
i(t) = C v t - 2 - v2t - 2

1
Cv3(t)
i(t)
+
v2(t)
+v3(t) -
Delay of T/2
Rin =
T
2
+
Fig. 9.4-11b
SPICE Primitives:
2
1
CV4
LosslessTransmission Line
V1-V2
TD = T/2, Z0 = R
Fig. 9.4-11c
B.D. Nelin, Analysis of Switched-Capacitor Networks Using General-Purpose Circuit Simulation Programs, IEEE Trans. on Circuits and Systems, pp. 43-48, vol. CAS-30,
No. 1, Jan. 1983.
P.E. Allen - 2004
Page 9.4-13
C2z-1/2
-C2z-1/2
-C2z-1/2
C2z-1/2
C1
C1z-1/2
-C1z-1/2
C1z-1/2
C1
Example 9.4-5 - SPICE Simulation of A Noninverting SC Integrator

Use SPICE to obtain a frequency domain simulation of the noninverting, switched
capacitor integrator. Assume that the clock frequency is 100kHz and design the ratio of
C1 and C2 to give an integration frequency of 10kHz.
Solution
The design of C1/C2 is accomplished from the ideal integrator transfer function.
C1
2fI
=
T
=
I
C2
fc = 0.6283
AssumeC2 = 1F C1 = 0.6283F.
C2
1
3
5
Next we replace the switched
+
+o
106V3
o
Vi
Vo
capacitor C1 and the unswitched
0
0
0
capacitor of integrator by the z-e
-e
Vo
Vi
domain model of the second row of
+
+
106V4
Fig. 9.4-3 and the first row of Fig.
2
4
6
C2
9.4-4 to obtain Fig. 9.4-12. Note Figure 9.4-12 - z-domain model for noninverting switched capacitor integrator.
that in addition we used Fig. 9.4-5
for the op amp and assumed that the op amp had a differential voltage gain of 106. Also,
the unswitched Cs are conductances.
As the op amp gain becomes large, the important components are indicated by the
darker shading.
P.E. Allen - 2004
Page 9.4-14

The SPICE input file to perform a frequency domain simulation of Fig. 9.4-12 is shown
below.
G36 6 3 36 0 1
X45NC2 4 5 45 DELAY
G45 5 4 45 0 1
EODD 6 0 4 0 -1E6
EVEN 5 0 3 0 -1E6
********************
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5U
RDO 3 0 1K
.ENDS DELAY
********************
.AC LIN 99 1K 99K
.PRINT AC V(6) VP(6) V(5) VP(5)
.PROBE
.END
VIN 1 0 DC 0 AC 1
R10C1 1 0 1.592
X10PC1 1 0 10 DELAY
G10 1 0 10 0 0.6283
X14NC1 1 4 14 DELAY
G14 4 1 14 0 0.6283
R40C1 4 0 1.592
X40PC1 4 0 40 DELAY
G40 4 0 40 0 0.6283
X43PC2 4 3 43 DELAY
G43 4 3 43 0 1
R35 3 5 1.0
X56PC2 5 6 56 DELAY
G56 5 6 56 0 1
R46 4 6 1.0
X36NC2 3 6 36 DELAY
P.E. Allen - 2004
Page 9.4-15

Simulation Results:
5
200
150
Magnitude
4
3
Both H
oe
and H
oo
2
1
100
50
0
oo
Phase of H (jw)
-50
oe
Phase of H (jw)
-100
-150
20
40
60
Frequency (kHz)
(a.)
80
100
-200
20
40
60
Frequency (kHz)
(b.)
80
100
Comments:
This approach is applicable to all switched capacitor circuits that use two-phase,
nonoverlapping clocks.
If the op amp gain is large, some simplification is possible in the four-port z-domain
models.
The primary advantage of this approach is that it is not necessary to learn a new
simulator.
P.E. Allen - 2004
Page 9.4-16
Simulation of Switched Capacitor Circuits Using SWITCAP

Introduction
Signal
SCN's or Mixed
SWITCAP is a general simulation
Outputs
Generators
SC/D Networks
program for analyzing linear switched
capacitor networks (SCNs) and mixed
switched capacitor/digital (SC/D)
Clocks
networks.
General Setup of SWITCAP
Major Features
1.) Switching Intervals - An arbitrary number of switching intervals per switching period
is allowed. The durations of the switching intervals may be unequal and arbitrary.
2.) Network Elements ON-OFF switches, linear capacitors, linear VCVSs, and independent voltage sources.
The independent voltage source waveforms may be continuous or piecewise-constant.
The switches in the linear SCNs are controlled by periodic clock waveforms only.
A mixed SC/D network may contain comparators, logic gates such as AND, OR, NOT,
NAND, NOR, XOR, and XNOR. The ON-OFF switches in the SC/D network may be
controlled not only by periodic waveforms but also by nonperiodic waveforms from
the output of comparators and logic gates.
K. Suyama, Users Manual for SWITCAP2, Version 1.1, Dept. of Elect. Engr., Columbia University, New York, NY 10027, Feb. 1992.
P.E. Allen - 2004
Page 9.4-17
SWITCAP - Major Features, Continued

3.) Time-Domain Analyses of Linear SCNs and Mixed SC/D Networks a.) Linear SCNs only: The transient response to any prescribed input waveform for
t 0 after computing the steady-state values for a set of dc inputs for t < 0.
b.) Both types of networks: Transient response without computing the steady-state
values as initial conditions. A set of the initial condition of analog and digital
nodes at t = 0- may be specified by the user.
4.) Various Waveforms for Time Domain Analyses - Pulse, pulse train, cosine,
exponential, exponential cosine, piecewise linear, and dc sources.
5.) Frequency Domain Analyses of Linear SCNs - A single-frequency sinusoidal input
can produce a steady-state output containing many frequency components. SWITCAP
can determine all of these output frequency components for both continuous and
piecewise-constant input waveforms. z-domain quantities can also be computed.
Frequency-domain group delay and sensitivity analyses are also provided.
6.) Built-In Sampling Functions - Both the input and output waveforms may be sampled
and held at arbitrary instants to produce the desired waveforms for time- and frequencydomain analyses of linear SCNs except for sensitivity analysis. The output waveforms
may also be sampled with a train of impulse functions for z-domain analyses.
P.E. Allen - 2004
Page 9.4-18
SWITCAP - Major Features, Continued

7.) Subcircuits - Subcircuits, including analog and/or digital elements, may be defined
with symbolic values for capacitances, VCVS gains, clocks, and other parameters.
Hierarchical use of subcircuits is allowed.
8.) Finite Resistances, Op Amp Poles, and Switch Parasitics - Finite resistance is
modeled with SCNs operating at clock frequencies higher than the normal clock. These
resistors permit the modeling of op amp poles. Capacitors are added to the switch
model to represent clock feedthrough.
P.E. Allen - 2004
Page 9.4-19
SWITCAP - Mixed SC/D Networks

Structure of mixed SC/D networks as defined in SWITCAP2.
Timing
Logic
Threshold
+
...
...
+
-
+
v
-
Av
SCN - Function Generation

P.E. Allen - 2004
Page 9.4-20
SWITCAP - Resistors
RQ
RQ
Ceq
R= T
4Ceq
RQ
RQ
RQ
t
RQ
The clock, RQ, for the resistor is run at a frequency, much higher than the system clock in
order to make the resistor model still approximate a resistor at frequencies near the
system clock.
P.E. Allen - 2004
Page 9.4-21
SWITCAP - MOS Switches

MOS Transistor Switch Model:
High Clock Voltage
G
MQ
MQ
MQ MQ
MQ
Cgs
RON
MQ
S
S
Cgd
Cbs
Cbd
Frequency
Higher than
MQ clock
More information:
SWITCAP Distribution Center
Columbia University
411 Low Memorial Library
New York, NY 10027
suyama@elab.columbia.edu
P.E. Allen - 2004
Page 9.4-22
SUMMARY
Can replace various switch-capacitor combinations with a z-domain model
The z-domain model consists of:
- Positive and negative conductances
- Delayed conductances (storistor)
- Controlled sources
- Independent sources
These models permit SPICE simulation of switched capacitor circuits
The type of clock circuits considered here are limited to two-phase clocks
P.E. Allen - 2004
Page 9.5-1
SECTION 9.5 FIRST-ORDER SWITCHED CAPACITOR CIRCUITS

Introduction
Objective:
Examine first-order SC circuits
Illustrate various design methods of SC circuits
Approach:
Low-pass: Design using oversampled assumption and direct z-domain design
High-pass: Design using oversampled assumption and direct z-domain design
All-pass: Design using oversampled assumption and direct z-domain design
P.E. Allen - 2004
Page 9.5-2
General, First-Order Transfer Functions

A general first-order transfer function in the s-domain:
sa1 a0
H(s) = s + b0
a1 = 0 Low pass, a0 = 0 High Pass, a0 0 and a1 0 All pass
Note that the zero can be in the RHP or LHP.
A general first-order transfer function in the z-domain:
zA1 A0 A1 A0z-1
H(z) = z - B0 = 1 - B z-1
0
P.E. Allen - 2004
Page 9.5-3
Noninverting, First-Order, Low Pass Circuit

2C1
2 1
2
1
1C1
1
- C1
+
2
C
1 2 1 1
C1
vo(t)
vo(t)
2
vi(t)
vo(t)
1
vi(t)
1C1
2
1
(a.)
(b.)
Figure 9.5-1 - (a.) Noninverting, first-order low pass circuit. (b.) Equivalent circuit of Fig. 9.5-1a.
Transfer function:
Summing currents flowing toward the inverting
op amp terminal gives
e
2C1V o (z)
- 1C1z-1/2V i (z) + C1(1-z-1)V o (z) = 0

o
Vo(z)
C12
-C11z-1/2 C1(1-z-1) V e(z)
o
Vo(z)
Solving for V o (z)/V i (z) gives

o
Vi(z)
-1
z
e
+
1
o
z-1/2Vo(z)
V o (z)
1z-1
1+2
=
=
o
-1
z-1
Figure 9.5-2 - z-domain model of Fig. 9.5-1b.
V i (z) 1 + 2 - z
1 - 1+2
Equating the above to H(z) of the previous page gives the design equations as
1 = A0/B0
and
2 = (1-B0)/B0
P.E. Allen - 2004
Page 9.5-4
Inverting, First-Order, Low Pass Circuit

An inverting low pass circuit can be obtained by reversing the phases of the leftmost two
switches in Fig. 9.5-1a.
2C1
2 1
2
1
1C1
2
vo(t)
- C1
C1
vo(t)
vo(t)
2
vi(t)
2
2C1
1
1
2
vi(t)
1C1
1
1
Inverting, first-order low pass circuit.
Equivalent circuit.
It can be shown that,

- 1
- 1
1+2
= 1 + 2 - z-1 =
z-1
V i (z)
1 - 1+
2
Equating to H(z) gives the design equations for the inverting low pass circuit as
1-B
-A1
0
1 = B0
and
2 = B0
e
V o (z)
e
P.E. Allen - 2004
Page 9.5-5
Example 9.5-1 - Design of a Switched Capacitor First-Order Circuit

Design a switched capacitor first-order circuit that has a low frequency gain of +10
and a -3dB frequency of 1kHz. Give the value of the capacitor ratios 1 and 2. Use a
clock frequency of 100kHz.
Solution
Assume that the clock frequency, fc, is much larger than the -3dB frequency. In this
example, the clock frequency is 100 times larger so this assumption should be valid.
Based on this assumption, we approximate z-1 as
z-1 = e-sT 1- sT +
(1)
Rewrite the z-domain transfer function as
o
1z-1
= 2 + 1- z-1
o
V (z)
V o (z)
(2)
Next, we note from Eq. (1) that 1-z-1 sT. Furthermore, if sT<<1, then z-1 1.
Making these substitutions in Eq. (2), we get
o
V o (s)
1
1/ 2
2 + sT = 1 + s(T/2)
(3)
V
Equating Eq. (3) to the specifications gives 1 = 102 and 2 = -3dB/fc
2 = 6283/100,000 = 0.0628 and 1 = 0.6283
o
i (s)
P.E. Allen - 2004
Page 9.5-6
First-Order, High Pass Circuit

2C
2 1
1
2C
2 1
1
1C
1C
vo(t)
Transfer function:
Summing currents at the
inverting input node of the op
amp gives
e
vo(t)
2
- C
vi(t)
- C
vi(t)
(b.)
(a.)
Figure 9.5-3 - (a.) Switched-capacitor, high pass circuit. (b.) Version of Fig. 9.5-3a
that constrains the charging of C1 to the 2 phase.
1(1-z-1)V o (z) + 2V o (z) + (1-z-1)V i (z) = 0

(1)
Solving for the Hee(z) transfer function gives
1
e
V o (z) -1(1-z-1) 2+1 (1-z-1)
(2)
Hee(z) = e = +1-z-1 =
1
2
-1
V i (z)
1 - +1 z
2
Equating Eq. (2) to H(z) gives,
1-B0
-A1
1 = B0
and
2 = B0
2
1(1-z-1)
(1-z-1)
Voe(z)
Vo(z)
Vi(z)
z-1/2Vo(z)
Figure 9.5-4 - z-domain model for Fig. 9.5-3.
P.E. Allen - 2004
Page 9.5-7
First-Order, Allpass Circuit

2
3C
2C
1
1
3C
2C
1
1
vo(t)
1
vi(t)
1C
2
1
2
vo(t)
C
vi(t)
C
2 1 1
Transfer function:
(a.)
(b.)
Summing the currents
Figure 9.5-5 - (a.) High or low frequency boost circuit. (b.) Modification of (a.) to simplify
flowing into the
the z-domain modeling
inverting input of the
3(1-z-1)
2
op amp gives
o
-1z-1/2 (1-z-1) V e(z)
-1z-1/2Voi (z)+3(1-z-1)Vei (z)+2Veo(z)+(1-z-1)Veo(z) = 0 Vie(z)
Vo(z)
o
Since Voi(z) = z-1/2Vei(z), then the above becomes
o
Vi(z)
e
+
z-1/2Vo(z)
Veo(z) 2+1-z-1 = 1z-1Vei(z) - 3(1-z-1)Vei(z)
Solving for Hee(z) gives
Figure 9.5-6 - z-domain model for Fig. 9.5-5b.
1+3
1-B0
1z-1-3(1-z-1) -3 1- 3 z-1
A1+A0
- A0
=
and
=
Hee(z) = +(1-z-1) = 2+1
1
2 B0
3
B0
B0
z-1
2
1-2+1
P.E. Allen - 2004
Page 9.5-8
Example 9.5-2 - Design of a Switched Capacitor Bass Boost Circuit

Find the values of the capacitor ratios1, 2,
20
and 3 using a 100kHz clock for Fig. 9.5-5
dB
that will realize the asymptotic frequency
response shown in Fig. 9.5-7.
0
10Hz
100Hz
1kHz
10kHz
Solution
Frequency
Since the specification for the example is
Figure 9.5-7 - Bass boost response for Ex. 9.5-2.
given in the continuous time frequency
domain, let us use the approximation that z-1 1 and 1-z-1 sT, where T is the period of
the clock frequency. Therefore, the allpass transfer function can be written as
-sT3 + 1
1 sT3/1 - 1
Hee(s) sT + 2 = - 2 sT/2 + 1
From Fig. 9.5-7, we see that the desired response has a dc gain of 10, a right-half
plane zero at 2 kHz and a pole at -200 Hz. Thus, we see that the following
relationships must hold.
1
1
2
=
10
,
=
2000
,
and
2
T 3
T = 200
From these relationships we get the desired values as
2000
200
1 = fc , 2 = fc , and 3 = 1
P.E. Allen - 2004
Page 9.5-9
Practical Implementations of the First-Order Circuits

1
2
1C
1
2
vi(t)
C1
1
1C
-+
+-
2
+
2
1
1C
2C
-+
+-
vo(t) vi(t)
vo(t)
2C
1C
2C
1
2
+
vo(t)
2C
1C
2
1
1C
1
2
3C
2 2C
1
2
2
1
vo(t) vi(t)
-
3C
-+
+-
vo(t)
-
vo(t)
2 2C
1
1
(c.)
(a.)
(b.)
Figure 9.5-8 - Differential implementations of (a.) Fig. 9.5-1, (b.) Fig. 9.5-3, and (c.) Fig. 9.5-5.
2
1
Comments:
Differential operation reduces clock feedthrough, common mode noise sources and
enhances the signal swing.
Differential operation requires op amps or OTAs with differential outputs which in turn
requires a means of stabilizing the output common mode voltage.
P.E. Allen - 2004
Page 9.5-10
SUMMARY
Examined first-order SC circuits (lowpass, highpass, allpass)
Illustrated design by assuming the clock frequency is higher than the signal frequency
(s-domain design)
Illustrated direct design by equating coefficients between the desired and design in the
z-domain (requires the specifications in the z-domain)
P.E. Allen - 2004
Page 9.6-1
SECTION 9.6 SECOND-ORDER SWITCHED CAPACITOR CIRCUITS

Why Second-Order Circuits?
They are fundamental blocks in switched capacitor filters.
Switched Capacitor Filter Design Approaches
Cascade design
Vin
SecondOrder
Circuit
Stage 1
SecondOrder
Circuit
Stage 2
(a.)
SecondOrder
Circuit
Stage n
Vout
FirstOrder
Circuit
Stage 1
SecondSecondVout
Order
Order
Circuit
Circuit
Stage 2
Stage n
(b.)
Figure 9.6-1 - (a.) Cascade design when n is even. (b.) Cascade designwhen n is odd.
Vin
Ladder design
Also uses first- and second-order circuits
There are also other applications of first- and second-order circuits:
Oscillators
Converters
P.E. Allen - 2004
Page 9.6-2
Biquad Transfer Function

A biquad has two poles and two zeros.
Poles are complex and always in the LHP.
The zeros may or may not be complex and may be in the LHP or the RHP.
Transfer function:
(s-z1)(s-z2)
Vout(s) -(K2s2+ K1s + K0)
=
K
Ha(s) = Vin(s) =
(s-p )(s-p )
o
1
2
s2 + Q s+ o2
j
o
2Q
Low pass: zeros at

Bandstop: zeros at jo
High pass: zeros at 0
Allpass: Poles and zeros are complex
Bandpass: One zero at 0 and the other at
conjugates
P.E. Allen - 2004
Page 9.6-3
Low-Q, Switched Capacitor Biquad

Development of the Biquad:
Rewrite Ha(s) as:
os
s2Vout(s) + Q Vout(s) + o2Vout(s) = -(K2s2 + K1s + K0)Vin(s)
Dividing through by s 2 and solving for Vout(s), gives
o
-1
1
Vout(s) = s (K1 + K2s)Vin(s) + Q Vout(s) + s (K0Vin(s) +o2Vout(s))
If we define the voltage V1(s) as
-1 K0
V1(s) = s o Vin(s) + oVout(s) , then Vout(s) can be expressed as
-1
o
Vout(s) = s (K1 + K2s) Vin(s) + Q Vout(s) - oV1(s)
Synthesizing the voltages V1(s)
Vin(s) K2
CA=1
and Vout(s), gives
Vout(s) 1/o
Vin(s) o/K0
V1(s)
CB=1
Vin(s) 1/K1
Vout(s) Q/o
Vout(s)
V1(s) -1/o
(a.)
(b.)
Figure 9.6-2 - (a.) Realization of V1(s). (b.) Realization of Vout(s).
P.E. Allen - 2004
Page 9.6-4
Low-Q, Switched Capacitor Biquad - Continued

Replace the continuous time integrators with switched capacitor integrators to get:
3C2
Vin(z)
2C1
Vout(z)
C1
2
1
e
Vin(z)
2
1
C2 V e (z)
out
4C2
Vin(z)
1C1
2
1
V1(z)
5C2
V1(s)
1
2
6C2
Vout(z)
2
1
(a.)
(b.)
Figure 9.6-3 - (a.) Switched capacitor realization of Fig. 9.6-2a. (b.) Switched
capacitor realization of Fig. 9.6-2b.
From these circuits we can write that:

1 e
2
e
e
V 1 (z) = - 1-z-1 Vin(z) - 1-z-1 Vout(z)
and
4 e
5z-1 e
6
e
e
e
V out(z) = -3 Vin(z) - 1-z-1 Vin(z) + 1-z-1 V 1(z) - 1-z-1 Vout(z) .
o
Note that we multiplied the V 1 (z) input of Fig. 9.6-3b by z-1/2 to convert it to V 1 (z).
P.E. Allen - 2004
Page 9.6-5

Connecting the two circuits
of Fig. 9.6-3 together gives
e
1C 1
the desired, low-Q, biquad
C1
Vin(z)
realization.
2
2
1
2C 1
e
V1(z)
5C 2
1
2
6C 2
C2
1
e
Vout(z)
+
If we assume that T<<1,
4C 2
e
1
1
then 1-z-1 sT and V1(z)
3C 2
e
andVout(z) can be
Figure 9.6-4 - Low Q, switched capacitor, biquad realization.
approximated as
1 e
2 e
2 e
-1 1 e
e
V 1 (s) - sT Vin(s) - sT Vout(s) = s T Vin(s) + T Vout(s)
and
5 e
6 e
-1 4
e
e
V out(s) s ( T + s3)Vin(s) - T V 1(s) + T Vout(s) .
These equations can be combined to give the transfer function, Hee(s) as follows.
s4 15
-3s2 + T + T2
Hee(s)
s6 25
s2 + T + T2
P.E. Allen - 2004
Page 9.6-6
s4 15
-3s2 + T + T2 -(K s2+ K s + K )
2
1
0
Equating Hee(s) to Ha(s) gives
o
s6 25 =
s2 + Q s+ o2
s2 + T + T2
oT
K0T
which gives,
1 = o , 2 = |5| = oT, 3 = K2, 4 = K1T, and 6 = Q .
Largest capacitor ratio:
If Q > 1 and oT << 1, the largest capacitor ratio is 6.
For this reason, the low-Q, switched capacitor biquad is restricted to Q < 5.
Sum of capacitance:
To find this value, normalize all of the capacitors connected or switched into the
inverting terminal of each op amp by the smallest capacitor, minC. The sum of the
normalized capacitors associated with each op amp will be the sum of the capacitance
connected to that op amp. Thus,
1 n
C = min i
i =1
where there are n capacitors connected to the op amp inverting terminal, including the
integrating capacitor.
P.E. Allen - 2004
Page 9.6-7
Example 9.6-1- Design Of A Switched Capacitor, Low-Q, Biquad

Assume that the specifications of a biquad are fo = 1kHz, Q = 2, K0 = K2 = 0, and K1 =
2fo/Q (a bandpass filter). The clock frequency is 100kHz. Design the capacitor ratios of
Fig. 9.6-4 and determine the maximum capacitor ratio and the total capacitance assuming
that C1 and C2 have unit values.
Solution
From the previous slide we have
oT
K0T
1 = o , 2 = |5| = oT, 3 = K2, 4 = K1T, and 6 = Q .
Setting K0 = K2 = 0, and K1 = 2fo/Q and letting fo = 1kHz, Q = 2 gives
1 = 3 = 0, 2 = 5 = 0.0628, and 4 = 6 = 0.0314.
The largest capacitor ratio is 4 or 6 and is 1/31.83.
capacitors connected to the input op amp = 1/0.0628 + 1 = 16.916.
capacitors connected to the second op amp = 0.0628/0.0314 + 1/0.0314 + 2 = 35.85.
Therefore, the total biquad capacitance is 52.76 units of capacitance.
(Note that this number will decrease as the clock frequency becomes closer to the signal
frequencies.)
P.E. Allen - 2004
Page 9.6-8
Z-Domain Characterization of the Low-Q, Biquad

Combining the following two equations,
1 e
2
e
e
V 1 (z) = - 1-z-1 Vin(z) - 1-z-1 Vout(z)
and
4 e
6
5z-1 e
e
e
e
V out(z) = -3 Vin(z) - 1-z-1 Vin(z) + 1-z-1 V 1(z) - 1-z-1 Vout(z) .
gives,
e
(3 + 4)z2 + (15 - 4 - 23)z + 3
V out(z)
ee
= H (z) = - (1 + )z2 + ( - - 2)z + 1
e
6
2 5
6
V in(z)
A general z-domain specification for a biquad can be written as
a2z2 + a1z + a0
H(z) = - b z2 + b z + 1
2
1
Equating coefficients gives
3 = a0, 4 = a2-a0, 15 = a2+a1+a0, 6 = b2-1, and 25 = b2+b1+1
Because there are 5 equations and 6 unknowns, an additional relationship can be
introduced. One approach would be to select 5 = 1 and solve for the remaining
capacitor ratios. Alternately, one could let 2 = 5 which makes the integrator frequency
of both integrators in the feedback loop equal.
P.E. Allen - 2004
Page 9.6-9
Voltage Scaling
It is desirable to keep the amplitudes of the output voltages of the two op amps
approximately equal over the frequency range of interest. This can be done by voltage
scaling.
If the voltage at the output node of an op amp in a switched capacitor circuit is to
be scaled by a factor of k, then all switched and unswitched capacitors connected to that
output node must be scaled by a factor of 1/k.
For example,
1C1
C1
v1
2C2
C2
The charge associated with v1 is:

Q(v1) = C1v1 + 2C2v1
Suppose we wish to scale the value of v1 by k1 so that v1 = k1v1. Therefore,
Q(v1) = C1v1 + 2C2v1 = C1k1v1 + 2C2k1v1
But, Q(v1) = Q(v1) so that C1 = C1/k1 and C2 = C2/k1.
This scaling is based on keeping the total charge associated with a node constant.
The choice above of 2 = 5 results in a near-optimally scaled dynamic range realization.
P.E. Allen - 2004
Page 9.6-10
High-Q, Switched Capacitor Biquad

Desired: A biquad capable of realizing higher values of Q without suffering large
element spreads.
Development of such a biquad:
Reformulate the equations for V1(s) and Vout(s) as follows,
1
Vout(s) = - s K2sVin - oV1(s)
and
1 K0 K1
s
V1(s) = - s o + o s Vin(s) + o + Q Vout(s)
Synthesizing these equations:

CA=1
Vout(s) 1/o
CB=1
Vin(s) K2
Vout(s) 1/Q
Vin(s) K1/o
V1(s)
V1(s) -1/o
Vout(s)
Vin(s) o/K0
Realization of Vout(s).
Realization of V1(s).
P.E. Allen - 2004
Page 9.6-11
High-Q, Switched Capacitor Biquad - Continued

Replace the continuous time integrators with switched capacitor integrators to get:
e
Vout
(z)
4C1
Vin(z)
3C1
2C1
Vout(z)
C1
2
1
e
Vin(z)
1C1
2
1
V1(z)
e
6C2
5C2 2
Vin(z)
V1(s)
1
2
C2 V e (z)
out
+
1
(a.)
(b.)
Figure 9.6-6 - (a.) Switched capacitor realization of Fig. 9.6-5a. (b.) Switched
capacitor realization of Fig. 9.6-5b.
From these circuits we can write that:

1 e
2
e
e
e
e
V 1 (z) = - 1-z-1 Vin(z) - 1-z-1 Vout(z) - 3Vin(z) - 4Vout(z)
and
5z-1 e
e
e
V out(z) = -6 Vin(z) + 1-z-1 V 1(z) .
o
Note that we multiplied the V 1 (z) input of Fig. 9.6-6b by z-1/2 to convert it to V 1 (z).
P.E. Allen - 2004
Page 9.6-12

Connecting the two circuits
of Fig. 9.6-6 together gives
3C1
the desired, high-Q biquad
realization.
e
C
C
If we assume that T<<1,
e
then 1-z-1 sT and V1(z)
2
1
4C1
1
2
C2
2
Vout(z)
e
andVout(z)
5C2
1 Ve (z)
1
1 1
Vin(z)
2C1
6C2
can be
Figure 9.6-7 - High Q, switched capacitor, biquad realization.
approximated as
e
1 1
1 2
e
e
V 1 (s) - s T + s3V in(s) - s T + s4V out(s)
and
5 e
-1
e
e
V out(s) s (s6)Vin(s) - T V 1(s) .
These equations can be combined to give the transfer function, Hee(s) as follows.
s35 15
-6s2 + T + T2
Hee(s)
s45 25
s2 + T + T2
P.E. Allen - 2004
Page 9.6-13

Equating Hee(s) to Ha(s) gives
s35 15
2
-6s + T + T2 -(K s + K s + K )
2 2
1
0
o
s45 25 =
s2 + Q s+ o2
s2 + T + T2
which gives,
K0T
K1
1
1 = o , 2 = |5| = oT, 3 = o, 4 =Q, and 6 = K2 .
Largest capacitor ratio:
If Q > 1 and oT << 1, the largest capacitor ratio is 2 (5) or 4 depending on the
values of Q and oT.
P.E. Allen - 2004
Page 9.6-14
Example 9.6-2 - Design of a Switched Capacitor, High-Q, Biquad

Assume that the specifications of a biquad arefo = 1kHz, Q = 10, K0 = K2 = 0, and K1
= 2fo/Q (a bandpass filter). The clock frequency is 100kHz. Design the capacitor ratios
of the high-Q biquad of Fig. 9.6-4 and determine the maximum capacitor ratio and the
total capacitance assuming that C1 and C2 have unit values.
Solution
From the previous slide we have,
K0T
K1
1
1 = o , 2 = |5| = oT, 3 = o, 4 =Q, and 6 = K2 .
Using fo = 1kHz, Q = 10 and setting K0 = K2 = 0, and K1 = 2fo/Q (a bandpass filter) gives
1 = 6 = 0, 2 = 5 = 0.0628, and 3 =4 = 0.1.
The largest capacitor ratio is 2 or 5 and is 1/15.92.
capacitors connected to the input op amp = 1/0.0628 + 2(0.1/0.0628) + 1 = 20.103.
capacitors connected to the second op amp = 1/0.0628 + 1 = 16.916.
Therefore, the total biquad capacitance is 36.02 units of capacitance.
P.E. Allen - 2004
Page 9.6-15
Z-Domain Characterization of the High-Q, Biquad

Combining the following two equations,
1 e
2
e
e
e
e
V 1 (z) = - 1-z-1 Vin(z) - 1-z-1 Vout(z) - 3Vin(z) - 4Vout(z)
and
5z-1 e
e
e
V out(z) = -6 Vin(z) + 1-z-1 V 1(z)
gives,
e
6z2 + (35 - 15 - 26)z + (6 - 35)
V out(z)
ee
= H (z) = - z2 + ( + - 2)z + (1 - )
e
4 5
2 5
4 5
V in(z)
A general z-domain specification for a biquad can be written as
a2z2 + a1z + a0
(a2/b2)z2 + (a1/b2)z + (a0/b2)
H(z) = - b z2 + b z + 1 = z2 + (b1/b2)z + (b0/b2)
2
1
Equating coefficients gives
a2
a2-a0
a2+a1+a0
b1+1
1
6 = b2, 35 = b2 , 15 = b2
, 45 = 1- b2 and 25 = 1 + 2
Because there are 5 equations and 6 unknowns, an additional relationship can be
introduced. One approach would be to select 5 = 1 and solve for the remaining
capacitor ratios. Alternately, one could let 2 = 5 which makes the integrator frequency
of both integrators in the feedback loop equal.
P.E. Allen - 2004
Page 9.6-16
Fleischer-Laker, Switched Capacitor Biquad

E
K
C
2
2
e
Vin(z)
2
V1(s)
Vout(z)
+
I
H
1
J
2
1
2
L
2
Figure 9.6-8 - Fleischer-Laker, switched capacitor biquad.
e
V out(z)
(DJ^ - AH^)z-2 - [D( I^ + J^) - AG^]z - D I^
=
e
-2 -1
V in(z) (DB - AE)z [2DB - A(C + E) + DF]z + D(B +F)
e
^) + FH^ - E( I^+J^) - CJ^]z-1 - [ I^(C+E) - G
^(F+B)]
V 1(z) (EJ^ - BH^)z-2+[B(G^+H
=
e
(DB - AE)z-2 - [2DB - A(C + E) + DF]z-1 + D(B +F)
V in(z)
G^ = G+L,
where
H^ = H+L ,
I^ = I+K
and
J^ = J+L
P.E. Allen - 2004
Page 9.6-17
Z-Domain Model Of The Fleischer-Laker Biquad

E(1-z-1)
C
K(1-z-1)
D(1-z-1) V e(z) -Az-1
1
G
e
Vin(z)
-Hz-1
B(1-z-1)
e
(z)
Vout
+
I
-Jz-1
L(1-z-1)
Figure 9.6-9 - z-domain equivalent circuit for the Fleischer-Laker biquad of Fig. 9.6-8.
Type 1E Biquad (F = 0)
e
V out
z-2(JD - HA) + z-1(AG - DJ - DI) + DI
e = -2
-1
V in z (DB - AE) + z (AC + AE - 2BD) + BD
and
e
V 1 z-2(EJ - HB) + z-1(GB + HB - IE - CJ - EJ) + (IC + IE - GB)

e =
z-2(DB - AE) + z-1(AC + AE - 2BD) + BD
V in
P.E. Allen - 2004
Page 9.6-18
Z-Domain Model of the Fleischer-Laker Biquad - Continued

E(1-z-1)
C
K(1-z-1)
D(1-z-1) V e(z) -Az-1
1
G
e
Vin(z)
-Hz-1
B(1-z-1)
e
Vout
(z)
+
I
-Jz-1
L(1-z-1)
Figure 9.6-9 - z-domain equivalent circuit for the Fleischer-Laker biquad of Fig. 9.6-8.
Type 1F Biquad (E = 0)
e
z-2(JD - HA) + z-1(AG - DJ - DI) + DI

V out
=
e
-2
-1
V in z DB + z (AC - 2BD - DF) + (BD + DF)
and
e
V 1 -z-2HB + z-1(GB + HB + HF - CJ) + (IC + GF - GB)

e =
z-2DB + z-1(AC - 2BD - DF) + (BD + DF)
V in
P.E. Allen - 2004
Page 9.6-19
Example 9.6-3 - Design of a Switched Capacitor, Fleischer-Laker Biquad

Use the Fleischer-Laker biquad to implement the following z-domain transfer
function which has poles in the z-domain at r = 0.98 and = 6.2.
0.003z-2 + 0.006z-1 + 0.003
H(z) = 0.9604z-2 - 1.9485z-1 + 1
Solution
Let us begin by selecting a Type 1E Fleischer-Laker biquad. Equating the numerator
of Eq. (1) with the numerator of H(z) gives
DI = 0.003
AG-DJ-DI = 0.006 AG-DJ = 0.009
DJ-HA = 0.003
If we arbitrarily choose H = 0, we get
DI = 0.003
JD = 0.003
AG = 0.012
Picking D = A = 1 gives I = 0.003, J = 0.003 and G = 0.012. Equating the denominator
terms of Eq. (1) with the denominator of H(z), gives
BD = 1
BD-AE = 0.9604 AE = 0.0396
AC+AE-2BD = -1.9485 AC+AE = 0.0515 AC = 0.0119
Because we have selected D = A = 1, we get B = 1, E = 0.0396, and C = 0.0119. If any
capacitor value was negative, the procedure would have to be changed by making
different choices or choosing a different realization such as Type 1F.
P.E. Allen - 2004
Page 9.6-20

Since each of the alphabetic symbols is a capacitor, the largest capacitor ratio
will be D or A divided by I or J which gives 333. The large capacitor ratio is being
caused by the term BD = 1. If we switch to the Type 1F, the term BD = 0.9604 will cause
large capacitor ratios. This example is a case where both the E and F capacitors are
needed to maintain a smaller capacitor ratio.
P.E. Allen - 2004
Page 9.6-21
SUMMARY
The second-order switched capacitor circuit is a very versatile circuit
The second-order switched capacitor circuit will be very useful in filter design
Low-Q biquad is good for Qs up to about 5 before the elements spreads become large
Design methods:
- Assume that fc>>fsig and using continuous time specifications and design
- Direct design equate the z-domain transfer function to a z-domain specification
and solve for the capacitor ratios
P.E. Allen - 2004
Page 9.7-1
SECTION 9.7 SWITCHED CAPACITOR FILTERS

Continuous Time Filter Theory
Todays switched capacitor filters are based on continuous time filters.
Consequently, it is expedient to briefly review the subject of continuous time filters.
Filter
Switched
Continuous
Specifications
Time Filter
Capacitor Filter
Ideal Filter:
Magnitude
1.0
Passband
0.0
0
Stopband
fcutoff =
fPassband
Frequency
Phase
0 0
Frequency
Slope =
-Time delay
This specification cannot be achieve by realizable filters because:

An instantaneous transition from a gain of 1 to 0 is not possible.
A band of zero gain is not possible.
Therefore, we develop filter approximations which closely approximate the ideal filter
but are realizable.
ECE 6414 - Analog Integrated Systems Design
P.E. Allen - 2002
Page 9.7-2
Characterization of Filters
A low pass filter magnitude response.
Tn(jn)
T(j)
1
T(jPB)/T(j0)
T(j0)
T(jPB)
T(jSB)
0
0
T(jSB)/T(j0)
0
0
PB SB
1 SB/PB=n
(b.)
(a.)
Figure 9.7-1 - (a.) Low pass filter. (b.) Normalized, low pass filter.
Three basic properties of filters.

1.) Passband ripple = |T(j0) - T(jPB)|.
2.) Stopband frequency = SB.
3.) Stopband gain/attenuation = T(jSB).
For a normalized filter the basic properties are:
1.) Passband ripple = T(jPB)/T(j0) = T(jPB) if T(j0) = 1.
2.) Stopband frequency (called the transition frequency) = n = SB/PB.
3.) Stopband gain = T(jSB)/T(j0) = T(jSB) if T(j0) = 1.
P.E. Allen - 2002
Page 9.7-3
Filter Specifications in Terms of Bode Plots (dB)

Tn(jn) dB
An(jn) dB
1
log10(n)
T(jPB)
A(jSB)
T(jSB)
A(jPB)
0
0
log10(n)
1
n
(b.)
(a.)
Figure 9.7-2 - (a.) Low pass filter of Fig. 9.7-1 as a Bode plot. (b.) Low pass filter of
Fig. 9.7-2a shown in terms of attenuation (A(j) = 1/T(j)).
Therefore,
Passband ripple = T(jPB) dB
Stopband gain = T(jSB) dB or Stopband attenuation = A(jPB)
Transition frequency is still = n = SB/PB
P.E. Allen - 2002
Page 9.7-4
Butterworth Filter Approximation

This approximation is maximally flat
in the passband.
(j ) =
0.8
A
0.6
|T LPn (j n)|
0.4
Butterworth Magnitude
Approximation:
LPn
N=5
N=4
N=6
1
1+
0.2
N=3
N=2
N=8
2N
N=10
1 + 2 n
0
0
0.5
1
1.5
2
where N is the order of the
Normalized Frequency, n
approximation and is defined in
the above plot.
The magnitude of the Butterworth filter approximation at SB is given as
j SB
1
T
= |T
(j
)|
=
T
=
LPn
LPn
n
SB
2N
PB
1 + 2 n
This equation in terms of dB is useful for finding N given the filter specifications.
2.5
2N
20 log10(TSB) = TSB (dB) = -10 log101 + 2 n
P.E. Allen - 2002
Page 9.7-5
Example 9.7-1 - Determining the Order of A Butterworth Filter Approximation

Assume that a normalized, low-pass filter is specified as TPB = -3dB, TSB = -20 dB,
and n = 1.5. Find the smallest integer value of N of the Butterworth filter approximation
which will satisfy this specification.
Solution
TPB = -3dB corresponds to TPB = 0.707 which implies that = 1. Thus, substituting
= 1 and n = 1.5 into the equation at the bottom of the previous slide gives
TSB (dB) = - 10 log101 + 1.52N
Substituting values of N into this equation gives,
TSB = -7.83 dB for N = 2
-10.93 dB for N = 3
-14.25 dB for N = 4
-17.68 dB for N = 5
-21.16 dB for N = 6.
Thus, N must be 6 or greater to meet the filter specification.
P.E. Allen - 2002
Page 9.7-6
Poles and Quadratic Factors of Butterworth Functions

Table 9.7-1 - Pole locations and quadratic factors (sn2 + a1sn + 1) of normalized, low pass
Butterworth functions for = 1. Odd orders have a product (sn+1).
N
2
3
4
5
6
7
8
9
10
Poles
-0.70711 j0.70711
-0.50000 j0.86603
-0.38268 j0.92388
-0.92388 j0.38268
-0.30902 j0.95106
-0.80902 j0.58779
-0.25882 j0.96593
-0.96593 j0.25882
-0.70711 j0.70711
-0.22252 j0.97493
-0.90097 j0.43388
-0.62349 j0.78183
-0.19509 j0.98079
-0.83147 j0.55557
-0.55557 j0.83147
-0.98079 j0.19509
-0.17365 j0.98481
-0.76604 j0.64279
-0.50000 j0.86603
-0.93969 j0.34202
-0.15643 j0.98769
-0.89101 j0.45399
-0.45399 j0.89101
-0.98769 j0.15643
-0.70711 j0.70711
a1 coefficient
1.41421
1.00000
0.76536
1.84776
0.61804
1.61804
0.51764 1.93186
1.41421
0.44505 1.80194
1.24698
0.39018 1.66294
1.11114 1.96158
0.34730 1.53208
1.00000 1.87938
0.31286 1.78202
0.90798 1.97538
1.41421
P.E. Allen - 2002
Page 9.7-7
Example 9.7-2 - Finding the Butterworth Roots and Polynomial for a given N
Find the roots for a Butterworth approximation with =1 for N = 5.
Solution
For N = 5, the following first- and second-order products are obtained from Table
9.7-1
1
1
1
2
TLPn(sn) = T1(sn)T2(sn)T3(sn) = sn+1 2

sn+0.6180sn+1sn+1.6180sn+1
Illustration of the individual magnitude contributions of each product of TLPn(sn).
2
T 2 (jn)
Magnitude
1.5
TLPn(jn )
1
T1(jn )
0.5
T3 (jn)
0
0.5
1
1.5
2
2.5
P.E. Allen - 2002
Chebyshev Filter Approximation

The magnitude response of the
Chebyshev filter approximation for
= 0.5088.
Page 9.7-8
1
A
0.8
1
1+2
N=2
0.6
TLPn(jn )
0.4
N=3
N=4
The magnitude of the normalized,

Chebyshev, low-pass, filter
approximation can be expressed as
TLPn(jn) =
1
1 + 2 cos2[Ncos-1(n)] ,
n 1
and
0.2
0
N=5
0.5
1
1.5
2
2.5
1
(jn) = 1 + 2 cosh2[Ncosh-1( )] , n > 1
n
where N is the order of the filter approximation and is defined as
1
|TLPn(PB)| = |TLPn(1)| = TPB = 1+2 .
N is determined from 20 log10(TSB) = TSB (dB) = -10log10{1 + 2cosh2[Ncosh-1(n)]}
T
LPn
P.E. Allen - 2002
Page 9.7-9
Example 9.7-3 - Determining the Order of A Chebyshev Filter Approximation

Repeat Ex. 9.7-1 for the Chebyshev filter approximation.
Solution
In Ex. 9.7-2, = 1 which means the ripple width is 3 dB or TPB = 0.707. Now we
substitute = 1 into
20 log10(TSB) = TSB (dB) = -10log10{1 + 2cosh2[Ncosh-1(n)]}
and find the value of N which satisfies TSB = - 20dB.
For N = 2, TSB = - 11.22 dB.
For N =3, TSB = -19.14 dB.
For N = 4, TSB = -27.43 dB.
Thus N = 4 must be used although N = 3 almost satisfies the specifications. This result
compares with N = 6 for the Butterworth approximation.
P.E. Allen - 2002
Page 9.7-10
Poles and Quadratic Factors of Chebyshev Functions

Table 9.7-2 - Pole locations and quadratic factors (a0 + a1sn + sn2) of normalized, low pass
Chebyshev functions for = 0.5088 (1dB).
N
2
3
4
5
Normalized Pole
Locations
-0.54887 j0.89513
-0.24709 j0.96600
-0.49417
-0.13954 j0.98338
-0.33687 j0.40733
-0.08946 j0.99011
-0.23421 j0.61192
-0.28949
-0.06218 j0.99341
-0.16988 j0.72723
-0.23206 j0.26618
-0.04571 j0.99528
-0.12807 j0.79816
-0.18507 j0.44294
-0.20541
a0
a1
1.10251
0.99420
1.09773
0.49417
0.98650
0.27940
0.98831
0.42930
0.27907
0.67374
0.17892
0.46841
0.99073
0.55772
0.12471
0.99268
0.65346
0.23045
0.12436
0.33976
0.46413
0.09142
0.25615
0.37014
P.E. Allen - 2002
Page 9.7-11
Example 9.7-4 - Finding the Chebyshev Roots for a given N

Find the roots for the Chebyshev approximation with =1 for N = 5.
Solution
For N = 5, we get the following quadratic factors which give the transfer function as
0.2895
TLPn(sn) = T1(sn)T2(sn)T3(sn) = sn+0.2895
0.9883
0.4293
2
sn+0.1789sn+0.9883sn+0.4684sn+0.4293

P.E. Allen - 2002

Page 9.7-12
Other Approximations
Thomson Filters - Maximally flat magnitude and linear phase1
Elliptic Filters - Ripple both in the passband and stopband, the smallest transition region
of all filters.2
An excellent collection of filter approximations and data is found in A.I. Zverev,
Handbook of Filter Synthesis, John Wiley & Sons, Inc., New York, 1967.
W.E. Thomson, Delay Networks Having Maximally Flat Frequency Characteristics, Proc. IEEE, part 3, vol. 96, Nov. 1949, pp. 487-490.
W. Cauer, Synthesis of Linear Communication Networks, McGraw-Hill Book Co., New York, NY, 1958.
P.E. Allen - 2002
Page 9.7-13
GENERAL APPROACH FOR CONTINUOUS AND SC FILTER DESIGN

Approach
Low-Pass,
Normalized
Filter with a
passband of
1 rps and an
impedance
of 1 ohm.
Normalized
LP Filter
Root
Locations
Frequency
Transform the
Roots to HP,
BP, or BS
Cascade of
First- and/or
Second-Order
Stages
Normalized
Low-Pass
RLC Ladder
Realization
Frequency
Transform the
L's and C's to
HP, BP, or BS
First-Order
Replacement
of Ladder
Components
Denormalize
the Filter
Realization
All designs start with a normalized, low pass filter with a passband of 1 radian/second and
an impedance of 1 that will satisfy the filter specification.
1.) Cascade approach - starts with the normalized, low pass filter root locations.
2.) Ladder approach - starts with the normalized, low pass, RLC ladder realizations.

P.E. Allen - 2002

Page 9.7-14
A Design Procedure for the Low Pass, SC Filters Using the Cascade Approach
1.) From TPB, TSB, and n (or APB, ASB, and n) determine the required order of the
filter approximation, N.
2.) From tables similar to Table 9.7-1 and 9.7-2 find the normalized poles of the
approximation.
3.) Group the complex-conjugate poles into second-order realizations. For odd-order
realizations there will be one first-order term.
4.) Realize each of the terms using the first- and second-order blocks of the previous
lectures.
5.) Cascade the realizations in the order from input to output of the lowest-Q stage first
(first-order stages generally should be first).
More information can be found elsewhere1,2,3,4.
K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw Hill, New York, 1994.
P.E. Allen and E. Sanchez-Sinencio, Switched Capacitor Circuits, Van Nostrand Reinhold, New York, 1984.
R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons, New York, 1987.
3
4
L.P. Huelsman and P.E. Allen, Introduction to the Theory and Design of Active Filters, McGraw Hill Book Company, New York, 1980.
P.E. Allen - 2002
Page 9.7-15
Example 9.7-5 - Fifth-order, Low Pass, SC Filter using the Cascade Approach
Design a cascade, switched capacitor realization for a Chebyshev filter approximation
to the filter specifications of TPB = -1dB, TSB = -25dB, fPB = 1kHz and fSB = 1.5kHz. Give
a schematic and component value for the realization. Also simulate the realization and
compare to an ideal realization. Use a clock frequency of 20kHz.
Solution
First we see that n = 1.5. Next, recall that when TPB = -1dB that this corresponds to =
0.5088. We find that N = 5 satisfies the specifications (TSB = -29.9dB). Using the results
of previous lecture, we may write TLPn(sn) as
0.2895
0.9883
0.4293
2
TLPn(sn) = sn+0.2895 2
(1)
sn+0.1789sn+0.9883sn+0.4684sn+0.4293
Next, we design each of the three stages
1
individually.
21C11
11
11
2
Vin(ej)
V2(ej)
Stage 1 - First-order Stage
1
2
- C11
2
1
Let us select the first-order stage shown. We will
+
assume that fc is much greater than fBP (i.e. 100) and use
transfer function shown below to accomplish the design.
Stage 1
11/21
(2)
T1(s) 1 + s(T/21)
P.E. Allen - 2002

Page 9.7-16

Note that we have used the second subscript 1 to denote the first stage. Before we
can use this equation we must normalize the sT factor. This normalization is
accomplished by
s
sT = PB (PBT) = snTn .
(3)
Therefore, Eq. (2) can be written as
11/21
11/Tn
(4)
T1(sn) 1 + sn(Tn/21) = sn + 21/Tn
where 11 = C11/C and 21 = C21/C.
Equating Eq. (4) to the first term in TLPn(sn) gives the design of first-order stage as
0.2895PB 0.28952000
21 = 11 = 0.2895Tn =
=
= 0.0909
fc
20,000
The sum of capacitances for the first stage is
1
First-stage capacitance = 2 + 0.0909 = 13 units of capacitance
P.E. Allen - 2002
Page 9.7-17

1
Stage 2 2nd-order, high-Q Stage
22C12
42C12
2
The next product of TLPn(sn) is
0.9883
12C12
52C22
V3(ej)
V2(ej)
2
2
1
2
2
s n + 0.1789sn + 0.9883
- C12
- C22
2
1
1
2
1
+
+
T(0) n
(5)
= 2 n
Stage 2
2
sn + Q sn + n
where T(0) = 1, n = 0.9941 and Q = (0.9941/0.1789) = 5.56. Therefore, select the lowpass version of the high-Q biquad. First, apply the normalization of Eq. (3) to get
sn3252 1252
-62s n2 + Tn
+
T n2
.
(6)
T2(sn)
sn4252 2252
2
s n + Tn
+
T n2
To get a low pass realization, select 32 = 62 = 0 to get
-(1252/T n2)
(7)
T2(sn)
sn4252 2252 .
2
+
s n + Tn
T n2
P.E. Allen - 2002

Page 9.7-18

Equating Eq. (7) to the middle term of TLPn(sn) gives
0.9883PB2 0.988342
2
1252 = 2252 = 0.9883Tn =
=
= 0.09754
fc2
400
and
0.1789PB 0.17892
4252 = 0.1789Tn =
=
= 0.05620
fc
20
Choose a12 = a22 = 52 to get optimum voltage scaling. Thus we get, 12 = 22 = 52 =
0.3123 and 42 = 0.05620/0.3123 = 0.1800. The second-stage capacitance is
3(0.3123)
2
Second-stage capacitance = 1 + 0.1800 + 0.1800 = 17.316 units of capacitance
Stage 3 - Second-order, Low-Q Stage
The last product of TLPn(sn) is
1
0.4293
21C13 C
C
63
23
j
13
13
53
23
2
V3(e )
2
Vout(ej)
sn + 0.4684sn + 0.4293
2
1
2
2
- C13
- C23
1
1
2
1
T(0) n2
+
+
= 2
(8)
2
s n + (n/Q)sn + n
Stage 3
where we see that T(0) = 1, n = 0.6552 and Q = (0.6552/0.4684) = 1.3988. Therefore,
select the low pass version of the low-Q biquad. Apply the normalization of Eq. (3) to get
P.E. Allen - 2002
Page 9.7-19
sn43 1353
-33s n2 + Tn +
2
Tn
T3(sn)
.
(9)
sn63 2353
2
s n + Tn +
T n2
To get a low pass realization, select 33 = 43 = 0 to get
- (1353/T n2)
(10)
T3(sn)
sn63 2353 .
2
s n + Tn +
T n2
Equating Eq. (10) to the last term of TLPn(sn) gives
0.4293PB2 0.429342
2
1353 = 2353 = 0.4293T n =
=
= 0.04184
fc2
400
and
63 = 0.4684Tn = (0.4684PB/fc) = (0.46842/20) = 0.1472
Choose a13 = a23 = 53 to get optimum voltage scaling. Thus , 13 = 23 = 53 = 0.2058
and 63 = 0.1472. The third-stage capacitance is
3rd-stage capacitance = 1+(3(0.2058)/0.1472)+(2/0.1472) =18.78 units of capacitance
The total capacitance of this design is 13 + 17.32 + 18.78 = 49.10 units of capacitance.
P.E. Allen - 2002
Page 9.7-20

Final design with stage 3 second to maximize the dynamic range.
Stage 1
Vin(ej)
2
2
21C11
11C11
C11
Stage 3
2
2
1
23C13
13C13
1
C13
63C23
53C23
1
2
2
Stage 2
22C12
12C12
1
42C12
52C22
2
1
C23
C12
Vout(ej)
2
2
C22
Figure 9.7-7 - Fifth-order, Chebyshev, low pass, switched capacitor filter

of Example 9.7-5.
P.E. Allen - 2002
Page 9.7-21

Simulated Frequency Response:
0
200
Stage 1 Output
-20
Stage 3 Output
-30
-40
Stage 2 Output
(Filter Output)
-50
150
Phase (Degrees)
Magnitude (dB)
-10
Stage 2 Phase Shift

(Filter Output)
100
50
Stage 3 Phase Shift
0
-50
-100
-60
-150
-70
-200
500
1000
1500 2000 2500 3000 3500

Frequency (Hz)
Figure 9.7-8a - Simulated magnitude response of Ex. 9.7-5
Stage 1 Phase Shift

0
500
1000
1500 2000 2500 3000 3500

Frequency (Hz)
Figure 9.7-8b - Simulated phase response of Ex. 9.7-5
Comments:
There appears to be a sinx/x effect on the magnitude which causes the passband
specification to not be satisfied. This can be avoided by prewarping the specifications
before designing the filter.
Stopband specifications met
None of the outputs of the biquads exceeds 0 dB (Need to check internal biquad nodes)
P.E. Allen - 2002
Page 9.7-22

SPICE Input File:
******** 08/29/97 13:17:44 *********

*******PSpice 5.2 (Jul 1992) ********
*SPICE FILE FOR EXAMPLE 9.7-5
*EXAMPLE 9-7-5: nodes 5 is the output
*of 1st stage, node 13 : second stage (in
*the figure it is second while in design it *is
third, low Q stage), and node 21 is the
*final output of the *filter.
**** CIRCUIT DESCRIPTION ****
VIN
1 0 DC 0 AC 1
*.PARAM CNC=1 CNC_1=1 CPC_1=1

XNC1 1 2 3 4 NC1
XUSCP1 3 4 5 6 USCP
XPC1 5 6 3 4 PC1
XAMP1 3 4 5 6 AMP
XPC2 5 6 7 8 PC2
XUSCP2 7 8 9 10 USCP
XAMP2 7 8 9 10 AMP
XNC3 9 10 11 12 NC3
XAMP3 11 12 13 14 AMP
XUSCP3 11 12 13 14 USCP
XPC4 13 14 11 12 PC4
XPC5 13 14 7 8 PC2
XPC6 13 14 15 16 PC6
XAMP4 15 16 17 18 AMP
XUSCP4 15 16 17 18 USCP
XNC7 17 18 19 20 NC7
XAMP5 19 20 21 22 AMP
XUSCP5 19 20 21 22 USCP
XUSCP6 21 22 15 16 USCP1
XPC8 21 22 15 16 PC6
SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=25US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 11.0011
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.0909
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.0909
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.0909
RNC2 4 0 11.0011
.ENDS NC1
.SUBCKT NC3 1 2 3 4
RNC1 1 0 4.8581
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.2058
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.2058
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.2058
RNC2 4 0 4.8581
Ends NC3
P.E. Allen - 2002
Page 9.7-23

Spice Input FileContinued
.SUBCKT NC7 1 2 3 4
RNC1 1 0 3.2018
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.3123
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.3123
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.3123
RNC2 4 0 3.2018
.ENDS NC7
.SUBCKT PC1 1 2 3 4
RPC1 2 4 11.0011
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 4.8581
.ENDS PC2
.SUBCKT PC4 1 2 3 4
RPC1 2 4 6.7980
.ENDS PC4
.SUBCKT PC6 1 2 3 4
RPC1 2 4 3.2018
.ENDS PC6
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT USCP1 1 2 3 4
R1 1 3 5.5586
R2 2 4 5.5586
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 0.1799
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 .1799
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 .1799
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 .1799
.ENDS USCP1
.SUBCKT AMP 1 2 3 4
EODD 3 0 1 0 1E6
EVEN 4 0 2 0 1E6
.ENDS AMP
.AC LIN 100 10 3K
.PRINT AC V(5) VP(5) V(13)
VP(13) V(21) VP(21)
.PROBE
.END
P.E. Allen - 2002
Page 9.7-24

Spice Input FileContinued
.SUBCKT NC7 1 2 3 4
RNC1 1 0 3.2018
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.3123
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.3123
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.3123
RNC2 4 0 3.2018
.ENDS NC
.SUBCKT PC1 1 2 3 4
RPC1 2 4 11.0011
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 4.8581
.ENDS PC2
.SUBCKT PC4 1 2 3 4
RPC1 2 4 6.7980
.ENDS PC4
.SUBCKT PC6 1 2 3 4
RPC1 2 4 3.2018
.ENDS PC6
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT USCP1 1 2 3 4
R1 1 3 5.5586
R2 2 4 5.5586
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 0.1799
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 .1799
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 .1799
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 .1799
.ENDS USCP1
.SUBCKT AMP 1 2 3 4
EODD 3 0 1 0 1E6
EVEN 4 0 2 0 1E6
.ENDS AMP
.AC LIN 100 10 3K
.PRINT AC V(5) VP(5) V(13)
VP(13) V(21) VP(21)
.PROBE
.END
P.E. Allen - 2002
Page 9.7-25

Switcap2 Input File (The exact same results were obtained as for SPICE)
TITLE: EXAMPLE 9-7-5
S6
S7
S8
S9
S10
CL12
CL22
CL42
C12
CL52
C22
E1
E2
END;
OPTIONS;
NOLIST;
GRID;
END;
TIMING;
PERIOD 50E-6;
CLOCK CLK 1 (0 25/50);
END;
SUBCKT (1 100) STG1;
S1
(1 2)
CLK;
S2
(2 0)
#CLK;
S3
(3 4)
#CLK;
S4
(3 0)
CLK;
S5
(5 100)
#CLK;
S6
(5 0)
CLK;
CL11 (2 3)
0.0909;
CL21 (3 5)
0.0909;
E1
(100 0 0 4)1E6;
END;
(6 0)
#CLK;
(7 0)
CLK;
(7 8)
#CLK;
(300 9)
#CLK;
(9 0)
#CLK;
(2 3)
0.3123;
(3 9)
0.3123;
(4 300)
0.1799;
(4 5)
1;
(6 7)
0.3123;
(8 300)
1;
(5 0 0 4) 1E6;
(300 0 0 8)1E6
CL53
C23
E1
E2
END;
CIRCUIT;
X1
(1 100)
STG1;
X2
(100 200) STG3;
X3
(200 300) STG2;
V1
(2 0);
END;
ANALYZE SSS;
INFREQ 1 3000 LIN 150;
SET V1 AC 1.0 0.0;
PRINT vdb(100) vp(100);
PLOT vdb(300);
END;

S1
(100 2)
#CLK;
S2
(2 0)
CLK;
S3
(3 0)
CLK;
S4
(3 4)
#CLK;
S5
(6 5)
CLK;
S6
(6 0)
#CLK;
S7
(7 0)
CLK;
S8
(7 8)
#CLK;
S9
(200 9)
#CLK;
S10
(9 0)
#CLK;
CL13 (2 3)
0.2058;
CL23 (3 9)
0.2058;
CL63 (9 7)
0.1471;
C13
(4 5)
1;

S1
(200 2)
#CLK;
S2
(2 0)
CLK;
S3
(3 0)
CLK;
S4
(3 4)
#CLK;
S5
(6 5)
CLK;
(6 7)
0.2058;
(8 200)
1;
(5 0 0 4) 1E6;
(200 0 0 8)1E6
END;
P.E. Allen - 2002
Page 9.7-26
Using the Cascade Approach for Other Types of Filters

Other types of filters are developed based on the low pass approach.
TLP(j)
1
TPB
TBP(j)
1
TPB
One possible
filter realization
TSB
0
0
THP(j)
Transition
Region
1
TPB
1
TPB
Upper Transition Region
TSB
A
D
0
0 SB1 PB1 PB2 SB2
(c.)
(rps)
Transition
Region
(rps)
SB PB
TBS(j)
One possible
filter realization
TSB
(rps) 0
0
PB SB
(a.)
Lower
Transition
Region
One possible
filter realization
(b.)
One possible
Lower
filter realization
Transition
A Region
C
Upper TransiTSB
B
D
tion Region
0
(rps)
0 PB1 SB1 SB2 PB2
(d.)
Practical magnitude responses of (a.) low pass, (b.) high pass, (c.) bandpass, and (d.)
bandstop filter.
We will use transformations from the normalized, low pass filter to the normalized
high pass, bandpass or bandstop to achieve other types of filters.
P.E. Allen - 2002
Page 9.7-27
High Pass, SC Filters Using the Cascade Approach

Normalized, low pass to normalized high pass transformation:
1
sln = shn
where shn is the normalized, high-pass frequency variable.
A general form of the normalized, low-pass transfer function is
p1lnp2lnp3lnpNln
TLPn(sln) = (sln+p1ln)(sln+p2ln)(sln+p3ln)(sln+pNln)
where pkln is the kth normalized, low-pass pole.
Applying the normalized, low-pass to high-pass transformation toTLPn(sln) gives
N
p1lnp2lnp3lnpNln
shn
THPn(shn) = 1
1
1
1
=
1
1
1
1
+p
+p
+p
+p
s
+
s
+
s
+
s
+
1lnshn 2lnshn 3ln shn Nln
shn
hn p1ln hn p2ln hn p3ln hn pNln
N
shn
= shn+p1hnshn+p2hnshn+p3hnshn+pNhn
where pkhn is the kth normalized high-pass pole.

Use high pass switched capacitor circuits to achieve the implementation.
PB
1
n is defined for the high pass normalized filter as: n = hn = SB
P.E. Allen - 2002

Page 9.7-28
Example 9.7-6 - Design of a Butterworth, High-Pass Filter

Design a high-pass filter having a -3dB ripple bandwidth above 1 kHz and a gain of
less than -35 dB below 500 Hz using the Butterworth approximation. Use a clock
frequency of 100kHz.
Solution
From the specification, we know that TPB = -3 dB and TSB = -35 dB. Also, n = 2
(hn = 0.5). = 1 because TPB = -3 dB. Therefore, find that N = 6 will give TSB = -36.12
dB which is the lowest, integer value of N which meets the specifications.
Next, the normalized, low-pass poles are found from Table 9.7-1 as
p1ln, p6ln = -0.2588 j 0.9659
p2ln, p5ln = -0.7071 j 0.7071
and
p3ln, p4ln = -0.9659 j 0.2588
Inverting the normalized, low-pass poles gives the normalized, high-pass poles which are
p1hn, p6hn = -0.2588 +- j 0.9659
p2hn, p5hn = -0.7071 +- j 0.7071
and
p3hn, p4hn = -0.9659 +- j 0.2588 .
We note the inversion of the Butterworth poles simply changes the sign of the imaginary
part of the pole.
P.E. Allen - 2002
Page 9.7-29

The next step is to group the poles in second-order products, since there are no firstorder products. This result gives the following normalized, high-pass transfer function.
THPn(shn) = T1(shn)T2(shn)T3(shn)
2
2
2
shn
shn
shn
= (shn+p1hn)(shn+p6hn)(shn+p2hn)(shn+p5hn)(shn+p3hn)(shn+p4hn)
2
2
2
shn
shn
shn
.
= 2
2
2
shn+0.5176shn+1shn+1.4141shn+1shn+1.9318shn+1
Now we are in a position to do the stage-by-stage design. We see that the Qs of

each stage are Q1 = 1/0.5176 = 1.932, Q2 = 1/1.414 = 0.707, and Q3 = 1/1.9318 = 0.5176.
Therefore, we will choose the low-Q biquad to implement the realization of this example.
The low-Q biquad design equations are:
1 = (K0Tn/on) , 2 = |5| = onTn, 3 = K2, 4 = K1Tn, and 6 = (onTn/Q) .
For the high pass,
onTn
K0=K1=0 and K2=1, so that 1=4=0 and 2=|5| = onTn, 3 = K2 and 6 = Q .
Stage 1
21=51=(PB/fc)=(2103/105)=0.06283, 31 = 1,
and 61 = (PB/Qfc) = (0.06283/1.932) = 0.03252
P.E. Allen - 2002
63C23
1
e 33C23
Vin(z)
53C23
1
2 C23
2
1
C13
23C13
V3(z)
Stage 2
e
V2(z)
62C22
52C22
C12
21C12
2
1
Stage 1
61C21
C22 2 32C22
2
1
Stage 3

Stage 2
PB 2103
22 = 52 = fc = 105 = 0.06283,
32 = 1, and
PB 0.06283
62 = Qfc = 0.707 = 0.08884
Stage 3
PB 2103
23 = 53 = fc = 105 = 0.06283,
33 = 1, and
PB 0.06283
63 = Qfc = 0.5176 = 0.1214
Realization
Lowest Q stages are first in the cascade
realization.
capacitances = 104.62 units of capacitance
Page 9.7-30
51C21
31C21 2 C21
2
1
C11
21C11
2
e
Vout(z)
2
1
P.E. Allen - 2002
Page 9.7-31
Bandpass, SC Filters Using the Cascade Approach

1.) Define the passband and stopband as
and
SW = SB2 - SB1
BW = PB2 - PB1
where PB2 (PB1) is the larger (smaller) passband of the bandpass filter. SB2 (SB1) is
the larger (smaller) stopband frequency.
2.) Geometrically centered bandpass filters have the following relationship:
r = PB1PB2 = SB2SB1
3.) Define a normalized low-pass to unnormalized bandpass transformation as
2r
1 sb2 + 2r
1
sln = B W sb = B W sb + sb .
4.) A normalized low-pass to normalized bandpass transformation is achieved by
dividing the bandpass variable, sb, by the geometric center frequency, r, to get
1
r sb
1 r
sb
where sbn = r .
sln = B Wr + (sb/r) = B Wsbn + sbn
5.) Multiply by BW/r and define yet a further normalization as
B W
sl
1
BW
where b = r .
sln' = r sln = bsln = bPB = sbn + sbn
6.) Solve for sbn in terms of sln' from the following quadratic equation.
2
sbn - sln' sbn + 1 = 0 sbn = sln' /2 sln' /22 - 1 .
P.E. Allen - 2002
Page 9.7-32
Illustration of the Above Approach

TLPn(j 'ln )
TLPn(jln )
1
0
-1 0
Bandpass
Normalization
b s ln = BW s ln s 'ln
r
1
(a.)
0
-b 0 b
r ln (rps)
PB
TBPn(jbn )
-r
BW
0
0
(d.)
'ln (rps)
Normalized
2
s 'ln
low-pass to s 'ln
-1
normalized 2
2
bandpass
transformation
s bn
TPBn (jb )
BW
1
(b.)
Bandpass
Denormalization
sb b s bn = BW sbn
r
b (rps)
1
b
b
-1
0
0
(c.)
bn (rps)
Figure 9.7-10 - Illustration of the development of a bandpass filter from a low-pass filter.
(a.) Ideal normalized, low-pass filter. (b.) Normalization of (a.) for bandpass
transformation. (c.) Application of low-pass to bandpass transformation. (d.)
Denormalized bandpass filter.
P.E. Allen - 2002
Page 9.7-33
Bandpass Design Procedure for the Cascade Approach

1.) The ratio of the stop bandwidth to the pass bandwidth is defined as
S W SB2 - SB1
n = B W = PB2 - PB1.
2.) From TPB, TSB, and n, find the order N or the filter.
3.) Find the normalized, low-pass poles, p .
kln
4.) The normalized bandpass poles can be found from the normalized, low pass poles, pkln
using

jbn
pkln
pkln 2
'
p
jln
jbn
pkbn = 2
2 -1 .
For each pole of the low-pass filter, two poles
result for the bandpass filter.
Figure 9.7-11 - Illustration of how the
normalized, low-pass, complex conjugate
poles are transformed into two normalized,
bandpass, complex conjugate poles.

pkbn
p'jln
'ln
p'kln
= p'jln*
Low-pass Poles
Normalized by PB r
BW
bn
p*jbn
p*kbn
Normalized
Bandpass Poles
P.E. Allen - 2002

Page 9.7-34
Bandpass Design Procedure for the Cascade Approach - Continued

5.) Group the poles and zeros into second-order products having the following form
Kk sbn
Kk sbn
Tk(sbn) = (s + p )(s + p* ) = (sbn+kbn+jkbn)(sbn+kbn-jkbn)
bn
kbn bn
jbn
kon
sbn
T
(
)
k
kon
Kk sbn
Qk
= s2bn+(2kbn)sbn+(2bn+2kbn) =
kon
s2bn + Qk sbn + 2kon
where j and k corresponds to the jth and kth low-pass poles which are a complex
conjugate pair, Kk is a gain constant, and
2bn+2kbn
kon =
and
Qk = 2bn
.
6.) Realize each second-order product with a bandpass switched capacitor biquad and
cascade in the order of increasing Q.
2
kbn
+2kbn
P.E. Allen - 2002
Page 9.7-35
Example 9.7-7 - Design of a Cascade Bandpass Switched Capacitor Filter

Design a bandpass, Butterworth filter having a -3dB ripple bandwidth of 200 Hz
geometrically centered at 1 kHz and a stopband of 1 kHz with an attenuation of 40 dB or
greater, geometrically centered at 1 kHz. The gain at 1 kHz is to be unity. Use a clock
frequency of 100kHz.
Solution
From the specifications, we know that TPB = -3 dB and TSB = -40 dB. Also, n =
1000/200 = 5. = 1 because TPB = -3 dB. Therefore, we find that N = 3 will give TSB = 41.94 dB which is the lowest, integer value of N which meets the specifications.
Next, we evaluate the normalized, low-pass poles from Table 9.7-1 as
p1ln, p3ln = -0.5000 j0.8660 and p2ln = -1.0000 .
Normalizing these poles by the bandpass normalization of b = 200/1000 = 0.2 gives
p1ln, p3ln= -0.1000 j 0.1732
and p2ln= -0.2000 .
Each one of the pklnwill contribute a second-order term. The normalized bandpass
poles are found by using sbn = sln' /2 sln' /22 - 1 which results in 6 poles given as,
For p1ln= -0.1000 + j0.1732 p1bn, p2bn = -0.0543 + j1.0891, -0.0457 - j0.9159.
For p2ln= -0.1000 - j0.1732 p3bn, p4bn = -0.0457 + j0.9159, -0.543 - j 1.0891.
p5bn, p6bn = -0.1000 j 0.9950.
For p3ln= -0.2000
P.E. Allen - 2002
Page 9.7-36

The normalized low-pass pole locations, pkln, the bandpass normalized, low-pass pole
' , and the normalized bandpass poles, pkbn are shown below. Note that the
locations, pkln
bandpass poles have very high pole-Qs if BW < r.
jln
j'ln
j1
p1ln
p1ln
p1bn jbn
p5bn
j1
j0.8660
j1
p3bn
3 zeros
at j
p'1ln
p2ln
-1
ln
-0.5000
p2ln
p'2ln
-1
'ln
p'3ln
bn
-1
p 2bn
p3ln
-j0.8660
-j1
(a.)
p3ln
-j1
(b.)
p6bn
p4bn
-j1
(c.)
Pole locations for Ex. 9.7-8. (a.) Normalized low-pass poles. (b.) Bandpass
normalized low-pass poles. (c.) Normalized bandpass poles.
P.E. Allen - 2002
Page 9.7-37

Grouping the complex conjugate bandpass poles gives the following second-order
transfer functions.
K1sbn
K1sbn
T1(sbn) = (s+p1bn)(s+p4bn) = (sbn+0.0543+j1.0891)(sbn+0.0543-j1.0891)
1.0904
s
10.0410 bn
=
1.0904
s2bn+10.0410sbn+1.09042
K2sbn
K2sbn
0.9170
s
10.0333 bn
.
=
0.9170
2
2
sbn+10.0333sbn+0.9159
and
K3sbn
K3sbn
1.0000
s
5.0000 bn
.
=
1.0000
s2bn+5.0000sbn+1.00002
P.E. Allen - 2002

Page 9.7-38

Now we can begin the stage-by-stage design. Note that the Qs of the stages are Q1
= 10.0410, Q2 = 10.0333, and Q3 = 5.0000. Therefore, use the high-Q biquad whose
design equations are:
K0Tn
K1
1
1 = on , 2 = |5| = onTn , 3 = on, 4 =Q, and 6 = K2 .
For the bandpass realization K0 = K2 = 0 and K1 = on/Q, so that the design equations
simplify to
K1 on/Q 1
onr
1
1 = 0, 2 = |5| = on,Tn = fc , 3 = on = on = Q , 4 =Q, and 6 = 0
Stage 1
o1 1.09042x103
11=61=0, 21=|51|= fc =
=0.06815, 31=0.09959, and 41 =0.09959
105
Stage 2
o2 0.91592x103
12=62=0, 22=|52|= fc =
=0.05755, 32=0.09967, and 42 =0.09967
105
Stage 3
o3 1.00002x103
13=63=0, 23=|53|= fc =
= 0.06283, 31 = 0.2000, and 41 = 0.2000
105
P.E. Allen - 2002
Page 9.7-39

Realization:
1
2
e
Vin(z)
23C13
43C13
33C13
53C23
C13
1
2
C23
2
V3(z)
Stage 3
1
42C12
Stage 2
1
2
32C12
C12
52C22
C22
e
V2(z)
1
2
22C12
21C11
41C11
31C11
51C21
C11
1
2
C21
2
Vout(z)
Stage 1
P.E. Allen - 2002
Page 9.7-40
Higher Order Switched Capacitor Filters - Ladder Approach

The ladder approach to filter design starts from RLC realizations of the desired filter
specification.
These RLC realizations are called prototype circuits.
Advantage:
Less sensitive to capacitor ratios.
Disadvantage:
Design approach more complex
Requires a prototype realization
Singly-terminated RLC prototype filters:
+
Vin (sn )
L2n
LN,n
CN-1,n
C1n
C3n
+
Vout (sn )
-
(a.)
+
LN,n
CN-1,n
Vin (sn )
L3n
C2n
L1n
1
Vout (sn )
-
(b.)
Figure 9.7-12 - Singly-terminated, RLC prototype filters. (a.) N even. (b.) N odd.
P.E. Allen - 2002
Page 9.7-41
Formulation of the State Variables of a Prototype Circuit

State Variables:
The state variables of a circuit are the current through an element or the voltage across it.
The number of state variables to solve a circuit
= number of inductors and capacitors - inductor cutsets and capacitor loops.
An inductor cutset is a node where only inductors are connected.
A capacitor loop is a loop where only capacitors are in series.
The approach:
Identify the correct state variables and formulate each state variable as function of
itself and other state variables.
Convert this function to a form synthesizable by switched capacitor.
A low pass example:
+
Vin (s n)
R0n
L1n
C2n
I5
I3
I1
+
-
L3n
V2
C4n
+
-
L5n
V4
R 6n
Vout (s n )
-
The state variables are I1 , V2, I3, V4, and I5.

(The correct state variables will be the currents in the series elements and the voltage
across the shunt elements.)
P.E. Allen - 2002

Page 9.7-42
Writing the State Equations for a RLC Prototype Circuit

Alternately use KVL and KCL for a loop and a node, respectively.
Vin(s) - I1(s)R0n - sL1nI1(s) - V2(s) = 0
I1:
V 2:
I1(s) - sC2nV2(s) - I3(s) = 0
V2(s) - sL3nI3(s) - V4(s) = 0
I3:
V 4:
I3(s) - sC4nV4(s) - I5(s) = 0
and
V4(s) - sL5nI5(s) - R6nI5n(s) = 0
I5:
However, we really would prefer Vout as a state variable instead of I5. This is achieved
using Ohms law to get for the last two equations:
Vout(s)
I3(s) - sC4nV4(s) - R6n = 0
V 4:
and
sL5nVout(s)
V4(s) - Vout = 0
Vout:
R6n
P.E. Allen - 2002
Page 9.7-43
Voltage Analogs of Current

A voltage analog, Vj, of a current Ij is defined as
Vj = RIj
where Ris an arbitrary resistance (normally 1 ohm).
Rewriting the five state equations using voltage analogs for current gives:
V (s)
1
Vin(s) - R (R0n + sL1n) - V2(s) = 0

V 1:
V 2:
V (s)
3
V2(s) - sL3n R - V4(s) = 0
V3:
V 4:
V (s)
V1(s)
3
sC
V
(s)
= 0
2n
2
R
R
V3(s)
Vout(s)
sC
V
(s)
4n
4
R
R6n = 0
and
Vout:
V4(s) -

sL5nVout(s)
- Vout = 0
R6n
P.E. Allen - 2002

Page 9.7-44
The State Variable Functions

Solve for each of the state variables a function of itself and other state variables.
R0n
R'
V1'(s) = sL1n Vin(s) - V2(s) - R' V1'(s)
1
V2(s) = sR'C2n [V1'(s) - V3'(s) ]
R'
V3'(s) = sL3n [V2(s) - V4(s)]
R'
1
V4(s) = sR'C4n [V3'(s) - R6n Vout(s)]
R6n
Vout(s) = sL5n [V4(s) - Vout(s)]
Note that each of these functions is the integration of voltage variables and is easily
realized using switched capacitor integrators.
P.E. Allen - 2002
Page 9.7-45
General Design Procedure for Low Pass, SC Ladder Filters

1.) From TBP, TSB, and n (or APB, ASB, and n) determine the required order of the filter
approximation.
2.) From tables similar to Table 9.7-3 and 9.7-2 find the RLC prototype filter
approximation.
3.) Write the state equations and rearrange them so each state variable is equal to the
integrator of various inputs.
4.) Realize each of rearranged state equations by switched capacitor integrators.
P.E. Allen - 2002
Page 9.7-46
Example 9.7-8 - Fifth-order, Low Pass, Switched Capacitor Filter using the Ladder
Approach
Design a ladder, switched capacitor realization for a Chebyshev filter approximation
to the filter specifications of TBP = -1dB, TSB = -25dB, fPB = 1kHz and fSB = 1.5 kHz. Give
a schematic and component value for the realization. Also simulate the realization and
compare to an ideal realization. Use a clock frequency of 20 kHz. Adjust your design so
that it does not suffer the -6dB loss in the pass band. (Note that this example should be
identical with Ex. 1.)
Solution
From previous work, we know that a 5th-order, Chebyshev approximation will
satisfy the specification. The corresponding low pass, RLC prototype filter is
L5n =2.1349 H L3n =3.0009 H L1n=2.1349 H
+
Vin (sn)
-
+
C 4n=
1.0911 F
C2n =
1.0911 F
Vout(s n)
-
Next, we must find the state equations and express them in the form of an integrator.
Fortunately, the above results can be directly used in this example.
Finally, use switched-capacitor integrators to realize each of the five state functions
and connect each of the realizations together.
P.E. Allen - 2002
Page 9.7-47

11C1
C1 V' (ej)
R0n
R'
1
L1n: V1'(sn) = sn L1n Vin(sn) - V2(sn) - R' V1'(sn)
(1) Vin(ej) 1
2
2
21C1
This equation can be realized by the switched capacitor
+
integrator of Fig. 9.7-17 which has one noninverting input V2(ej) 2
1
and two inverting inputs. Therefore,
31C1
1
j)
V'
(e
1
2
(2)
V1(z) = z-1 11Vin(z) - 21zV2(z) - 31zV1(z)
1
1
However, since fPB < fc, replace z by 1 and z-1 by sT.
Figure 9.7-17 - Realization of V1'.
1
V 1(sn) s T 11Vin(s) - 21V2(s) - 31V1(s)

(3)
n n
Equating Eq. (1) to Eq. (3) gives the capacitor ratios for the first integrator as
RTn RPB
12000
11 = 21 = L1n = fcL1n = 20,0002.1349 = 0.1472
and
R0nTn R0nPB
12000
31 = L1n = fcL1n = 20,0002.1349 = 0.1472
Assuming that R0n = R = 1. Also, double the value of 11 (11 = 0.2943) in order to get
0dB gain. The total capacitance of the first integrator is
2(0.1472)
1
First integrator capacitance = 2 + 0.1472 + 0.1472 = 10.79 units of capacitance.
P.E. Allen - 2002

Page 9.7-48

12C2
C2 V (ej)
2
V'1(ej)
1
1
2
C2n:
V2(sn) = sn R'C2n [V1'(sn) - V3'(sn)]
(4)
2
22C2
+
This equation can be realized by the switched
V'3(ej)
2
capacitor integrator of Fig. 9.7-18 which has one
1
1
noninverting input and one inverting input. As before
we write that
Figure 9.7-18 - Realization of V2.
1
(5)
V2(z) = z-1 12V1 (z) - 22zV3(z) .
Simplifying as above gives
1
(6)
V2(sn) snTn 12V1 (sn) - 22V3(sn) .
Equating Eq. (4) to Eq. (6) yields the design of the capacitor ratios for the second
integrator as
PB
Tn
2000
12 = 22 = RC2n = RfcC2n = 120,0001.0911 = 0.2879.
The second integrator has a total capacitance of
1
Second integrator capacitance = 0.2879 + 2 = 5.47 units of capacitance.
P.E. Allen - 2002
Page 9.7-49

R'
13C3
C3 V' (ej)
3
L3n: V3'(sn) = sn L3n [V2(sn) - V4(sn)]
(7)
j
V2(e )
1
2
2
Eq. (7) can be realized by the switched capacitor
23C3
+
integrator of Fig. 9.7-19 which has one noninverting
V4(ej)
2
input and one inverting input. For this circuit we get
1
1
1
V 3(z) = z-1 13V2 (z) - 23zV4(z) . (8)

Figure 9.7-19 - Realization of V3'.
Simplifying as above gives
1
(9)
V 3(sn) snTn 13V2(sn) - 23V4(sn) .
Equating Eq. (7) to Eq. (9) yields the capacitor ratios for the third integrator as
RTn RPB
12000
13 = 23 = L3n = fcL3n = 20,0003.0009 = 0.1047.
The third integrator has a total capacitance of
1
Third integrator capacitance = 0.1047 + 2 = 11.55 units of capacitance

P.E. Allen - 2002

Page 9.7-50

14C4
C4 V (ej)
R'
1
4
j
'
V'
(e
)
1
2
C4n: V4(sn) = sn R'C4n [V3 ( sn)- R6nVout(sn)] (10)
2
2
Eq. (10) can be realized by the switched capacitor
24C4
+
Vout(ej)
integrator of Fig. 9.7-20 with one noninverting and
2
1
1
one inverting input. As before we write that
1
V4(z) = z-1 14V3 (z) - 24zVout(z) .

(11)
Figure 9.7-20 - Realization of V4.
Assuming that fPB < fc gives
1
V4(sn) snTn 14V3 (sn) - 24Vout(sn) . (12)

Equating Eq. (10) to Eq. (12) yields the design of the capacitor ratios for the fourth
integrator as
PB
Tn
2000
14 = 24 = RC4n = RfcC4n = 120,0001.0911 = 0.2879.
if R = R0n. In this case, we note that fourth integrator is identical to the second integrator
with the same total integrator capacitance.
P.E. Allen - 2002
Page 9.7-51

R6n
15C5
C5 V (ej)
L5n:
Vout(sn) = snL5n [V4(sn) - Vout(sn)]
(13)
out
V4(ej)
1
2
2
The last state equation, Eq. (13), can be realized by
25C5
the switched capacitor integrator of Fig. 9.7-21 which V (ej)
+
out
2
has one noninverting input and one inverting input.
1
1
For this circuit we get
1
Figure 9.7-21 - Realization of Vout.
(14)
Vout(z) = z-1 15V4 (z) - 25zVout(z) .
Simplifying as before gives
1
Vout(sn) s T 15V4(sn) - 25Vout(sn).
(15)
n n
Equating Eq. (13) to Eq. (15) yields the capacitor ratios for the fifth integrator as
R6nTn R6nPB
12000
15 = 25 = L3n = fcL3n = 20,0002.1349 = 0.1472
where R6n = 1.
1
Fifth integrator capacitance = 0.1472 + 2 = 8.79 units of capacitance
We see that the total capacitance of this filter is 10.79 + 5.47 + 11.53 + 5.47 + 8.79 =
42.05. We note that Ex. 1 which used the cascade approach for the same specification
required 49.10 units of capacitance.
P.E. Allen - 2002

Final realization of Ex. 9.7-8.
Page 9.7-52
31C1
Vin(ej)
1
211C1
C1
2
21C1
1
2
C2
22C2
1
C3
13C3
2
23C3
1
2
C4
24C4
1
+
15C5
C5
2
25C5
1
V'3(ej)
14C2 1
1
2
V4(ej)
V'1(ej)
12C2 1
V2(ej)
1
2
1
2
Vout(ej)
P.E. Allen - 2002
Page 9.7-53

Simulated Frequency Response:
10
200
150
Magnitude (dB)
V1' Output
-10
V2 Output
-20
V3' Output
-30
-40
V4 Output
-50
Filter Output
Filter Phase
V2 Phase
100
V3' Phase
50
0
-50
V4 Phase
-100
V1' Phase
-150
-60
-200
-70
0
500
1000
1500 2000 2500

Frequency (Hz)
3000
3500
500
1000
1500 2000 2500

Frequency (Hz)
3000
3500
Comments:
Both passband and stopband specifications satisfied.
Some of the op amp outputs are exceeding 0 dB (need to voltage scale for maximum
dynamic range)
P.E. Allen - 2002
Page 9.7-54

SPICE Input File:
******* 08/29/97 13:12:51 *********
******PSpice 5.2 (Jul 1992) ********
**** CIRCUIT DESCRIPTION ****
*SPICE FILE FOR EXAMPLE 9.7_5
*Example 9.7-8 : ladder filter
*Node 5 is the output at V1'
*Node 7 is the output at V2
*Node 9 is the output of V3'
*Node 11 is the output of V4
*Node 15 is the final output
VIN 1 0 DC 0 AC 1
**************************
* V1' STAGE
XNC11 1 2 3 4 NC11
XPC11 7 8 3 4 PC1
XPC12 5 6 3 4 PC1
XUSC1 5 6 3 4 USCP
XAMP1 3 4 5 6 AMP
**************************
*V2 STAGE
XNC21 5 6 19 20 NC2
XPC21 9 10 19 20 PC2
XUSC2 7 8 19 20 USCP
XAMP2 19 20 7 8 AMP
**************************
*V3' STAGE
XNC31 7 8 13 14 NC3
XPC31 11 12 13 14 PC3
XUSC3 9 10 13 14 USCP
XAMP3 13 14 9 10 AMP
**************************
*V4 STAGE
XNC41 9 10 25 26 NC2
XPC41 15 16 25 26 PC2
XUSC4 11 12 25 26 USCP
XAMP4 25 26 11 12 AMP
**************************
*VOUT STAGE
XNC51 11 12 17 18 NC1
XPC51 15 16 17 18 PC1
XUSC5 15 16 17 18 USCP
XAMP5 17 18 15 16 AMP
*************************
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=25US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 6.7934
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 .1472
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 .1472
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 .1472
RNC2 4 0 6.7934
.ENDS NC1
P.E. Allen - 2002
Page 9.7-55

SPICE Input File:
.SUBCKT NC11 1 2 3 4
RNC1 1 0 3.3978XNC1 1 0 10 DELAY
GNC1 1 0 10 0 .2943
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 .2943
XNC3 4 0 40 DELAYGNC3 4 0 40 0 .2943
RNC2 4 0 3.3978
.ENDS NC11
.SUBCKT NC2 1 2 3 4
RNC1 1 0 3.4730
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 .2879
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.2879
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.2879
RNC2 4 0 3.4730
.ENDS NC2
GNC3 4 0 40 0 0.1047
RNC2 4 0 9.5521
.ENDS NC3
.SUBCKT NC4 1 2 3 4
RNC1 1 0 3.4730
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 .2879
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 .2879
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 .1472
RNC2 4 0 6.7955
.ENDS NC4
.SUBCKT PC1 1 2 3 4
RPC1 2 4 6.7934
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 3.4730
.ENDS PC2
.SUBCKT NC3 1 2 3 4
RNC1 1 0 9.5521
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.1047
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.1047
XNC3 4 0 40 DELAY
.SUBCKT PC3 1 2 3 4
RPC1 2 4 9.5521
.ENDS PC3
P.E. Allen - 2002
Page 9.7-56

Switcap2 Input File (The results are exactly the same as for the SPICE simulation)
TITLE: EXAMPLE 9-7-11
CIRCUIT
OPTIONS;
NOLIST;
GRID;
END;
/***** V1 STAGE ****/

X11 (1 2) NC (0.2943);
X12 (3 2) PC (0.1472);
X13 (4 2) PC (0.1472);
E11 (4 0 0 2)
1E6;
C11 (2 4) 1;
TIMING;
PERIOD 50E-6;
CLOCK CLK 1 (0 25/50);
END;
SUBCKT (1 4) NC (P:CAP);
S1
(1 2)
CLK;
S2
(2 0)
#CLK;
S3
(3 0)
CLK;
S4
(3 4)
#CLK;
C11
(2 3)
CAP;
END;
SUBCKT (1 4) PC (P:CAP1);
S1
(1 2)
#CLK;
S2
(2 0)
CLK;
S3
(3 0)
CLK;
S4
(3 4)
#CLK;
C21
(2 3)
CAP1;
END;
/***** V2 STAGE ****/

X21 (1 2) NC (0.2879);
X22 (3 2) PC (0.2879);
E21 (3 0 0 6)
1E6;
C21 (6 3) 1;
/***** V3 STAGE ****/
X31 (3 8) NC (0.1047);
X32 (7 8) PC (0.1047);
E31 (5 0 0 8)
1E6;
C31 (8 5) 1;
/***** VOUT STAGE

****/
X51 (7 10) NC (0.1472);
X52 (100 10)
PC
(0.1472);
E51 (100 0 0 10) 1E6;
C51 (10 100)
1;
V1 (1 0);
END;
ANALYZE SSS;
INFREQQ 20 3000 LOG 80;
SET V1 AC 1.0 0.0;
PRINT VDB(4) VP(4)
VDB(3);
PRINT VP(3) VDB(7) VP(7);
PRINT VDB(100) VP(100);
PLOT VDB(100);
END;
END;
/***** V4 STAGE ****/

X41 (5 9) NC (0.2879);
X42 (100 9)
PC
(0.2879);
E41 (7 0 0 9)
1E6;
C41 (9 7) 1;
P.E. Allen - 2002
Page 9.7-57
High Pass Switched Capacitor Filters Using the Ladder Approach

High pass, switched capacitor filters using the ladder approach are achieved by
applying the following normalized, low pass to normalized, high pass transformation on
the RLC prototype circuit.
1
sln = shn
This causes the following transformation
Chn = 1
Lln
on the inductors and capacitors of the
Lln
RLC prototype:
1
C
s ln s
hn
ln
Lhn = 1
Cln
Design Procedure:
Normalized LowNormalized High1.) Identify the appropriate RLC
Pass
Network
Pass Network
prototype, low pass circuit to meet
the specifications.
2.) Transform each inductor and capacitor by the normalized, low pass to high pass
transformation.
3.) Choose the state variables and write the state functions.
4.) Realize the state functions using switched capacitor circuits.
The problem: The realizations are derivative circuits.
P.E. Allen - 2002
Page 9.7-58
Switched Capacitor Derivative Circuit

2
C1
1
C2
Vin(z) C1
Vout(z)
Vin(z) C1
1
-
Vin(z) C1
Vout(z)
Vout(z)
(a.)
C2
C2
(b.)
(c.)
Figure 9.7-26 - (a.) Switched capacitor differentiatior circuit. (b.) Stray insensitive version of (a.).
(c.) Modification to keep op amp output from being discharged to ground during 1.
Transfer function:
1: (n-1)T < t < (n -0.5)T
e
o
vc1(n -0.5)T = vin(n -1)T
and
o
vc2(n -0.5)T = 0
C1
vin(n-1)
C2
e
vout
(n)
vin(n)
2: (n-0.5)T < t < (n )T
C1 e
C1 e
e
vout(n )T = - C2 vin(n )T + C2 vin(n -1)T
e
Vout(z)
C1 e
C1 e
C1
C1
e
e
Vout(z) = C V in(z) - z-1 C V in(z) = - C (1-z-1)Vin(z) Hee(z) =
=
e
C2 (1-z-1)
2
2
2
V in(z)
P.E. Allen - 2002
Page 9.7-59
Frequency Response of the Derivative Circuit

Replace z by ejT to get,
C1
C1 ejT/2 - e-jT/2
C1
-jT/2
Hee(ejT) = - C 1 - e-jT = - C
=
C2 2j sin(T/2)e
ejT/2
2
2
or
jTC1 sin(/2)
-j sin(/2)
= - C2 /2 (-j/2) = o /2 e-jT/2
= (Ideal)x(Mag. Error)x(Phase Error)
where o = C2/(C1T).
Frequency Response for C2 = 0.2C1:
|Hee(ejT)
5
10
1
0
Continuous
Time
Discrete
Time
0 o= 10c
c
2

Phase
0
-90
c
c
2
Continuous
Time
-180
-270
Discrete
Time
P.E. Allen - 2002

Page 9.7-60
Example 9.7-9 - High Pass, Switched Capacitor Ladder Filter

Design a high pass, switched capacitor ladder filter starting from a third-order,
normalized, low pass Butterworth prototype filter. Assume the cutoff frequency is 1kHz
and the clock frequency is 100kHz. Use the doubly terminated structure.
Solution
A third-order
L3n
C3hn
L1n
C1hn
R0n
R0n
prototype filter
=1H
=1F I3
=1 =1H
=1 =1F
s = 1
transformed to the
+ ln shn
+
+
L2hn
C2n
R
R
normalized high
I
4n
4n
1
Vout
V
Vin
Vin
=0.5H V2 =1 - out
=2F
=1 pass filter is shown.
State Variable Eqs:
I1
R0n
Vin=I1R0n+snC1hn+V2 I1 = snC1hn [Vin - I1R0n - V2] V1 = snC1hnR [Vin - R V 1-V 2]
V2
V2
Vout
Vout
V1 Vout
I1 = s L + I3 = s L + R
V2 = snL2hn [I1 - R ]
V
=
s
L
[
2
n 2hn R - R4n ]
n 2hn
n 2hn
4n
4n
I3
V2 = snC3hn + I3R4n I3 = snC3hn [V2 - I3R4n]
Vout = snR4nC3hn [V2 - Vout]

Problem! Derivative circuit only has inverting inputs. Solution?
1.) Use inverters.
2.) Rearrange the eqs. to get integrators where possible.
3.) Redefine the polarity of the voltages at internal nodes (180 phase reversal).
P.E. Allen - 2002
Page 9.7-61

Make the first eq. into an integrator, reverse the sign of V2 and V1, and use one inverter.
Note that V1' = - V 1' andV2 = - V2 . Therefore the rewrite the first state equation as:
- V 1
R0n
-V 1
R
R
'
'
'
'
V 1=snC1hnR [Vin- R V1-V2] V1=snC1hnR0n +R0n(Vin -V2) V 1 =snC1hnR0n -R0n(Vin+ V2 )
V 1 V
- V 1 Vout
V1 Vout
out
V2 = snL2hn[ R - R4n ] V2 = -snL2hn[ R - R4n ] V2 =-snL2hn R + R4n

Vout = snR4nC3hn [- V2 - Vout]
31C1
C1hn:
V2
21C1
This state equation can be realized by the SC
C1
integrator shown with two inverting unswitched inputs. Vin
V1'
11C1
-11z
V1'
2
2
V 1 (z) = z -1 V 1 (z) - 21Vin(z) - 31 V2 (z)
+
1
1
Assuming that z -1 sT and z 1, we write that
-11
V 1 (s) sT V 1 (s) - 21Vin(s) - 31 V2 (s)
Normalizing this equation gives,
-11
Tn
2103
V 1' (sn) snTn V 1' (sn)-21Vin(sn)-31 V2 (sn) 11=R0nC1hn = 1105 =0.06283, 21=31=1
P.E. Allen - 2002

L2hn:
This state eq. can be realized by the SC
differentiator circuit shown with two inputs.
V2(z) = -(1-z-1)[12 V 1 (z) + 22Vout(z)]
V2(s) -sT [12 V 1 (s) + 22Vout(s)]
Page 9.7-62
12C2
V1'
Vout
C2
2
1
V2
1
-
1 2
22C2
Normalizing T by PB gives V2(sn) = -snTn

[12 V 1 (sn) + 22Vout(sn)]
L2hn 0.5105
12 = 22 = T = 2103 = 7.9577 if R = R0n = 1.
n
L2hn:
This state equation can be realized by the SC
differentiator circuit shown with two inputs.
Vout(z) = -(1-z-1)[13 V2 (z) + 23Vout(z)]
Vout(s) -sT [13 V2 (s) + 23Vout(s)]
V2
13C3
V2
Vout
C3
2
1
1 2
23C3
Vout
1
+
Normalizing T by PB gives Vout(sn) = -snTn [13 V2 (sn) + 23Vout(sn)]

R4nC3hn 1105
13 = 23 = Tn = 2103 = 15.915 if R4n = 1. capacitances =100.49 units of C
P.E. Allen - 2002
Page 9.7-63
Bandpass Switched Capacitor Filters Using the Ladder Approach

Bandpass switched capacitor ladder filters are obtained from low pass RLC prototype
circuits by applying the normalized, low pass to normalized bandpass transformation
given as
1 r
1
r sb
sln = B Wr + (sb/r) = B Wsbn + sbn
This causes the following
r
Lln Cbn = BW 1
Lbn =
transformation on the inductors and
r Lln
BW
Lln
capacitors of the RLC prototype:
Cln
sn
r
s bn + 1
sbn
BW
Cbn =
r
Cln
BW
Design Procedure:
1.) Identify the appropriate RLC
Normalized
Lbn = BW 1
Low-Pass
r Cln
prototype, low pass circuit to meet
Network
Normalized Bandpass Network
the specifications.
2.) Transform each inductor and capacitor by the normalized, low pass to bandpass
transformation.
3.) Choose the state variables and write the state functions.
4.) Realize the state functions using switched capacitor circuits.
In this case, the state functions will be second-order, bandpass functions which can
be realized by switched-capacitor biquads.
P.E. Allen - 2002
Page 9.7-64
Example 9.7-10 - Design of a 4th-Order, Butterworth Bandpass, SC Ladder Filter

Design a fourth-order, bandpass, switched capacitor ladder filter. The filter is to have a
center frequency (r) of 3kHz and a bandwidth (BW) of 600 Hz. fc = 128kHz.
Solution
R0n =1 L2n=1.8478H L 4n=0.7659H
The low pass normalized prototype
+
+
+
filter is shown (Note that this form is slightly V (s )
R5n
V
(sn )
C
=
C
out
=
3n
in n
1n
=1
different than the form used in Table 9.7-4)
1.8478F 0.7659F
-
Applying the lowpass-bandpass

transformation on the elements
gives,
R0n
Vin(sn)
C1bn =
r C
1ln
BW
L2bn =
C2bn =
r
L2ln
1/L2bn
BW
+
I2 C
=
V1 L1bn = 3bn
rC
3ln
1/C
1bn
BW
L4bn =
+
V3
-
r
L4ln C4bn =
BW
1/L4bn
I4
L3bn =
1/C3bn
R5n
+
Vout(sn)
-
Ex.6-B
The state equations for this
circuit can be written as illustrated below.
V1(s)
Z1bn
Vin(s) = I2(s) + Z1bn R0n + V1(s) V1(s) = R0n [Vin(s) - I2(s)R0n - V1(s)]
sL1bn(1/sC1bn)
s/C1bn
s/C1bn
= 2
where
Z1bn = sL1bn + (1/sC1bn) = 2
s + (1/L1bnC1bn) s +1
s/R0nC1bn
R0n
V1(s) =
Vin(s) - R V 2(s) - V 1(s)
2
s +1
(1)
P.E. Allen - 2002
Page 9.7-65

sR/L2bn
[V (s) - V (s)]
V2(s) = 2
3
s +1 1
I2(s) = Y2bn[V1(s) - V3(s)]
(2)
V 2 (s) Vout(s)
s/RC3bn
R
V3(s)=Z3bn(I2(s)-I4(s))=Z3bn R - R
V
(s)V
V3(s)=
(3)
2
out
R
2
5n
s +1
5n
and
I4(s) =Y4bn[V3(s)-Vout(s)] Vout(s) = R5nY4bn[V3(s)-Vout(s)]
sR5n/L4bn
[V3(s)-Vout(s)]
or Vout(s) =
s 2+1
How to realize? Consider the bandpass form of the low-Q and high-Q biquads:
2C1
2C1
1
2
C1
e
V1(z)
5C2
6C2
4C1
2
1
e
Vout(z)
4C2
Vin(z)
C2
1
2
(4)
Low Q, switched capacitor, biquad BP realization.
5C2
C1 Ve (z)
1
Vin(z) 3C1
-
1
2
C2
2
Vout(z)
High Q, switched capacitor, biquad realization.
P.E. Allen - 2002
Page 9.7-66

Note that the high-Q biquad can only have inverting inputs. Therefore, we shall use the
low-Q biquad to realize the above state equations because it can have both inverting and
noninverting inputs (4C2).
For the low-Q biquad, if we let 1 = 3 = 6 = 0, we get
-(4s/T)
- (4sn/Tn)
Normalizing by n gives
ee(sn)
Hee(s) 2
H
s + (25/T2)
sn2+ (25/Tn2)
All the 2s and 5s will be given as: 25 = Tn2 = n2T 2 = r2/fc2 = (2)2(fr/fc)2
2fr 23x103
2 = |5| = f =
= 0.1473
c
128x105
Now all that is left is to design 4 for each stage (assuming R0n = R5n = R = 1).
Therefore, let
Also, the sum of capacitances per stage will be:

2
4
|5|
2
capacitances/stage = min + min + min + min x (no. of inputs)
P.E. Allen - 2002
Page 9.7-67

Stage 1
Tn
41
rBW
1
2600
=
=
=
=
41
Tn R0nC1bn
R0nC1bn fcrC1ln 128x1030.7658 = 0.03848
There will be one noninverting input (Vin) and two inverting inputs (V2 and V1).
2(0.1437)
2
capacitances = 0.03848 + 0.03848 + 3 = 62.44 units of capacitance
Stage 2
42
rBW
TnBW
R
2600
=
=
=
=
42 rL2ln fcrL2ln 128x1031.8478 = 0.01594
Tn L2bn
There will be one noninverting input (V1) and one inverting input (V3).
2
2(0.1437)
capacitances = 0.01594 + 0.01594 + 2 = 145.50 = units of capacitance
Stage 3
Same as stage 2. 43 = 0.01594
There will be one noninverting input (V2) and one inverting input (Vout).
capacitances = 145.50 units of capacitance
Stage 4
Same as stage 1 except capacitances = 61.44 units of capacitance. 44 = 0.03848.
There will be one noninverting input (V3) and one inverting input (Vout).
P.E. Allen - 2002
Page 9.7-68

Total capacitance of this example is 414.88 units of capacitance.
Realization:
5C2
C1
1
2
1
2
C2
2
2
1
2C1
2,5
+
Ex.9.7-13B
Using this simplification gives:

41C21
Vin 1 41C21
2
41C21
21 =
51 =
0.1473
V'2
22 =
52 =
0.1473
143C23 43C23
2
23 =
53 =
0.1473
Vout
24 =
52 =
0.1473 2
1 2
1
2
V1 C
V3 C C
2
42 22 42C22 1
2
44 42 44 42 1
P.E. Allen - 2002
Page 9.7-69
General Approach to Designing Switched Capacitor Ladder Filters

Choose
State
Variables
Low pass
Prototype
RLC Ckt.
Write
State
Equations
Use SC
Integrators to
Design Each
State Equation
Low Pass
Switched
Capacitor
Filter
Normalized LP
to Normalized
High pass
Transformation
Choose
State
Variables
Write
State
Equations
Use SC
Differentiators
to Design Each
State Equation
High Pass
Switched
Capacitor
Filter
Normalized LP
to Normalized
Bandpass
Transformation
Choose
State
Variables
Write
State
Equations
Use SC
BP Ckts. to
Design Each
State Equation
Bandpass
Switched
Capacitor
Filter
Eliminate
L-cutsets
and
C-loops
Normalized LP
to Normalized
Bandpass
Transformation
Normalized LP
to Normalized
High pass
Transformation
Choose
State
Variables
Write
State
Equations
Use SC
BS Ckts. to
Design Each
State Equation
Bandstop
Switched
Capacitor
Filter
P.E. Allen - 2002
Page 9.7-70
ANTI-ALIASING IN SWITCHED CAPACITOR FILTERS

A characteristic of circuits that sample the signal (switched capacitor circuits) is that
the signal passbands occur at each harmonic of the clock frequency including the
fundamental.
T(j)
T(j0)
T(jPB)
Anti-Aliasing Filter
Baseband
c-PB
c+PB
2c-PB
2c+PB
0
c
2c
-PB 0 PB
Figure 9.7-28 - Spectrum of a discrete-time filter and a continuous-time
anti-aliasing filter.
The primary problem of aliasing is that there are undesired passbands that contribute
to the noise in the desired baseband.
P.E. Allen - 2002
Page 9.7-71
Noise Aliasing in Switched Capacitor Circuits

In all switched capacitor circuits, a noise aliasing occurs from the passbands that
occur at the clock frequency and each harmonic of the clock frequency.
Magnitude
;;
;;
;;
From higher bands

Noise Aliasing
Baseband
fc-fsw
fc+fsw
f
fc-fB
-fB
fc+fB
0.5fc
fc
0 fsw fB
Figure 9.7-31 - Illustration of noise aliasing in switched capacitor circuits.
It can be shown that the aliasing enhances the baseband noise voltage spectral density by
a factor of 2fsw/fc. Therefore, the baseband noise voltage spectral density is
kT/C 2fsw
2kT
2
eBN = fsw x fc = fcC volts2/Hz

Multiplying this equation by 2fB gives the baseband noise voltage in volts(rms)2.
Therefore, the baseband noise voltage is
2kT
2kT 2fB 2kT /C
vBN = fcC 2fB = C fc = OSR volts(rms)2
where OSR is the oversampling ratio.

P.E. Allen - 2002

Page 9.7-72
Simulation of Noise in Switched Capacitor Filters

The noise of switched capacitor filters can be simulated using the above concepts.
1.) Convert the switched capacitor filter to a continuous time equivalent filter by
replacing each switched capacitor with a resistor whose value is 1/(fcC).
2.) Multiply the noise of this resistance by 2fB/fc, to make the resulting noise to
approximate that of the switched capacitor filter.
Unfortunately, simulators like SPICE do not permit the multiplication of the thermal
noise. Another approach is to assume that the resistors are noise-free and build a noise
generator that represents the effect of the noise of vBN2.
1.) Put a zero dc current through a resistor identical to the one being modeled.
2.) A voltage source that is dependent on the voltage across this resistor can be placed at
the input of an op amp to implement vBN2. The gain of the voltage dependent source
should be 2fB/fc.
3.) Model all resistors that represent switched capacitors in the same manner.
The resulting noise source model along with the normal noise sources of the op amp will
serve as a reasonable approximation to the noise in a switched capacitor filter.
P.E. Allen - 2002
Page 9.7-73
CONTINUOUS TIME ANTI-ALIASING FILTERS

Sallen and Key, Unity Gain, Low Pass Filter
C2
Vin (s)
R1
R3
K=1
C4
(a.)
Vout (s)
K=1
Voltage
Amplifier
(b.)
Transfer function:
K
TLP(0) o2
R1R3C2C4
Vout(s)
=
=
1
o
1
1
K
1
Vin(s)
s 2 + s R3C4 + R1C2 + R3C2 - R3C4+ R1R3C2C4
s 2 + Q s + o2
We desire K = 1 in order to not influence the passband gain of the SCF. With K = 1,
1
R1R3C2C4
1/mn(RC)2
Vout(s)
=
=
1
s 2 + (1/RC)[(n+1)/n]s + 1/mn(RC)2
1
1
Vin(s)
s 2 + s R1C2 + R3C2 + R1R3C2C4
where R3 = nR1 = nR
and C4 = mC2 = mC.
P.E. Allen - 2002

Page 9.7-74
Design Equations for The Unity Gain, Sallen and Key Low Pass Filter
Equating Vout(s)/Vin(s) to the standard second-order low pass transfer function, we
get two design equations which are
1
o =
mnRC
m
1
Q = (n +1) n
The approach to designing the components of Fig. 9.7-29a is to select a value of m
compatible with standard capacitor values such that
1
m 4Q 2 .
Then, n, can be calculated from
1
1
n = 2mQ 2 - 1 2mQ 2 1-4mQ 2 .
This equation provides two values of n for any given Q and m. It can be shown that
these values are reciprocal. Thus, the use of either one produces the same element
spread.
Incidentally, these filters have excellent linearity because the op amp is in unity gain.
P.E. Allen - 2002
Page 9.7-75
Example 9.7-11 - Application of the Sallen-Key Anti-Aliasing Filter

Use the above design approach to design a second-order, low-pass filter using Fig.
9.7-7a if Q = 0.707 and fo = 1 kHz
Solution
We see that m should be less than 0.5 for this example. Let us choose m = 0.5.
m = 0.5 n = 1.
These choices guarantee that Q = 0.707.
1
Now, use o =
to find the RC product RC = 0.225x10-3.
mnRC
At this point, one has to try different values to see what is best for the given situation
(typically the area required).
Let us choose C = C2 = 500pF.
This gives R = R1 = 450k. Thus, C4 = 250pF and R3 = 450k.
It is readily apparent that the anti-aliasing filter will require considerable area to
implement.
P.E. Allen - 2002
Page 9.7-76
A Negative Feedback, Second-Order, Low Pass Anti-Aliasing Filter

Another continuous-time filter suitable for anti-aliasing filtering is shown in Fig. 9.730. This filter uses frequency-dependent negative feedback to achieve complex conjugate
poles.
R1=
1
2|TLP(0)|oQC
Vin
C4=
4Q2(1+|TLP(0)|)C
R2=
1
2oQC
C5=C
R3=
1
2(1+|TLP(0)|)oQC
Vout
Figure 9.7-30 - A negative feedback realization of a second-order, low pass filter.
This gain of this circuit in the passband is determined by the ratio of R2/R1.
P.E. Allen - 2002
Page 9.7-77
Example 9.7-12 - Design of A Negative Feedback, Second-Order, Low-Pass Active

Filter
Use the negative feedback, second-order, low-pass active filter of Fig. 9.7-30 to
design a low-pass filter having a dc gain of -1, Q = 1/ 2 , and fo = 10kHz.
Solution
Let us use the design equations given on Fig. 9.7-30. Assume that C5 = C = 100pF.
Therefore, we get C4 = (8)(0.5)C = 400pF. The resistors are
2
R1 = (2)(1)(6.2832)(10-6) = 112.54 k
2
R2 = (2)(6.2832)(10-6) = 112.54 k
and
2
R3 = (2)(6.2832)(2)(10-6) = 56.27 k
Unfortunately we see that again because of the passive element sizes that antialiasing filters will occupy a large portion of the chip.
P.E. Allen - 2002
Page 9.8-1
SUMMARY
Switched capacitor circuits have reached maturity in CMOS technology.
The switched capacitor circuit concept was a pivotal step in the implementation of
analog signal processing circuits in CMOS technology.
The accuracy of the signal processing is proportional to the capacitor ratios.
Switched capacitor circuits have been developed for:
Amplification
Integration
Differentiation
Summation
Filtering
Comparison
Analog-digital conversion
Approaches to switched capacitor circuit design:
Oversampled approach clock frequency is much greater than the signal frequency
z-domain approach the specifications are converted to the z-domain and directly
realized. Such circuits can operate to within half of the clock frequency.
SPICE or SWITCAP permits frequency domain simulation of switched capacitor ckts.
Clock feedthrough and kT/C noise represent the lower limit of the dynamic range of
switched capacitor circuits.
P.E. Allen - 2002

Chap09 2UP 5 2 04

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Chap09 2UP 5 2 04

Hochgeladen von

Copyright:

Verfügbare Formate

Chapter 9 Switched Capacitor Circuits

CHAPTER 9 SWITCHED CAPACITOR CIRCUITS

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Advantages of Switched Capacitor Circuits

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

SECTION 9.1 SWITCHED CAPACITOR CIRCUITS

Two-Phase, Nonoverlapping Clock:

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Equivalent Resistance of a Switched Capacitor Circuit

However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore,

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Example 9.1-1 - Design of a Parallel Switched Capacitor Resistor Emulation

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Power Dissipation in the Resistance Emulation

Continuous Time Resistor:

Discrete Time Resistor Emulation:

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Other SC Equivalent Resistance Circuits

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Example 9.1-2 - Design of a Series-Parallel Switched Capacitor Resistor Emulation

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Summary of the Four Switched Capacitor Resistance Circuits

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Accuracy of Switched Capacitor Circuits

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

ANALYSIS OF SWITCHED CAPACITOR CIRCUITS

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

CMOS Analog Circuit Design

0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5

Chapter 9 Section 1 (5/2/04)

Analysis Methods for Two-Phase, Nonoverlapping Clocks - Contd

V(z) = v(nT)z- n = v(0) + v(T)z- 1 + v(2T)z- 2 +

for all z for which the series V(z) converges.

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Transfer Function Viewpoint of Switched Capacitor Circuits

Vo (z) = Vo (z) + Vo (z)

z-domain transfer functions:

Vo(z) Vo(z) + Vo (z)

CMOS Analog Circuit Design

P.E. Allen - 2004

Chapter 9 Section 1 (5/2/04)

Approach for Analyzing Switched Capacitor Circuits

CMOS Analog Circuit Design