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24-Bit

ADC DS
VREFP VREFN CAP DVDD
GND
AINP
AINN
SCLK
SPEED
DRDY/DOUT
PDWN
AVDD
Internal
Oscillator
G = 128
SW
CAP
CLKIN
EMI
Filter
A D S 1 2 3 1
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2 4 - B it A n a l og - to- D ig ita l C on v e r te r
f or B r id g e S e n s or s
C he ck f or S a mpl e s : A D S 1 2 3 1
1 FEA TURES D ES C RIPTION
The ADS1231 is a precision, 24-bit analog-to-digital
2 C ompl e te Fr on t- En d f or B r id g e S e n s or s
converter (ADC). With an onboard low-noise
In te r n a l A mpl if ie r , Ga in of 1 2 8
amplifier, onboard oscillator, precision third-order 24-
In te r n a l Os cil l a tor
bit delta-sigma () modulator, and bridge power
switch, the ADS1231 provides a complete front-end
Low- S id e Powe r S witch f or B r id g e S e n s or
solution for bridge sensor applications including
Low Nois e : 3 5n Vr ms
weigh scales, strain gauges, and load cells.
S e l e cta bl e D a ta Ra te s : 1 0S PS or 80S PS
The low-noise amplifier has a gain of 128, supporting
S imul ta n e ous 50Hz a n d 60Hz Re je ction a t
a full-scale differential input of 19.5mV. The ADC
1 0S PS
has 24-bit resolution and is comprised of a third-order
In put EMI Fil te r modulator and fourth-order digital filter. Two data
rates are supported: 10SPS (with both 50Hz and
Exte r n a l Vol ta g e Re f e r e n ce up to 5V f or
60Hz rejection) and 80SPS. The ADS1231 can be
Ra tiome tr ic Me a s ur e me n ts
put in a low-power standby mode or shut off
S impl e , Pin - D r iv e n C on tr ol
completely in power-down mode.
Two- Wir e S e r ia l D ig ita l In te r f a ce
The ADS1231 is controlled by dedicated pins; there
S uppl y Ra n g e : 3 V to 5.3 V
are no digital registers to program. Data are output
over an easily-isolated serial interface that connects Pa cka g e : S OIC - 1 6
directly to the MSP430 and other microcontrollers.
Te mpe r a tur e Ra n g e : 4 0C to +85C
The ADS1231 is available in an SO-16 package and
A PPLIC A TIONS is specified from40C to +85C.
We ig h S ca l e s
S tr a in Ga ug e s
Loa d C e l l s
In d us tr ia l Pr oce s s C on tr ol
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 20092013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
A D S 1 2 3 1
SBAS414D J ULY 2009 REVISED OCTOBER 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range fromsubtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORD ERING INFORMA TION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
A B S OLUTE MA XIMUM RA TINGS
(1 )
Over operating free-air temperature range, unless otherwise noted.
A D S 1 2 3 1 UNIT
AVDD to GND 0.3 to +6 V
DVDD to GND 0.3 to +6 V
100, momentary mA
Input current
10, continuous mA
Analog input voltage to GND 0.3 to AVDD +0.3 V
Digital input voltage to GND 0.3 to DVDD +0.3 V
Human body model (HBM)
2000 V
J EDEC standard 22, test method A114-C.01, all pins
ESD
(2)
Charged device model (CDM)
500 V
J EDEC standard 22, test method C101, all pins
Maximumjunction temperature +150 C
Operating temperature range 40 to +85 C
Storage temperature range 60 to +150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
THERMA L INFORMA TION
A D S 1 2 3 1
THERMA L METRIC
(1 )
S OIC (D ) UNITS
1 6 PINS

J A
J unction-to-ambient thermal resistance 79.5

J Ctop
J unction-to-case (top) thermal resistance 37.5

J B
J unction-to-board thermal resistance 37.1
C/W

J T
J unction-to-top characterization parameter 5.6

J B
J unction-to-board characterization parameter 36.7

J Cbot
J unction-to-case (bottom) thermal resistance n/a
(1) For more information about traditional and newthermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: ADS1231
A D S 1 2 3 1
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ELEC TRIC A L C HA RA C TERIS TIC S
Minimum/maximumlimit specifications apply from40C to +85C. Typical specifications at +25C.
All specifications at AVDD =DVDD =VREFP =+5V, V
CM
=2.5V and VREFN =GND, unless otherwise noted.
A D S 1 2 3 1
PA RA METER C OND ITIONS MIN TYP MA X UNIT
A NA LOG INPUTS
0.5V
REF
/ 128 V
Full-scale input voltage (AINP AINN) V
REF
=AVDD =5V 19.5 mV
V
REF
=AVDD =3V 11.7 mV
Common-mode input range GND +1.5 AVDD 1.5 V
Differential input current 2 nA
LOW- S ID E POWER S WITC H
AVDD =5V, I
SW
=30mA 3.5 5
On-resistance (R
ON
)
AVDD =3V, I
SW
=30mA 4 7
Current through switch 30 mA
S YS TEM PERFORMA NC E
Resolution No missing codes 24 Bits
Internal oscillator, SPEED =high 80 SPS
Internal oscillator, SPEED =low 10 SPS
Data rate
External clock, SPEED =high f
CLKIN
/ 61,440 SPS
External clock, SPEED =low f
CLKIN
/ 491,520 SPS
Digital filter settling time Full settling 4 Conversions
f
DATA
=10SPS, AVDD =V
REF
=5V 35 nV, rms
f
DATA
=80SPS, AVDD =V
REF
=5V 102 nV, rms
Noise
f
DATA
=10SPS, AVDD =V
REF
=5V 232 nV, P-P
f
DATA
=80SPS, AVDD =V
REF
=5V 622 nV, P-P
Integral nonlinearity (INL) Differential input, end-point fit 8 ppm
Input offset error 10 V
Input offset drift 20 nV/C
Gain error 1 %
Gain drift 2 ppm/C
f
IN
=50Hz or 60Hz 1Hz, f
DATA
=10SPS,
80 100 dB
internal oscillator
Normal-mode rejection
(1)
f
IN
=50Hz or 60Hz 1Hz, f
DATA
=10SPS,
90 110 dB
external clock
(2)
Common-mode rejection At dc 110 dB
Power-supply rejection At dc 90 100 dB
VOLTA GE REFERENC E INPUT
Voltage reference input (V
REF
) V
REF
=VREFP VREFN 1.5 AVDD AVDD +0.1 V
Negative reference input (VREFN) GND 0.1 VREFP 1.5 V
Positive reference input (VREFP) VREFN +1.5 AVDD +0.1 V
Voltage reference input current 10 nA
D IGITA L INPUT/OUTPUT (D VD D = 3 V to 5.3 V)
V
IH
0.8 DVDD DVDD +0.1 V
V
IL
GND 0.2 DVDD V
Logic levels
V
OH
I
OH
=500A DVDD 0.4 V
V
OL
I
OL
=500A 0.2 DVDD V
Input leakage 0<V
DIGITAL INPUT
<DVDD 10 A
External clock input frequency (f
CLKIN
) 1 4.9152 6 MHz
Serial clock input frequency (f
SCLK
) 5 MHz
(1) Specification is assured by the combination of design and final test.
(2) f
CLKIN
=4.9152MHz.
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A D S 1 2 3 1
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ELEC TRIC A L C HA RA C TERIS TIC S (con tin ue d )
Minimum/maximumlimit specifications apply from40C to +85C. Typical specifications at +25C.
All specifications at AVDD =DVDD =VREFP =+5V, V
CM
=2.5V and VREFN =GND, unless otherwise noted.
A D S 1 2 3 1
PA RA METER C OND ITIONS MIN TYP MA X UNIT
POWER S UPPLY
Power-supply voltage (AVDD, DVDD) 3 5.3 V
Normal mode, AVDD =3V 900 A
Normal mode, AVDD =5V 900 A
Analog supply current
Standby mode 0.1 A
Power-down 0.1 A
Normal mode, DVDD =3V 60 A
Normal mode, DVDD =5V 95 A
Digital supply current Standby mode, SCLK =high, DVDD =3V 45 A
Standby mode, SCLK =high, DVDD =5V 65 A
Power-down 0.2 A
Normal mode, AVDD =DVDD =3V 2.9 mW
Power dissipation, total
Normal mode, AVDD =DVDD =5V 5 mW
TEMPERA TURE
Operating temperature range 40 +85 C
Specified temperature range 40 +85 C
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Product Folder Links: ADS1231
DVDD
GND
CLKIN
SPEED
CAP
CAP
AINP
AINN
DRDY/DOUT
SCLK
PDWN
AVDD
SW
GND
VREFP
VREFN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A D S 1 2 3 1
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PIN C ONFIGURA TION
D PA C KA GE
S O- 1 6
(TOP VIEW)
PIN D ES C RIPTIONS
A NA LOG/D IGITA L
NA ME TERMINA L INPUT/OUTPUT D ES C RIPTION
DVDD 1 Digital Digital power supply
GND 2 Supply Ground for digital and analog supplies
CLKIN 3 Digital input External clock input: typically 4.9152MHz. Tie lowto activate internal oscillator.
Data rate select:
S PEED D A TA RA TE
SPEED 4 Digital input
0 10SPS
1 80SPS
CAP 5 Analog Gain amplifier bypass capacitor connection
CAP 6 Analog Gain amplifier bypass capacitor connection
AINP 7 Analog input Positive analog input
AINN 8 Analog input Negative analog input
VREFN 9 Analog input Negative reference input
VREFP 10 Analog input Positive reference input
GND 11 Supply Ground for digital and analog supplies
SW 12 Analog Low-side power switch
AVDD 13 Supply Analog power supply
PDWN 14 Digital input Power-down: holding this pin lowpowers down the entire converter and resets the ADC.
Serial clock: clock out data on the rising edge. Also used to initiate Standby mode. See the Standby
SCLK 15 Digital input
Mode section for more details.
Dual-purpose output:
DRDY/DOUT 16 Digital output Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the first rising edge of SCLK.
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A D S 1 2 3 1
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NOIS E PERFORMA NC E
The ADS1231 offers outstanding noise performance. Table 1 summarizes the typical noise performance with
inputs shorted externally for different data rates and voltage reference values.
The RMS and Peak-to-Peak noise are referred to the input. The effective number of bits (ENOB) is defined as:
ENOB =ln (FSR/RMS noise)/ln(2)
The Noise-Free Bits are defined as:
Noise-Free Bits =ln (FSR/Peak-to-Peak Noise)/ln(2)
Where:
FSR (Full-Scale Range) =V
REF
/Gain.
Ta bl e 1 . Nois e Pe r f or ma n ce
A VD D a n d V
REF
RMS NOIS E
(1 )
PEA K- TO- PEA K NOIS E
(1 )
ENOB
D A TA RA TE (V) (n V) (n V) (RMS ) NOIS E- FREE B ITS
5 35.2 231.9 20.1 17.4
10
3 33.5 199.2 19.4 16.8
5 102.1 622.1 18.5 15.9
80
3 80.3 549.6 18.2 15.4
(1) Noise specifications are based on direct measurement of 1024 consecutive samples.
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0
25
50
75
100
125
150
20 15 10 5 0 5 10 15 20
Input Voltage (mV)
R
M
S

N
o
i
s
e

(
n
V
)
Data Rate = 10SPS
0
25
50
75
100
125
150
20 15 10 5 0 5 10 15 20
Input Voltage (mV)
R
M
S

N
o
i
s
e

(
n
V
)
Data Rate = 80SPS
40353025201510 5 0 5 10 15 20 25 30 35 40
0
50
100
150
200
250
300
350
400
450
500
40353025201510 5 0 5 10 15 20 25 30 35 40
24bit LSBs
#

o
f

O
c
c
u
r
r
e
n
c
e
s
Data Rate = 10SPS
40353025201510 5 0 5 10 15 20 25 30 35 40
0
25
50
75
100
125
150
175
200
225
250
40353025201510 5 0 5 10 15 20 25 30 35 40
24bit LSBs
#

o
f

O
c
c
u
r
r
e
n
c
e
s
Data Rate = 80SPS
300
250
200
150
100
50
0
50
100
150
200
250
300
0 200 400 600 800 1000
Time (Reading Number)
C
o
n
v
e
r
s
i
o
n

D
a
t
a

(
n
V
)
Data Rate = 10SPS
300
250
200
150
100
50
0
50
100
150
200
250
300
0 200 400 600 800 1000
Time (Reading Number)
C
o
n
v
e
r
s
i
o
n

D
a
t
a

(
n
V
)
Data Rate = 80SPS
A D S 1 2 3 1
www.ti.com SBAS414D J ULY 2009 REVISED OCTOBER 2013
TYPIC A L C HA RA C TERIS TIC S
At T
A
=+25C, AVDD =DVDD =REFP =5V, REFN =GND, and V
CM
=2.5V unless otherwise noted.
NOIS E v s TIME NOIS E v s TIME
Fig ur e 1 . Fig ur e 2 .
NOIS E HIS TOGRA M NOIS E HIS TOGRA M
Fig ur e 3 . Fig ur e 4 .
NOIS E v s INPUT VOLTA GE NOIS E v s INPUT VOLTA GE
Fig ur e 5. Fig ur e 6.
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1200
1000
800
600
400
200
0
85 60 35 22.5 10 -2.5 -40
A
n
a
l
o
g

S
u
p
p
l
y

C
u
r
r
e
n
t

(
A
)
m
Temperature ( C)
-15 -27.5 72.5 47.5
120
115
110
105
100
95
90
85
80
85 60 35 22.5 10 -2.5 -40
D
i
g
i
t
a
l

S
u
p
p
l
y

C
u
r
r
e
n
t

(
A
)
m
Temperature ( C)
-15 -27.5 72.5 47.5
9.8
9.85
9.9
9.95
10
10.05
10.1
10.15
10.2
40 27.5 15 2.5 10 22.5 35 47.5 60 72.5 85
Temperature (C)
D
a
t
a

R
a
t
e

(
S
P
S
)
Data Rate = 10SPS
3
2
1
0
1
2
3
4
5
6
7
-
-
-
-
-
-
-
20 10 5 0 -5 -20
I
n
t
e
g
r
a
l

N
o
n
l
i
n
e
a
r
i
t
y

(
p
p
m
)
Input Voltage (mV)
-10 -15 15
- 20 C
-40 C
+25 C
+70 C
2000
1500
1000
500
0
500
1000
1500
2000
-
-
-
-
85 60 35 22.5 10 -2.5 -40
O
f
f
s
e
t

(
n
V
)
Temperature ( C)
-15 -27.5 72.5 47.5
0.02
0.015
0.01
0.005
0
0.005
0.01
0.015
0.02
-
-
-
-
85 60 35 22.5 10 -2.5 -40
G
a
i
n

E
r
r
o
r

(
%
)
Temperature ( C)
-15 -27.5 72.5 47.5
A D S 1 2 3 1
SBAS414D J ULY 2009 REVISED OCTOBER 2013 www.ti.com
TYPIC A L C HA RA C TERIS TIC S (con tin ue d )
At T
A
=+25C, AVDD =DVDD =REFP =5V, REFN =GND, and V
CM
=2.5V unless otherwise noted.
OFFS ET D RIFT v s TEMPERA TURE GA IN ERROR v s TEMPERA TURE
Fig ur e 7. Fig ur e 8.
INL v s INPUT VOLTA GE D A TA RA TE v s TEMPERA TURE
Fig ur e 9. Fig ur e 1 0.
A NA LOG S UPPLY C URRENT v s TEMPERA TURE D IGITA L S UPPLY C URRENT v s TEMPERA TURE
Fig ur e 1 1 . Fig ur e 1 2 .
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Product Folder Links: ADS1231
R
INT
R
INT
R
F1
R
1
R
F2
ADC A3
Gain = 1
CAP
AINP
CAP
A2
A1
AINN
EMI
Filter
EMI
Filter
AVDD
Z = 500MW
EFF
VREFP VREFN
AVDD
ESD
Protection
C
BUF
Z = 500MW
EFF
A D S 1 2 3 1
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OVERVIEW
The ADS1231 is a precision, 24-bit ADC that includes
a low-noise PGA, internal oscillator, third-order delta- Exte r n a l C a pa citor
sigma () modulator, and fourth-order digital filter.
An external capacitor (C
EXT
) across the two ADS1231
The ADS1231 provides a complete front-end solution
CAP pins combines with the internal resistor R
INT
(on-
for bridge sensor applications such as weigh scales,
chip) to create a low-pass filter. The recommended
strain gauges, and pressure sensors.
value for C
EXT
is 0.1F which provides a corner
Data can be output at 10SPS for excellent 50Hz and frequency of 720Hz. This low-pass filter serves two
60Hz rejection, or at 80SPS when higher speeds are purposes. First, the input signal is band-limited to
needed. The ADS1231 is easy to configure, and all prevent aliasing by the ADC and to filter out the high-
digital control is accomplished through dedicated frequency noise. Second, it attenuates the chopping
pins; there are no registers to program. A simple two- residue fromthe amplifier to improve temperature drift
wire serial interface retrieves the data. performance. NPO or C0G capacitors are
recommended. For optimal performance, place the
external capacitor very close to the CAP pins. A NA LOG INPUTS (A INP, A INN)
The input signal to be measured is applied to the
VOLTA GE REFERENC E INPUTS
input pins AINP and AINN. The ADS1231 accepts
(VREFP, VREFN)
differential input signals, but can also measure
unipolar signals. The voltage reference used by the modulator is
generated from the voltage difference between
VREFP and VREFN: V
REF
=VREFP VREFN. The LOW- NOIS E A MPLIFIER
reference inputs use a structure similar to that of the
The ADS1231 features a low-drift, low-noise amplifier
analog inputs. In order to increase the reference input
that provides a complete front-end solution for bridge
impedance, switching buffer circuitry is used to
sensors. A simplified diagram of the amplifier is
reduce the input equivalent capacitance. The
shown in Figure 13. It consists of two chopper-
reference drift and noise impact ADC performance. In
stabilized amplifiers (A1 and A2) and three accurately
order to achieve best results, pay close attention to
matched resistors (R
1
, R
F1
, and R
F2
) that construct a
the reference noise and drift specifications. A
differential front-end stage with a gain of 128,
simplified diagram of the circuitry on the reference
followed by gain stage A3 (Gain =1). The inputs are
inputs is shown in Figure 14. The switches and
equipped with an EMI filter, as shown in Figure 13.
capacitors can be modeled approximately using an
The cutoff frequency of the EMI filter is 20MHz. By
effective impedance of .
using AVDD as the reference input, the bipolar input
ranges from19.5mV to +19.5mV. The inputs of the
ADS1231 are protected with internal diodes
connected to the power-supply rails. These diodes
clamp the applied signal to prevent it fromdamaging
the input circuitry.
Fig ur e 1 4 . S impl if ie d Re f e r e n ce In put C ir cuitr y
ESD diodes protect the reference inputs. To prevent
these diodes fromturning on, make sure the voltages
on the reference pins do not go below GND by more
than 100mV, and likewise, do not exceed AVDD by
100mV:
GND 100mV < (VREFP or VREFN) < AVDD +
Fig ur e 1 3 . S impl if ie d D ia g r a m of the A mpl if ie r 100mV
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Bridge
Sensor
+VDD
AINP
AINN
VREFN
SW
GND
ADS1231
VREFP
CLK_DETECT
Internal
Oscillator
MUX
To ADC
S
S0 S1
EN
CLKIN
A D S 1 2 3 1
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LOW- S ID E POWER S WITC H (S W) C LOC K S OURC E
The ADS1231 incorporates an internal switch for use The ADS1231 can use the internal oscillator or an
with an external bridge sensor, as shown in external clock source to accommodate a wide variety
Figure 15. The switch can be used in a return path for of applications. Figure 16 shows the equivalent
the bridge power. By opening the switch, power circuitry of the clock module. The CLK_DETECT
dissipation in the bridge is eliminated. block determines whether an external clock signal is
applied to the CLKIN pin so that the internal oscillator
The switch is controlled by the ADS1231 conversion
is bypassed or activated. When the CLKIN pin
status. During normal conversions, the switch is
frequency is above ~200kHz, the CLK_DETECT
closed (the SW pin is connected to GND). During
circuit shuts down the internal oscillator and passes
standby or power-down modes, the switch is opened
the external clock signal to the ADC. When the
(the SW pin is high impedance). When using the
CLKIN pin frequency is below ~200kHz, the
switch, it is recommended that the negative reference
CLK_DETECT block activates the internal oscillator.
input (VREFN) be connected directly to the bridge
When the internal oscillator is chosen, make sure to
ground terminal, as shown in Figure 15 for best
connect the CLKIN pin to GND.
performance.
Fig ur e 1 6. Equiv a l e n t C ir cuitr y of the C l ock
S our ce
The allowable frequency range for the external clock
signal f
CLKIN
is specified in the Electrical
Characteristics table.
Fig ur e 1 5. Low- S id e Powe r S witch
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Frequency (Hz)
G
a
i
n

(
d
B
)
0
-50
-100
-150
0 10 20 30 40 50 60 70 80 90 100
(a)
Frequency (Hz)
(b)
G
a
i
n

(
d
B
)
-50
-100
-150
49 48 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Data Rate = 10SPS
Data Rate = 10SPS
A D S 1 2 3 1
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FREQUENC Y RES PONS E
The ADS1231 uses a sinc
4
digital filter with the
frequency response shown in Figure 17 for f
CLKIN
=
4.9152MHz. The frequency response repeats at
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a 3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
To help see the response at lower frequencies,
Figure 17(a) illustrates the nominal response out to
100Hz, when the data rate = 10SPS. Notice that
signals at multiples of 10Hz are rejected, and
therefore simultaneous rejection of 50Hz and 60Hz is
achieved.
The benefit of using a sinc
4
filter is that every
frequency notch has four zeros on the same location,
thus providing excellent normal-mode rejection of
line-cycle interference.
Figure 17(b) zooms in on the 50Hz and 60Hz notches
with the SPEED pin tied low(10SPS data rate).
The ADS1231 data rate and frequency response
scale directly with clock frequency. For example, if
f
CLKIN
increases from4.9152MHz to 5.5296MHz when
the SPEED pin is tied high, the data rate increases
from80SPS to 90SPS, while the notch also increases
from80Hz to 90Hz. Note that these changes are only
possible when an external clock source is applied.
Fig ur e 1 7. Nomin a l Fr e que n cy Re s pon s e Out To
1 00Hz
Copyright 20092013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: ADS1231
Abrupt Change in External V
IN
V
IN
DRDY/DOUT
Start of
Conversion
Conversion
including
unsettled V .
IN
1st Conversion;
V settled, but
digital filter
unsettled.
IN
2nd Conversion;
V settled, but
digital filter
unsettled.
IN
3rd Conversion;
V settled, but
digital filter
unsettled.
IN
4th Conversion;
V settled, but
digital filter
unsettled.
IN
Conversion
Time
A D S 1 2 3 1
SBAS414D J ULY 2009 REVISED OCTOBER 2013 www.ti.com
Ta bl e 2 . D a ta Ra te S e ttin g s S ETTLING TIME
D A TA RA TE
Fast changes in the input signal require time to settle.
S PEED PIN In te r n a l Os cil l a tor Exte r n a l C l ock For example, an external multiplexer in front of the
ADS1231 can generate abrupt changes in input 0 10SPS f
CLKIN
/ 491,520
voltage by simply switching the multiplexer input
1 80SPS f
CLKIN
/ 61,440
channels. These sorts of changes in the input require
four data conversion cycles to settle. When
D A TA FORMA T
continuously converting, five readings may be
necessary in order to settle the data. If the change in The ADS1231 outputs 24 bits of data in binary twos
input occurs in the middle of the first conversion, four complement format. The least significant bit (LSB)
more full conversions of the fully-settled input are has a weight of (0.5V
REF
/128)(2
23
1). The positive
required to obtain fully-settled data. Discard the first full-scale input produces an output code of 7FFFFFh
four readings because they contain only partially- and the negative full-scale input produces an output
settled data. Figure 18 illustrates the settling time for code of 800000h. The output clips at these codes for
the ADS1231. signals exceeding full-scale. Table 3 summarizes the
ideal output codes for different input signals.
D A TA RA TE
Ta bl e 3 . Id e a l Output C od e v s In put S ig n a l
The ADS1231 data rate is set by the SPEED pin, as
INPUT S IGNA L V
IN shown in Table 2. When SPEED is low, the data rate
(A INP A INN) ID EA L OUTPUT
is nominally 10SPS. This data rate provides the
+0.5V
REF
/128 7FFFFFh
lowest noise, and also has excellent rejection of both
000001h (+0.5V
REF
/128)/(2
23
1) 50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED 0 000000h
high selects a data rate of nominally 80SPS.
FFFFFFh (0.5V
REF
/128)/(2
23
1)
0.5V
REF
/128 800000h
1. Excludes effects of noise, INL, offset, and gain
errors.
Fig ur e 1 8. S e ttl in g Time in C on tin uous C on v e r s ion Mod e
12 Submit Documentation Feedback Copyright 20092013, Texas Instruments Incorporated
Product Folder Links: ADS1231
DRDY/DOUT 23 22 21
1 24
0
LSB MSB
Data
Data Ready
SCLK
t
DS
t
CONV
t
SCLK
t
PD
New Data Ready
t
SCLK
t
HT
t
UPDATE
A D S 1 2 3 1
www.ti.com SBAS414D J ULY 2009 REVISED OCTOBER 2013
D A TA REA D Y/D A TA OUTPUT (D RD Y/D OUT) D A TA RETRIEVA L
This digital output pin serves two purposes. First, it The ADS1231 continuously converts the analog input
indicates when new data are ready by going low. signal. To retrieve data, wait until DRDY/DOUT goes
Afterwards, on the first rising edge of SCLK, the low, as shown in Figure 19. After DRDY/DOUT goes
DRDY/DOUT pin changes function and begins low, begin shifting out the data by applying SCLKs.
outputting the conversion data, most significant bit Data are shifted out MSB first. It is not required to
(MSB) first. Data are shifted out on each subsequent shift out all 24 bits of data, but the data must be
SCLK rising edge. After all 24 bits have been retrieved before new data are updated (within t
CONV
)
retrieved, the pin can be forced high with an or else the data will be overwritten. Avoid data
additional SCLK. It then stays high until newdata are retrieval during the update period (t
UPDATE
). If only 24
ready. This configuration is useful when polling on the SCLKs have been applied, DRDY/DOUT remains at
status of DRDY/DOUT to determine when to begin the state of the last bit shifted out until it is taken high
data retrieval. (see t
UPDATE
), indicating that new data are being
updated. To avoid having DRDY/DOUT remain in the
state of the last bit, the 25th SCLK can be applied to S ERIA L C LOC K INPUT (S C LK)
force DRDY/DOUT high, as shown in Figure 20. This
This digital input shifts serial data out with each rising
technique is useful when a host controlling the device
edge. This input has built-in hysteresis, but care
is polling DRDY/DOUT to determine when data are
should still be taken to ensure a clean signal. Glitches
ready.
or slow-rising signals can cause unwanted additional
shifting. For this reason, it is best to make sure the
rise and fall times of SCLK are both less than 50ns.
Fig ur e 1 9. 2 4 - B it D a ta Re tr ie v a l Timin g
S YMB OL D ES C RIPTION MIN TYP MA X UNITS
t
DS
DRDY/DOUT lowto first SCLK rising edge 0 ns
t
SCLK
SCLK positive or negative pulse width 100 ns
t
PD
(1)
SCLK rising edge to newdata bit valid: propagation delay 50 ns
t
HT
(1)
SCLK rising edge to old data bit valid: hold time 20 ns
t
UPDATE
Data updating: no readback allowed 90 s
SPEED =1 12.5 ms
t
CONV
Conversion time (1/data rate)
SPEED =0 100 ms
(1) Minimumrequired fromsimulation.
Copyright 20092013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: ADS1231
DRDY/DOUT 23 22 21
1 24
0 23
SCLK
Standby Mode
Data Ready
t
DSS
t
STANDBY
t
S_RDY
Start Conversion
23
1 24 25
22 21 0
Data
25th SCLK to Force /DOUT High DRDY
Data Ready New Data Ready
DRDY/DOUT
SCLK
A D S 1 2 3 1
SBAS414D J ULY 2009 REVISED OCTOBER 2013 www.ti.com
S TA ND B Y MOD E
When t
STANDBY
has passed with SCLK held high,
Standby mode dramatically reduces power Standby mode activates. DRDY/DOUT stays high
consumption by shutting down most of the circuitry. when Standby mode begins. SCLK must remain high
To enter Standby mode, simply hold SCLK high after to stay in Standby mode. To exit Standby mode
DRDY/DOUT goes low; see Figure 21. Standby mode (wake up), set SCLK low. The first data after exiting
can be initiated at any time during readback; it is not Standby mode are valid.
necessary to retrieve all 24 bits of data beforehand.
Fig ur e 2 0. D a ta Re tr ie v a l with D RD Y/D OUT For ce d Hig h A f te r wa r d s
Fig ur e 2 1 . S ta n d by Mod e Timin g (C a n be us e d f or s in g l e con v e r s ion s )
S YMB OL D ES C RIPTION MIN TYP MA X UNITS
SCLK high after DRDY/DOUT SPEED =1 12.44 ms
t
DSS
(1)
goes lowto activate Standby
SPEED =0 99.94 ms
mode
SPEED =1 12.5 ms
t
STANDBY
Standby mode activation time
SPEED =0 100 ms
SPEED =1 52.6 ms
Data ready after exiting Standby
t
S_RDY
(1)
mode
SPEED =0 401.8 ms
(1) Based on an ideal internal oscillator.
14 Submit Documentation Feedback Copyright 20092013, Texas Instruments Incorporated
Product Folder Links: ADS1231
Data Ready
Start
Conversion
DRDY/DOUT
SCLK
CLK Source
Wakeup
Power-Down Mode
PDWN
t
WAKEUP
t
TS_RDY
t
PDWN
AVDD
DVDD
PDWN
m 10 s
A D S 1 2 3 1
www.ti.com SBAS414D J ULY 2009 REVISED OCTOBER 2013
POWER- D OWN MOD E
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry. Power-Down mode can be
initiated at any time during readback; it is not
necessary to retrieve all 24 bits of data beforehand. Fig ur e 2 2 . Powe r - Up Timin g S e que n ce
Figure 23 shows the wake-up timing from Power-
Down mode.
Fig ur e 2 3 . Wa ke - Up Timin g f r om Powe r - D own Mod e
S YMB OL D ES C RIPTION MIN TYP UNITS
t
WAKEUP
(1)(2)
Wake-up time after Power-Down mode 7.95 s
t
PDWN
(1)
PDWN pulse width 26 s
(1) Based on an ideal internal oscillator.
(2) Typical required fromsimulation.
Copyright 20092013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ADS1231
ADS1231
10
5
6
7
8
12
16
15
14
4
VREFP
CAP
CAP
AINP
AINN
SW
AVDD DVDD
GND
DRDY/DOUT
SCLK
PDWN
SPEED
1 F m
(1)
0.1 F m
(2)
+ -
2, 11
13 1
MSP430x4xx
VDD
GND
3V to 5.3V 3V
1 F m
(1)
9
VREFN
Load
Cell
3
CLKIN
A D S 1 2 3 1
SBAS414D J ULY 2009 REVISED OCTOBER 2013 www.ti.com
A PPLIC A TION EXA MPLE
We ig h S ca l e S ys te m
Figure 24 shows a typical ADS1231 application as part of a weigh scale system.
(1) Place a 0.1F or higher capacitor as close as possible on both AVDD and DVDD.
(2) Place capacitor very close to the ADS1231 CAP pins for optimal performance.
Fig ur e 2 4 . We ig h S ca l e Exa mpl e
16 Submit Documentation Feedback Copyright 20092013, Texas Instruments Incorporated
Product Folder Links: ADS1231
A D S 1 2 3 1
www.ti.com SBAS414D J ULY 2009 REVISED OCTOBER 2013
REVIS ION HIS TORY
NOTE: Page numbers for previous revisions may differ frompage numbers in the current version.
C ha n g e s f r om Re v is ion C (D e ce mbe r 2 01 0) to Re v is ion D Pa g e
Changed "oscillator" to "clock" in data rate parameter of electrical characteristics .............................................................. 3
Changed all "f
CLK
" to "f
CLKIN
" throughout data sheet ............................................................................................................. 3
Deleted extra space in data rate parameter typical value (typo) .......................................................................................... 3
Changed "oscillator" to "clock" in data rate parameter of electrical characteristics .............................................................. 3
Deleted extra space in data rate parameter typical value (typo) .......................................................................................... 3
Changed location of noise parameter ................................................................................................................................... 3
Changed "oscillator" to "clock" in normal-mode rejection parameter of electrical characteristics ........................................ 3
Changed "AGND" to "GND" in negative reference input parameter min value .................................................................... 3
Added newexternal clock input frequency parameter .......................................................................................................... 3
Changed "oscillator" to "f
CLKIN
" in note 2 of electrical characteristics ................................................................................... 3
Changed pin 12 name fromPSW to SW in pinout drawing ................................................................................................. 5
Changed pin 12 name fromPSW to SW in Pin Descriptions table ...................................................................................... 5
Changed title of Figure 5 ...................................................................................................................................................... 7
Changed title of Figure 6 ...................................................................................................................................................... 7
Changed plot title and X-axis label of Figure 9 ..................................................................................................................... 8
Changed plot title and Y-axis label of Figure 11 ................................................................................................................... 8
Changed plot title and Y-axis label of Figure 12 ................................................................................................................... 8
Changed Clock Source section .......................................................................................................................................... 10
Added text to first sentence of Frequency Response section ............................................................................................ 11
Changed third paragraph of Frequency Response section ................................................................................................ 11
Added newtext to end of Frequency Response section .................................................................................................... 11
Changed Table 2 ................................................................................................................................................................ 12
Changed pin numbers in Figure 24 to match the device pinout and added missing CLKIN pin ........................................ 16
Copyright 20092013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADS1231
PACKAGE OPTION ADDENDUM
www.ti.com 9-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Device Marking
(4/5)
Samples
ADS1231ID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1231
ADS1231IDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS1231

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
ADS1231IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1231IDR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2013
Pack Materials-Page 2
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