Watchdog Timer on the PIC18F4525

by Dan Peirce B.Sc.

July 2, 2008
The PIC18 devices contain a Watchdog timer. A watchdog timer is typically used to
improve system reliability. The main loop of the embedded system program will contain a
statement intended to reset the timer. If the reset does not occur the watchdog timer will
eventually time out and force the processor to reset. This is intended to bring theMCU into
a known condition if something has prevented normal program execution and is much like
resetting a PC when it hangs (except it is automatic and can be programmed to happen in
short time frames in the order of milliseconds or 10s of milliseconds).
Configuration bits must be set when the PIC is programmed in order to enable the
watchdog timer and set the postscaller.
example directives to set the watchdog timer on with the postscaller set
to 1:8
#pragma config WDT = ON
#pragma config WDTPS = 8
More on #pragma directives can be found at Embedded systems and Pragma statements.
In a project I set up for testing the watchdog timer in isolation I put the directive shown
above into the com_port.c file. The project is in the file wdt_1.zip .
The PIC18F4525 has an internal oscillator block that contains an 8 MHz source and a 31
KHz source (INTRC).
The datasheet says the WDT period is 4 ms. Using the internal watchdog timer
oscillator a 1:1 postscaller results in a 4 ms timeout period (128 * 1/31000 = 4.13
ms ).


Setting the postscaller to 1:8 results in a 33 ms. The image below shows the
simulated time for the watchdog timer to timeout.


Simulated output when the ClrWdt() macro is commented out of the main loop. Note that
at 9600 bps it takes about 2 ms to send a 0 and a comma out the USART.

When the ClrWdt() macro is put back in the timeouts do not occur.

To get the simulation working correctly the Break Options under simulator settings should
be changed to match the screen shot shown below.


23.2 Watchdog Timer (WDT)
page
256
PIC18F4525 datasheet
Reset Control Register page 42 PIC18F4525 datasheet
CONFIG2H: CONFIGURATION
REGISTER 2 HIGH
page
252
PIC18F4525 datasheet
ClrWdt() Instruction Macro page 35
MPlab C18 C Compiler User's
Guide
isWDTTO() function
page
145
MPlab C18 C Compiler
Libraries
isPOR() function
page
145
MPlab C18 C Compiler
Libraries
StatusReset() function
page
146
MPlab C18 C Compiler
Libraries
28.3 Watchdog Timer (WDT) Operation
page
28-4
PICmicro 18C Family
Reference Manual
There are flags set within the processor that indicate different possible causes of a system
reset. For example there is a power on reset flag that indicates a rising edge has been
detected on the power pins. There is also a flag to indicate that the watchdog timer has
timed out.
For power saving modes it is possible to shut down the 8 MHz source while keeping the 31
KHz source running as the source clock for the watchdog timer. The watchdog timer can be
used to periodically wake up the processor.