1

Dr. Navakanta Bhat

E3-238 : Analog VLSI Circuits
Dr. NavakantaBhat
Associate Professor, ECE Department
Indian Institute of Science, Bangalore-560012
Email: navakant@ece.iisc.ernet.in
URL: http://ece.iisc.ernet.in/~navakant
August 2007
Lecture # 1
2
Dr. Navakanta Bhat
Logistics
Instructors : NavakantaBhat, SundarajanKrishnan, Srinivasan
Teaching Assistants : RakeshGnanaDavid, ManodeepanSahu
Class timings : Friday 8:00am-9:00am
Saturday 9:00am-11:00am
Lab session :
Involves circuit design, simulation and analysis
using any circuit simulator (Spice3f5, WinSpice,
T-Spice, P-Spice, H-Spice, Spectre, Eldo)
Grading :
Home work (lab assignments) : 20%
Mid term exam : 20 %
Course project : 20 %
Final exam : 40%
3
Dr. Navakanta Bhat
List of Reference books
Due to the advent of mixed signal SOCs, numerous books
have been published on Analog Design. A partial list :
1. Analog CMOS Design
Razavi, McGraw Hill Publication
2. CMOS: Circuit Design, Layout , and Simulation
Boise, Baker, Lee, Prentice Hall Publication
3. Analog VLSI : Signal and Information Processing
Ismail and Feiz, McGraw Hill Publication
4. Analysis and Design of Analog Integrated Circuits
Gray and Meyer, Wiley Publication
5. Trade-offs in Analog Circuit Design: The Designers
Companion, Ed: C. Toumazou and other, Kluwer
4
Dr. Navakanta Bhat
Course details
Review of Bode plots; Stability of feedback systems; location of nondominant
poles for stability; J udging stability from magnitude and phase plots;
Y-parameter two port amplifier constraints on small signal y parameters to
realize gain - MOS Transistor Characteristics Derivation of the common source
amplifier with biasing and swing limits. Several variants of biasing : current
source in the source, feedback from drain to gate, current mirror, use of an opamp
for biasing
Review of linear networks. Nonlinear networks and notion of incremental
linearity. Small signal linear equivalents of nonlinear one and two port networks.
Concept of negative feedback; Ideal opamp feedback circuits; Introduce idea of
nullator/norator ; Real opamp feedback circuits-effect of finite A0, wu
SPICE simulator, Transistor models, BSIM3 models, Model extraction, Models for
: Vt, I-V, Capacitance, Substrate current, S/D parasitics, Temp dependence,
NQS effect, Noise, RF Modeling, Gate leakage
Logistics, Technology trend, Need for Analog design, Simple longchannel
MOSFET theory, Sub-micron transistor theory, SCE, NWE, DIBL, Sub-threshold
conduction, Reliability, Digital metrics, Analog metrics
5
Dr. Navakanta Bhat
Course details
Differential pair, small and large signal analysis; Concept of common mode
rejection
Effect of Random mismatch in integrated circuits
Frequency response of the basic amplifier configurations, Ft of transistor;
Common source amplifier response with varying Cgd-show miller
multiplication, pole splitting
Introduce bipolar transistor as another candidate device, run through all the
above with BJ Ts. Illustrate poweradvantage of Bipolar vs MOS
Derive the other controlled sources VCVS (Common drain), CCCS (Common
Gate), CCVS (Transimpedance Amp), VCCS (Transconductor)., multi-stage
amplifiers
6
Dr. Navakanta Bhat
Course details
Bandgapreferences
Passives in Analog Circuits
Single-stage differential op-amp with common-mode feedback
Current mirrors: Cascode, Nagativefeedback, Wilson, Regulated cascode,
Layout issues
Two-stage differential amplifiers with various types of compensation
(dominant pole, miller, pole-zero)
Two-stage differential amplifiers with various types of compensation
(dominant pole, miller, pole-zero)-pole splitting, effect of RHP zero, zero
cancellation
Differential to Single-Ended Conversion: Use of active loads leading to the
5-transistor single-stage opamp; also introduce slewing in more detail -->
extend to gain enhancement techniques like cascodes, telescopic cascodes;
7
Dr. Navakanta Bhat
Why Analog ?
Interaction with the Physical World
Computing
Platform
Physical
Environment
Physical
Environment
Input Output
Sensing Actuation
Human perception is inherently analog in nature
8
Dr. Navakanta Bhat
Why Analog ?
An Interesting Comparison
Neural networks outperform the digital computers, in certain class
of applications such as speech recognition, pattern recognition
The architecture and massive parallelism are distinguishing features
Analog (Adaptive learning) Digital (RISC/CISC ) Architecture
~ 1 Trillion ~1 Billion Integration
2m/sec 10
8
m/sec Wire / Fibre
100mS 1ps Transistor /
Neuron
Biological Neural System CMOS Digital Computer
9
Dr. Navakanta Bhat
The First IC : 1958
First IC demonstrated by J .S.Kilbyof Texas Instruments in 1958
First IC using planar process and photolithography was demonstrated by Robert Noyce at Fairchild semiconductors
Phase shift oscillator, an analog circuit!
A thin slice of germanium with
1 bipolar transistor (under the large bar of
aluminum in the center),
1 capacitor,
3 resistors (the germanium functioned as its
own so-called bulk resistor)
4 input/output terminals (the small vertical
aluminum bars)
ground pad (the large bar on the far right),
and wires of gold.
Connected together with wax
Actual size: 0.040 x 0.062 inches
Blue tinge was created by a light shown on the chip.
10
Dr. Navakanta Bhat
Metal Oxide Semiconductor Field Effect
Transistor (MOSFET)
Field effect transistor concept proposed in 1930s by Lilienfeld
First MOSFET fabricated in 1960 by Kahngand Atalla
oxide
metal
Silicon
p+ p+
n
PMOSFET
oxide
metal
Silicon
n+ n+
p
NMOSFET
Early MOS technology was based on PMOSFETs
MOSFETS were thought to be unfriendly for Analog circuits!
11
Dr. Navakanta Bhat
CMOS Technology Today (2007)
65nm digital technology in volume production
Technology scaling for future is more challenging and expensive
State of the art fabset-up costs more than US$2 billion
Recovering the fabcost requires a modular process technology
approach capable of producing diverse products
Number of transistors per chip is ~1 billion( DRAMs),
~100 million (microprocessors)
What do we do with the technology capable of making
millions of transistor on a tiny area in Si? :
Mixed Signal Systems On Chip (SOC)
12
Dr. Navakanta Bhat
BJ T versus MOSFET speed
p
p
p
n-
p
n+
oxide
metal
Silicon
n+ n+
p
Base width defined by
diffusion process
Channel length defined by
Photolythographyprocess
Historically BJ T used to be faster than MOSFET
CMOS scaling has brought MOSFET on par with BJ T
13
Dr. Navakanta Bhat
Cut-off frequency, f
T
MOSFET f
T
has increased considerably with scaling
Cut-off frequency trend
0
20
40
60
80
100
120
0 0.2 0.4 0.6 0.8 1 1.2
Channel length
f
t
ft
14
Dr. Navakanta Bhat
Analog Design on Digital Technology
Microprocessors are todays technology drivers
The most elegant analog designs make use of the
existing digital technology
Every modification to the baseline technology adds on
to the manufacturing cost
Design For Manufacturability (DFM)
CMOS analog circuits are logical choice
15
Dr. Navakanta Bhat
Long channel MOSFET Theory
16
Dr. Navakanta Bhat
Transistor abstraction
schematic switch model
n+ n+
Si
cross section
gate
P-well
G
D
S
B
lay out
A
A
17
Dr. Navakanta Bhat
Simple 3-D picture of MOSFET
Lg = Length of the gate
Wg = Width of the gate
The 2 important dimensional parameters of MOSFET
under circuit designers control are:
n+ gate
Oxide
n+ source n+ drain
p substrate
Lg
Wg
Tox
x
j
Doping concentration =Na
18
Dr. Navakanta Bhat
Simple MOS Theory
Vgs < Vt, MOSFET is in cut off region
Vgs > Vt, Vds < Vgs-Vt, MOSFET is in linear region
Vgs > Vt, Vds > Vgs-Vt, MOSFET is in saturation region
where is mobility,
ox
is permittivity of the oxide,
and Vt is the threshold voltage of the MOSFET
( )
2
2
Vt Vgs
L T
W
Ids
ox
ox

=

( )

=
2
2
Vds
Vds Vt Vgs
L T
W
Ids
ox
ox

Ids = 0
ox
b a s ox
b fb t
qN T
V V

4
2 + + =
19
Dr. Navakanta Bhat
I-V characteristics
Ids
Vds
Vg1
Vg2
Vg3
Ids is constant and independent of Vdsin saturation
Vgs
Ids
Linear
Vds~0.1V
Saturation
Vds=Vdd
Output Characteristics Transfer Characteristics
Ids is zero in sub-threshold region
Both of these idealities are incorrect especially for
the sub-micron MOS transistor
20
Dr. Navakanta Bhat
Channel length modulation
p-substrate
n+drain
n+source
Vg >Vt Vd>Vg - Vt
electron channel
L
Effective channel length is Leff = L - L, where L=f(Vds)
Ids increases slightly in saturation region with increasing Vds
( )
2
2
Vt Vgs
L T
W
I
eff ox
ox
ds

=

This limits the AC output resistance for analog applications
Vds
Ids
Vds=Vgs-Vt
ds
ds
out
I
V
R

=
( )
( )
ds
ox
ox
ds
V
Vt Vgs
L T
W
I

= 1
2
2
is channel length modulation parameter in SPICE
21
Dr. Navakanta Bhat
Body effect
Vt increases due to body effect
= body effect factor ( = 0.3-0.7)
Vs
n+
Vbs
Vg
n+
Vd
ox
b a s ox
b fb t
qN T
V V

4
2
0
+ + =
( )
b b bs t t
V V V 2 2
0
+ + =
ox
a s ox
N q T

2
=
This results in a transconductanceterm
p-substrate
22
Dr. Navakanta Bhat
The Sub-micron MOS Transistor for
Analog Design
Sub-micron transistor theory, SCE, NWE, DIBL, Sub-threshold conduction,
Digital metrics, Analog metrics
23
Dr. Navakanta Bhat
Constant field scaling
Primary scaling factors:
Tox, L, W, Xj (all linear dimensions) 1/K
Na, Nd(doping concentration) K
Vdd(supply voltage) 1/K
Derived scaling behavior of transistor:
Electric field 1
Ids 1/K
Capacitance 1/K
Derived scaling behavior of circuit:
Delay (CV/I) 1/K
Power (VI) 1/K
2
Power-delay product 1/K
3
Circuit density ( 1/A) K
2
Technology scaling
Scaling factor K >1
SCALING IS DRIVEN BY DIGITAL CIRCUIT REQUIREMENTS
24
Dr. Navakanta Bhat
Short Channel Effect (SCE)
p-substrate
n+
n+
depletion
depletion
Fraction of the depletion charge (Qdin Vt equation) is supported
by the source and drain junctions and hence Vg need not support this
When L is very small (~1m) this charge becomes significant
fraction of the total depletion charge and can not be neglected
=> Vt decreases with decreasing L
L (m)
Vt
~1m
L
Vg
Impacts matching of transistors in analog applications
25
Dr. Navakanta Bhat
Reverse Short Channel Effect
Vt
L
ve
dL
dV
t
+ =
ve
dL
dV
t
=
Invariably exists in almost all the sub-micron technologies
The techniques used to suppress SCE are responsible for RSCE
Vt becomes very sensitive function of L
26
Dr. Navakanta Bhat
Drain Induced Barrier Lowering (DIBL)
Vds=Vdd
Vds=0.1V
L
Vt
Vs
n+
Vg
n+
Vd
Vt is also a function of drain voltage in sub-micron transistors
DIBL effect is negligible in the long channel regime
Potential barrier
Vds=Vdd
Vds=0.1V
27
Dr. Navakanta Bhat
Narrow Width Effect
W (m)
Vt
~1m
Additional depletion charge at the edge of source & drain should
be supported by the Vg before inverting the channel
When W is very small (~1m) this charge becomes significant
fraction of the total depletion charge and can not be neglected
=> Vt increases with decreasing W
p-substrate
n+
depletion
W
Vg
28
Dr. Navakanta Bhat
Sub threshold conduction
For Vg < Vt, current is non zero and is exponential function of Vg
Log Ids
Vgs
Vt
The inverse slope
of this line is S, the
sub threshold slope
(S~80-100mV/decade)
S = 2.3kT/q (1 + Csi/Cox) mV/decade
Csi=depletion capacitance in Si, Cox=oxide capacitance,kT/q=thermal voltage
MOSFET should be designed to have minimum possible S
Sub threshold analog circuits work below Vt
S
G
D
29
Dr. Navakanta Bhat
Velocity saturation
For velocity saturated transistor, the saturation drive current is
E
10
7
cm/sec at T=300
o
K
~10
4
V/cm
v
v = E valid only at low
electric fields (E)
Ids (Vgs-Vt)
2
Ids
Vds
Ids (Vgs-Vt)
Ids will be less than expected
due to velocity saturation
For L=0.1m transistor operating at Vd=1V:
E=10
5
V/cm => transistor is velocity saturated
Transconductancewill be independent of L
ox
sat t gs
T
v V V W
Ids
) (
=

30
Dr. Navakanta Bhat
Transistor design methodology for Digital Technology
Design parameters:
L, Vdd, Tox, N, Xj
S/D engineering
Channel engineering
Circuit characteristics:
Delay (Vt/Vdd)
Active power (Vdd)
Standby power (Vt)
Hot carrier reliability
Vdd, L, N
Gate oxide reliability
Vdd, Tox
System compatibility
Vdd
31
Dr. Navakanta Bhat
Vt-Vdddesign plane
Normalized delay
Vt/Vdd 0.4
Delay increases significantly for Vt/Vdd> 0.4
Pactive(Pac) = CV
dd
2
f
Pstandby(Psb) = WV
dd
I
off
Vt
Vdd
Psb
Pac
Delay
Delay and Power are the only trade-off points for digital design
32
Dr. Navakanta Bhat
Analog Circuit Performance Metrics
The Analog Octagon:
Multiple trade-offs involved in Analog Design make it very interesting
B. Razavi
NOISE
POWER
SPEED
GAIN
SUPPLY VOLTAGE
LINEARITY
VOLTAGE SWINGS
I/O IMPEDANCE
33
Dr. Navakanta Bhat
Summary
Scaling is driven by digital technology
Analog design is indispensable for interaction with physical world
Sub-micron transistors present unique challenges for analog design
Characterize the behaviour of the MOSFETsin any given
technology by doing simple I-V simulations and extracting
Vt, Rout etc. as a function of dimensions and bias points
The voltage swings in analog circuits will be limited by the
reliability constraints
While delay and power are the only two metrics for digital design,
analog design involves optimization and trade-off between
several conflicting metrics