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Microprocessor is a programmable integrated device that has

computing and decision-making capability similar to that of the


central processing unit of the computer.

It is a multipurpose, programmable, clock-driven, register-based
electronic device that reads binary instructions from a storage
device called memory, accepts binary data as input and processes
data according to those instructions, and provide results as output.

Micro -
Processor
Memory
Input
Output
Whereas Microcontroller that include all the components
shown in the previous figure on one chip.

Examples include a wide range of products such as washing
machines, dishwashers, traffic light controllers, and
automatic testing instruments.



8-bit microprocessor
Up to 8 MHz
64 KB RAM
Single voltage
On-chip peripherals
256 I/O ports
8080 object-code compatible
Produced: From 1977 to 1990s
Common manufacturer(s): Intel and several others
Instruction set: pre x86
Package(s): 40 pin DIP (Dual in-line package)

Features 8080 8085
Processor speed (MHz) 2 - 3.1 3 - 6
Power supply +5V, -5V and +12V +5V
On-chip peripherals
Clock oscillator
system controller
Serial I/O lines
Address/Data bus Separate address and data busses Multiplexed address and data
Pins/signals
Reset Out pin
RD bus signal
WR bus signal
IO/M bus signal
ALE pin provides encoded bus status
information
Interrupts
Three maskable interrupts and one
non-maskable
Instruction set
RIM - read interrupt mask
SIM - Set interrupt mask
Internal Registers and Flags of 8085A
Accumulator or A register is an 8-bit register used for arithmetic,
logic, I/O and load/store operations.

Flag is an 8-bit register containing 5 1-bit flags:
Sign - set if the most significant bit of the result is set.
Zero - set if the result is zero.
Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the
result.
Parity - set if the parity (the number of set bits in the result) is even.
Carry - set if there was a carry during addition, or borrow during
subtraction/comparison.

Stack pointer is a 16 bit register., it points to a memory location in
R/W memory canned the stack. The beginning of stack is defined by
loading the 16 bit address in the stack pointer.

Program counter is a 16-bit register, it points to the memory
address from which the next byte is to be fetched, when the next
byte is fetched the counter is incremented by one and point to next
location.

General registers:

8-bit B and 8-bit C registers can be used as one 16-bit BC register pair.
When used as a pair the C register contains low-order byte. Some
instructions may use BC register as a data pointer.

8-bit D and 8-bit E registers can be used as one 16-bit DE register pair.
When used as a pair the E register contains low-order byte. Some
instructions may use DE register as a data pointer.

8-bit H and 8-bit L registers can be used as one 16-bit HL register pair.
When used as a pair the L register contains low-order byte. HL register
usually contains a data pointer used to reference memory addresses.

Program, data and stack memories occupy the same memory
space. The total addressable memory size is 64 KB.

Program memory - program can be located anywhere in
memory. Jump, branch and call instructions use 16-bit
addresses.

Data memory - the processor always uses 16-bit addresses
so that data can be placed anywhere.

Stack memory is limited only by the size of memory. Stack
grows downward.
The processor has 5 interrupts. They are presented below in the order
of their priority (from lowest to highest):

INTR is maskable 8080A compatible interrupt. When the interrupt
occurs the processor fetches from the bus one instruction, usually one
of these instructions:

RST5.5 is a maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches
to 2Ch (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches
to 34h (hexadecimal) address.

RST7.5 is a maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches
to 3Ch (hexadecimal) address.

Trap is a non-maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches
to 24h (hexadecimal) address.
256 Input ports

256 Output ports
Data moving instructions.

Arithmetic - add, subtract, increment and decrement.

Logic - AND, OR, XOR and rotate.

Control transfer - conditional, unconditional, call subroutine, return
from subroutine and restarts.

Input/Output instructions.

Other - setting/clearing flag bits, enabling/disabling interrupts,
stack operations, etc.

Register - references the data in a register or in a register pair.

Register indirect - instruction specifies register pair containing
address, where the data is located.

Direct.

Immediate - 8 or 16-bit data.
In many engineering schools in developing
countries the 8085 processor is popularly used in
many introductory microprocessor courses.

The 8085 processor has found marginal use in
small scale computers up to the 21st century.

One niche application for the rad-hard version of
the 8085 has been in on-board instrument data
processors for several NASA and ESA space physics
missions in the 1990s and early 2000s
Monolithic 8-bit microprocessor and is an upgraded version
of 8080 CPU
Its instruction set has 156 basic instruction, which include the
8080 instruction set.
Mnemonic are different from Intel mnemonics
It requires +5v power supply and the clock frequency vary
from 4khz -20khz
Execution time 0f 1ms.
Z-80 chip has 16-bit address lines to address 64K memory
and eight data lines.
8-bit data bus is bi-directional as well as tri state buffered,
making direct memory addressing and multiprocessing
application realizable, with built in refresh signal and use
dynamic RAM.
The z-80 has two interrupt lines, one is compatible with
8080A interrupt line and second is non mask able interrupt.
Additional significant feature of the Z-80 is its onboard logic
RESH to refresh dynamic memory.
The internal architecture of Z-80 is similar to that of 8080
except that it has two 8-bit registers.
One set is active at the time, however access the alternate set
of register is only through an instruction called
exchange(EXX).
It has two 16-bit index register and one 8-bit interrupt vector
register, and one 7-bit memory refresh register.
The instruction set of Z-80 is the most powerful set among
the 8-bit microprocessors.

It includes instructions to transfer data from one block of
memory to another(LDIR), and to search the entire memory
for an 8-bit character(CPIR).
Jump functions performs more than one function , such has
decrement B and jump if non-zero(DNZ). This group of
instruction is called Bit Manipulation.
Z-80 microprocessor is supported by peripheral devices such
as the parallel I/O, the clock time circuit(CTC), the DMA and
the serial I/O.

16-bit microprocessor with 32 bit internal architecture housed in
64 pin package.
Capable of addressing 16 megabyte of memory and the clock
frequency ranges from 4Mhz to 10 MHz for different version of
chip.
It includes seventeen 31-bit general purpose register, 32 bit
program counter, 16 bit status register, 7 address registers and
2 stack pointers.
It is operated in 2 different modes. User mode and Supervisor
mode.
Non segmented memory: To increase memory addressing
capability, motorola increased no. of. Pins in its package.
The instruction set of M6800 as one of the most powerful yet
simple instruction sets. It include 56 basic instructions and can
operate on 5 different types of bits : BYTE, BCD, 16 BIT WORD
and 32 BIT WORD.




Asynchronous and Synchronous Controlling:
Communication with Asynchronous peripherals is handled
through control lines called UPPER DATE STROBE (UDS),
LOWER DATA STROBE (LDS) and DATA ACKNOWLEDGE
(DACK).
The DACK signal is similar to a handshake line: the bus cycle
is not terminated until the signal, DACK, is received.
The 68000 family offers some synchronous peripherals and
communication with these peripherals is handled through the
control signals called Valid Peripheral Addresses ( VPA), valid
Memory Addresses (VMA) and Enable(E).
The Intel 8086 is a 16-bit microprocessor that has both 8 bit and 16 bit
attributes.
It has a 16 bit wide physical path to memory for high performance.
Its architecture allows higher throughput than 5MHZ 8085 A-2.It is
available in different maximum operating frequencies like 5MHz 8086,
8MHz 8086-2 and 10 MHz 8086-1.
FEATURES:
1) Can directly address 1 Megabyte of memory.
2) 14, 16 bit register with symmetrical operations
3) 8 and 16 bit signed and unsigned binary or decimal arithmetic
operations
4) Multiply and divide instructions
5) 24 operand addressing modes
6) Assembly language compatible with 8080A/8085
7) Bit, byte , word and Block operations
8) Architecture designed for powerful assembly language and efficient
high level languages.
Several of the 40 pins of CPU have dual functions that are
selected by a strapping pin configured in minimum mode.
These pins transfer control signals directly to memory and
I/O devices.
In maximum mode, these same pins take on different
functions that are helpful in medium to large systems,
especially with multiple processors.
The control functions assigned to these pins in these modes
are assumed by support chip, the 8288 bus controller.
Microprocessor generally execute a program by repeatedly
cycling through the steps as shown below:
Fetch the next instruction from memory.
Read an operand (if required by instruction)
Execute the instruction
Write the result (If required by instruction)

The above steps allocate them to two separate processing
units within CPU.They are: (1) EXECUTION UNIT (EU) and BUS
INTERFACE UNIT (BIU)

Execution Unit (EU) executes the instruction and the other Bus
Interface Unit (BIU) which fetches instructions read operation and
writes results.
The two units which can operate independently and under most
circumstances are able to extensively overlap fetch instructions,
disappears because of the EU, executing instructions that have
already been fetched by the BIU.
EXECUTION UNIT:
The EU has no connection to the system bus.
Like wise, when instruction requires access to the memory or to
a peripheral device the EU requests the BIU to obtain or store the
data.
All addresses manipulated by the EU are 16 bit wide.
The BIU however, perform an address relocation that gives the EU
to the full megabyte of memory space.
BUS INTERFACE UNIT:
The BIU performs all the bus operations for the EU.
Data is transferred between CPU and memory or I/O devices
upon demand from the EU.
Other sections describe the interactions of the BIU with memory
or I/O devices.


(BIU contd:)
In addition when the EU is very busy, executing this
instruction, the BIU LOOKS AHEAD and fetches more
instructions from the memory.
The instructions stored in an internal RAM array called the
instruction stream queue.
The 8086 queue can store up to 6 Instruction Bytes.
These queues allow the BIU to keep the EU supplied with
perfected instructions undermost conditions without
monoplizing the system bus.
The 8086 fetches other instruction bytes whenever two bytes
are empty in its queue.
The 8086 BIU normally obtains two instruction bytes prefetch.
If a program transfer forces fetching from an odd address,
the 8086 BIU automatically reads one byte from the address
and then resume fetching two byte word from the subsequent
even address.
The primary function of a microprocessor is to process data
according to the instruction stored in its memory.

However the data meant for processing by the
microprocessor originate from outside, from different devices
such as keyboard, switches, analog to digital converters etc.

Therefore the microprocessor has to read from these input
devices.

The different approaches in connecting such devices to the
microprocessor are known as Interfacing of Microprocessor.


The Intel 8085 uses a 16-bit wide address bus for
addressing memories and I/O devices.

Using 16-bit wide address bus it can access 2
16
=
64 K bytes of memory and I/O devices.

The 64 K addresses are to be assigned to
memories and I/O devices for their addressing.


There are two schemes for the allocation of
addresses to memories and I/O devices.

1. Memory mapped I/O scheme
2. I/O mapped I/O scheme
In memory mapped I/O scheme there is only one address space.
Address space defined as set of all possible addresses that a
microprocessor can generate. Some addresses are assigned to
memories and some addresses to I/O devices

An I/O device is also treated as a memory location and one
addresses is assigned to it. Suppose that memory locations are
assigned the address 2000 to 24FF. One address is assigned to an
I/O device.

The address for I/O devices are different from the address which
have been assigned to memories. The addresses which have not
been assigned to memories can be assigned to I/O devices. For
example, 2500, 2501, 2502 etc, may be assigned to I/O devices.
One address is assigned to each I/O device.

In this scheme all the data transfer instructions of the
microprocessor can be used for both memory as well as I/O devices.
In this scheme address assigned to memory locations can also be
assigned to I/O devices.

Since the same address may be assigned to a memory location or an
I/O device, the microprocessor must issue a signal to distinguish
whether the address on the address bus is for a memory location or
an I/O device. The Intel 8085 issues an IO/M signal for this purpose.

When this signal is low the address on the address bus is for an I/O
device. When this signal is high the bus is for memory location. Two
extra instructions IN and OUT are used to address I/O device.

The IN instruction is used to read data of an input device. The OUT
instruction is used to send data to an output device. The scheme is
suitable for a large system.
Several memory chips and I/O devices are
connected to a microprocessor.

An address decoding circuit is employed to select
the required I/O device or a memory chip.

If is high the decoder 2 is activated and the
required I/O device is selected.

If is low, the decoder 1 is activated and the
required memory chip is selected. A few MSBs of
the address lines are applied to the decoder to
select a memory chip or an I/O device.


Prime or Main Memory
ROM (Read only memory)
MASKED ROM
PROM (Programmable ROM)
EPROM (Erasable programmable ROM)
EEPROM (Electronically Erasable Programmable ROM)
RAM (Random Access Memory)
Static
Dynamic
Storage Memory
Magnetic Bubble
Magnetic Disc
HDD
CD/DVD
PARALLEL AND SERIAL COMMUNICATION
The microprocessors receives (or transmits) binary data in
either of two modes: PARALLEL MODE AND SERIAL MODE.
PARALLEL MODE:
In the parallel mode, the entire word (4 bit, 8 bit or 16 bit) is
transferred one at a time.
Within the microcomputer data is transferred in parallel,
because that is the fasted way to do it.
The devices commonly used for parallel data transfer are
keyboards seven segment LEDS, data converters and memory.
For transmitting over long distances however parallel data
transmission requires too many wires. Therefore the data to
be sent to the long distances is usually converted to serial
form, so that it can be sent on single wire or pair of wires.
The serial I/O mode is commonly used with peripherals such as
teletypes (TTY) CRT terminals printers (also used in parallel
mode I/O) and Cassette tapes.
Three methods of serial data transfer are:
1) SIMPLEX
2) HALF DUPLEX
3) FULL DUPLEX.

A simplex data line can transmit data only in one direction.
Half duplex transmission communication can take place in
either direction between two systems but can occur only in one
direction at a time.
In full duplex each system can send and receive data at the
same time.
The hardware approach makes use of special purpose devices
for converting Parallel to Serial or Serial to Parallel data. One
such device is the Intels 8251 Universal Synchronous
Asynchronous receiver transmitter (USART).
This device can be used as a peripheral to a microprocessor for
serial communication.

Two main data transfer schemes are :
Programmed Data Transfer
Direct Memory Access Data Transfer
In the programmed data transfer scheme data are transferred from I/O
devices to the microprocessor using a program which resides in
memory.
In direct memory access scheme data are directly transferred from the
I/O device to the memory without going through the microprocessor.
The programmed data transfer is further classified as follows:
Synchronous Data Transfer
Asynchronous Data Transfer
SYNCHRONOUS DATA TRANSFER:
When the speed of an I/O device matches with that of the
microprocessor, Synchronous data transfer scheme is used.
Data are transferred from the microprocessor to / from the I/O device to
microprocessor using suitable instructions.
The IN instruction is used to read data from an input device or input
port.
The OUT instruction is used to send data from the microprocessor to an
output port.


As the speed of the I/O device matches with that of the
microprocessor, it is assumed that the I/O device is ready to
the transfer data when IN or OUT instructions are issued by
the microprocessor.
ASYNCHRONOUS DATA TRANSFER:
The asynchronous data transfer scheme is used when the
speed of an I/O device does not match the speed of the
microprocessor.
In this method of data transfer, the microprocessor checks
whether the peripheral is ready to transfer data or not prior to
the actual data transfer. This form of data transfer is also
known as DATA TRANSFER WITH HANDSHAKE.
DIRECT MEMORY ACCESS (DMA):
The direct memory access is a process of communication or
data transfer controlled by an external peripheral.
In situations in which the microprocessor Controlled data
transfer is too slow, the DMA is generally used.
For Example: Data transfer between a floppy disk and
memory of the System.

A microprocessor has two pins:
HOLD (hold)
HLDA (Hold acknowledge).
This is an active high input signal available on the 8085/8080
from another master requesting the use of the address and
data buses.
After receiving the HOLD request, the MPU relinquishes the
buses in the following machine cycle.
All buses are tri-stated and a hold acknowledge(HLDA) signal
is sent out.
The MPU regains the control of buses after HOLD goes low.
The processor completes the execution of the current
machine cycle floats (high impedance state) the address, the
data, and the control lines and sends the HOLD acknowledge
(HLDA) and destination , thus bypassing the microprocessor.
At the end of the data transfer, the controller terminates the
request by sending a low signal a low signal to the HOLD pin
and the microprocessor regains control of the buses.

When temperature is high than the reference
temperature, microprocessor sends control
signal to reduce temperature.

If the measured temperature is less than the
reference temperature, the microprocessor
sends a control signal to increase
temperature.
The temperature of the cabin is controlled by
controlling the air conditioner.


Probes
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