LINGAYAS INTITUE OF MANAGEMENT AND TECHNOLOGY

MADALAVARIGUDAM, KRISHNA Dt.

Department of Electronics and communication Engineering
SECOND SEMESTER 2012-13
Course Handout
VLSI
1. Course description: In this course the IC designing in very large scale is discussed. Digital design in
CMOS technology, layouts and applications in CMOS design is discussed in deatail.
2. Scope and Objective of the course: The aim of this course is to give a broad and general introduction to
the Very large scale IC design. One main goal is to give the student training in formulating and analyzing
simple digital design in CMOS technology. These techniques are widely used in low power applications.
3.Textbooks:
1. Essentials of VLSI circuits and systems Kamran Eshraghian, Eshraghian Dougles and A.
Pucknell, PHI,2005 Edition.
2. Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 1999.
4.

Reference books:
1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P. Uyemura, Thomson
Learning.
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
4. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
5. VLSI Technology S.M. SZE, 2nd Edition, TMH, 2003.

5.Course

Lec.
No.
1-7

Plan:

Learning Objectives
UNIT I
INTRODUCTION

7-12

UNIT II
BASIC
ELECTRICAL
PROPERTIES

12-20

UNIT III
VLSI CIRCUIT
DESIGN
PROCESSES

20-25

UNIT IV
GATE LEVEL
DESIGN

25-30

UNIT V

Topics to be covered
Introduction to IC Technology MOS, PMOS,
NMOS, CMOS & BiCMOS technologiesOxidation, Lithography, Diffusion, Ion
implantation, Metallisation, Encapsulation,
Probe testing, IntegratedResistors
andCapacitors.
Basic Electrical Properties of MOS and
BiCMOS Circuits: Ids-Vds
relationships, MOS transistor threshold Voltage,
gm, gds, figure of merit WO; Pass transistor,
NMOS Inverter,Various pull ups, CMOS
Inverter analysis and design, Bi-CMOS
Inverters.
VLSI Design Flow, MOS Layers, Stick
Diagrams, Design Rules and
Layout, 2 m CMOS Design rules for wires,
Contacts and Transistors Layout Diagrams for
NMOS and CMOS Inverters and Gates, Scaling
of MOS circuits, Limitations of Scaling.
Logic Gates and Other complex gates, Switch
logic, Alternate gate circuits, Basiccircuit
concepts, Sheet Resistance RS and its concept to
MOS, Area Capacitance Units, Calculations -Delays, Driving large Capacitive Loads, Wiring
Capacitances, Fan-in and fan-out, Choice of
layers
Subsystem Design, Shifters, Adders, ALUs,

References
Ch-1 of T1

Ch-2 of T2

Ch-3 &4 of T1

Ch-3 of T2

Ch-4 &5 of T2

SUBSYSTEM
DESIGN
30-37

37-43

43-48

6.

UNIT VI
SEMICONDUCTO
R INTEGRATED
CIRCUIT DESIGN
UNIT VII
VHDL SYNTHESIS
:
UNIT VIII
CMOS TESTING

Multipliers, Parity generators,Comparators,

Zero/One Detectors, Counters, High Density
Memory Elements.
PLAs, FPGAs, CPLDs, Standard
Cells,Programmable Array Logic, Design
Approach.

Ch- 6 of T2 & Ch-5

of T1

VHDL Synthesis, Circuit Design Flow, Circuit

Synthesis, Simulation, Layout, Design capture
tools, Design Verification Tools, Test Principles.

Ch-6 of T1

CMOS Testing, Need for testing, Test

Principles, Design Strategies for test, Chiplevel
Test Techniques, System-level Test Techniques,
Layout Design for improved Testability.

Ch 3& 4 of R1

Assignments: Comprises of Reading and/or Home assignments. Details will be

announced in the class from time to time and also will be uploaded in college website.

7. Evaluation scheme: : Consists of a series of Closed book and Open book tests after
completion of every Unit in addition to Descriptive and Online quiz exams as prescribed by the
JNTUK.

08. Notices: Concerning the course will be displayed on Department Notice Board.

INSTRUCTOR-IN-CHARGE