ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC.

2005

A Low-Power 6-bit 1GS/s Flash A/D Converter

In Jae Chung and Gi Hyun Ko
ECE Department, University of Illinois at Urbana-Champaign

1406 W. Green St., Urbana, IL 61801, U.S.A.

Abstract A 6-bit 1GS/s flash analog-to-digital converter
(ADC) for PRML DVD read-channel applications was designed.
The 63 slices of chains of comparators with digital back-ends
were put together for HSPICE simulations with random static
and dynamic offsets taken into account. We obtained ENOB of
5.73 bits (without offset) and 4.3 bits (with offset) for a 500MHz
frequency input signal. Resistor averaging schemes with an op
timum averaging factor (ratio of averaging resistance and output
resistance) were applied to mitigate the offset effects, improving
ENOB to 4.51 bits. Several architecture changes (e. g. multiplestaged preamp, etc.) were unsuccessfully attempted at the last
minute.
Index TermsAnalog-to-digital converter (ADC), flash, resist
or averaging, mismatch, digital error correction, quasi-gray en
coder, ENOB, SNDR.

I.INTRODUCTION
OW-VOLTAGE analog designs in mixed-signal systems have
been recognized as the essential technique to keep up
with the constant drop in digital supply voltage due to techno
logy scaling [1]. The CMOS channel length scaling brings
higher speed in digital designs. To interface with low supply
voltage and high speed digital circuitries in mixed-signal
chips, high-speed analog-to-digital converter (ADC) operating
at low supply voltage is increasingly needed. In this paper,
low-voltage and high speed methodology have been used in
the design of 6-bit fully-differential flash ADC in 0.25 m
CMOS process for a PRML DVD read-channel signal pro
cessing chip. In order to mitigate mismatch effects, resistive
averaging will be discussed and implemented. The flash ADC
architectures are typically the simplest and the fastest struc
tures that can be used to implement ADCs [3]. However, the
main downfall of flash-type ADCs is of larger die-size and
power consumption. The converter is designed to achieve low
est power consumption possible while operating at a satisfact
ory performance level. The first part of the paper describes the
architecture and building blocks. The optimization techniques
and digital error correction methods have been explained in
the following part. The final part of the paper shows simula
tion results.

ENOB (Fs < Fin < Fs/2) 5.5 bits

Input capacitance 1 pF
Total reference ladder resistance : 250
Supply voltage : 1.8 V
Process : 0.25 m CMOS
Ath, NMOS = 10 mVm, Ath, PMOS = 7.5mVm
Latch offset os = 25 mV

The main goal is to design a 6-bit flash ADC having a good

dynamic performance with given mismatch and dynamic latch
offsets constrained. For the purpose of demonstrating a
simplest yet realistic dynamic performance, threshold mis
matches associated with input differential pairs and a typical
dynamic offset value generated from latches are taken into ac
count. Once oss are obtained from transistor sizes, they are
multiplied with Gaussian random numbers with zero mean
and standard deviation of unity and added at the correspond
ing input terminals in SPICE netlists. This manual approach
enables us to account for essential process-dependent vari
ations in the early stage of design. We will skip DNL/INL
code test, while highlighting the targeted performances in
terms of ENOB/SNDR values.
B.Architecture descriptions
Figure 1 describes parallel characteristics of flash converter.
Among the 63 identical slices for 6-bit resolution, each con
sists of resistor ladder, preamplifier, and comparator followed
by digital back-ends. Fully differential comparators are re
quired in order to filter out even-number harmonic distortions.
Reference ladders spanning a full-scale (FS) voltage of 0.7 V
with a common-mode voltage of 0.85 V are constructed,
which provides differential reference voltages to preamplifier
reference terminals drawn from resistor taps. Regarding the
topologies of preamps and comparators, several topologies
were compared for bandwidth, gain, simplicity in search of
optimum candidates. Comparator connects analog signals into
digital block once it regenerates rail-to-rail analog signals
which become thermometer code. The one-out-of-2 N code is
ready once the thermometer code passes through digital cor
rection logic (here, 3-NAND are utilized). Quasi-Gray en
coder/decoder is chosen for a minimum latency as opposed to
Gray encoder/decoder for accuracy.

A.Design specifications
The specifications required for our design project are listed
below:
Resolution : 6 bits
Sample rate (Fs) : 1 GS/s

ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC. 2005

...

+ - +

ing edge of clock cycle, voltage imbalance fed into differential

pair will be amplified and show up at the output, triggering
latch operations. In our design, we make sure that cascade will
be effective in boosting up input signal difference, and the
parasitic capacitance dumped by PMOS latch and reset switch
are minimal, while functioning decently.

Latch & XOR

.VgvBPdnoiraeus-+fatmplifer

...

ROM

g5

b5

g4

b4

Quasi- b3
QuasiGray-toGray
g2 Binary b2
Encoder
Decoder
g3

+
+
-

g1

b1

g0

b0

...

+ - +

NAND

...

+ - +

Comparator

...

Preamp

...

Ref. Ladder

vim

vinp

clk

Figure 1 The schematics of overall flash ADC.

II.DESIGN OF BUILDING BLOCKS

A.Preamplifier design
Having several simple structures in mind, we mainly look
into three aspects of performance for fast and high-gain
preamp designs; bandwidth (speed), gain, and harmonic dis
tortion. High speed operation is highly needed since we do not
have a SHA in front-end. High gains will be also welcomed
since it fights against any noise generated from comparators.
However, distortion is also of concerns for a low supply
voltage design. With a FS of 0.7 V, a preamp gain larger than
5 will cause strong distortions since the rail-to-rail differential
voltage is only 3.6 V. Among three candidates, we pick up one
with differential pairs loaded with resistors. Tweaking resistor
value and transistor sizes results in gain of 3.1 and bandwidth
of 2.35 GHz. A FS voltage minimizing nonlinearity is 0.7 V in
our case. HSPICE simulations confirm that the peak-to-peak
output signal corresponding to sinusoidal input of 0.35 V
amplitude is ~2.2 V. As is pointed out later in the final present
ation, there is still possibility that gain can be improved
without sacrificing distortion and bandwidth by cascading one
or two stages subsequently. Unfortunately, we have not pur
sued it until at the last minute.
B.Comparator design
Among the other components, comparators are recognized
as a key component to determine speed and accuracy. A tiny
voltage difference detected in the preamp stage should be
amplified quickly enough. In that aspect, overdrive recovery is
one of the important performance metrics that our comparator
must meet. The comparator schematic shown in Figure 3 has a
cascaded differential pair with clocking in front-end, and pullup and pull-down latches with a reset switch connecting out
put terminals. On-clock will reset any output difference
(Vout). In off-clock cycle, latch operations will occur at the
output terminal, and the noise associated with it will be shut
off from input side since cascade gate will be off. On the fall

Figure 2 Resistor-loaded 4-input differential pair amplifier.

C
B
vcg
V
ln
d
ika
o
u
m
s-+
tparator

Figure 3 Comparator schematics.

Once preamp and comparator meet basic metrics, we put to

gether slice of preamp and comparator followed by buffers in
order to test for overdrive recovery. Given the transitions from
a positive FS to a negative half LSB (or vice versa) in the in
put at Nyquist frequency, whether it will resolve the output
signals is of the essential capability for comparator. Figure 4
visualizes how our comparator works. The top two curves are
1 GHz clock signal and 500 MHz input pulse wave. The input
signal takes on either a FS or a negative a half LSB. Preamp
output is shown as a third curve. The bottom two curves are
those of the comparator output and buffer output. As clearly
shown, the comparator successfully generates a negative peak
as large as 1 V with a negative half LSB within clock cycle.
Then, it is regenerated to a rail-to-rail signal at the buffer out
put.
2

ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC. 2005

Table I shows ENOB variations for several R2/R1 ratios where

R2 is averaging resistance and R1 is the output impedance.
TABLE I.

ENOB AT INPUT FREQUENCY OF 512 MHZ FOR THE DIFFERENT

AVERAGING RATIO (R2/R1).
ENOB (bits) at 512 MHz

No offset

With offset

R2/R1 = 0.25

R2/R1 = 1

R2/R1 = 2

5.7

4.32

4.34

4.40

4.51

Figure 4 Overdrive recovery test at Nyquist frequency.

III.RESISTIVE AVERAGING
As planned earlier in the checkpoint report, we design and
implement resistor averaging schemes. Averaging resistors
connecting adjacent amplifiers will allow for effective cancel
lations of low-frequency signals, particularly offset noise. It
can be also regarded as enlarging transistor sizes by providing
several identical amplifiers in parallel, and as a result reducing
random offsets. However, the ones residing at each boundary
have adjacent ones only at one side. It causes averaging to be
less effective on boundary amplifiers and their thresholds to
drift away from the value without averaging.
We work on two different configurations. The one called
triple cross-connection [6] is investigated first in order to see
if it minimizes threshold drift and gain compensation. As
pointed out in class presentation, negative transconductance
(gm) contributed by cross connected dummy amplifiers drops
the gain of amplifiers at the boundary, causing undesirable
systematic gain errors as shown in Figure 5. The top plot
shows the first few transfer curves of preamplifiers without
averaging, with their threshold uniformly apart by 1 LSB. The
middle and bottom sections contain the same with 6 and 8
dummy amplifiers cross-connected, respectively. It is noticed
that the first preamp with averaging has a significantly smaller
gain, 1.5 ~ 2.0 deviating from its original value, 3.1. It turns
out that the cross-connected amplifiers also deteriorate dy
namic performance. Specifically, its presence reduces ENOB
to 4.3 from 5.7 without offset included.
Afterwards, we look into a traditional averaging scheme in
that the additional reference ladder taps (beyond FS voltage)
feed dummy amplifiers. 8 dummies are provided at each
boundary and the terminal two dummies are cross-connected
to maintain symmetry. While burning extra powers, this meth
od preserves the gain of boundary amplifiers and has a uni
form capacitive coupling to every resistor tap. Based on the
available information regarding the effect of the number of
dummies and averaging ratios upon its performance, we
sweep through averaging ratios to find out an optimum value.

Figure 5 Transfer curves of the first six preamplifiers. The top section
contains transfer curves (TF) without averaging. The middle and bottom
ones show TFs for 6 and 8 dummies added at the boundaries, respect
ively.

IV.DIGITAL LOGIC DESIGN

A.Bubble Correction
For fast input signals, small timing differences between the
response time of the comparators and the offset voltages in the
comparators can cause a one to appear above a zero, which is
called a Bubble in the thermometer code [2]. There could be
a first-order bubble which has a single zero between the two
ones and higher order bubble which has more than one zero
between the ones. The latter is harder to correct but also less
likely to occur. Therefore, the bubble correction has been con
centrated on eliminating a single zero bubble. To correct the
bubble, digital circuit methods such as majority voting and 3input NAND gate masking method have been proposed [2].
The majority voting method uses equation (1) to compare
three consecutive thermometer outputs to obtain one corrected
output.
Cj* = Cj-1Cj +CjCj+1+ Cj+1Cj-1

(1)

The 3-input NAND gate masking method takes three con

secutive thermometer outputs and uses a masking scheme to
mask them before inputting them through a NAND gate to
produce a single corrected output. For typical first-order and
second-order bubble errors, the majority voting method will
give 75% correction rate as opposed to 50% correction rate of
the NAND masking method [7]. It turns out that the majority
3

ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC. 2005

...

...

...

...

voting scheme induces path-dependent delays at the logics

residing at the threshold. Assuming that threshold sits at the jth
slice, Ck* becomes high where k j. However, Cj* will be
high only through one path, Cj-1Cj in this case, while all the
other Ck* (k j) be high through three different paths, namely,
Cj-1Cj, CjCj+1, and Cj+1. Therefore, the low-to-high transition in
Cj* contains an additional delay compared with the others.
Another reason to use NAND masking method rather than
majority voting is on the fact that its output is in one-out-of-2 N
code. Majority voting will need an extra stage to convert ther
mometer codes into one-out-of-2N codes needed for ROM ad
dressing. Among the different masking schemes, we test
011 or 001 schemes. Both 011 and 001 will have
same correction rate. The only difference is the zero-to-one
crossing point of the output for certain cases. After testing the
two masking schemes, it has been concluded that the differ
ence is negligible.

g5

+
D

D
g4

g3

+
D

g1

g0

...

...

...

...

clk

Quasig2
Gray
Encoder

Figure 6 Digital error correction logics.

B.Metastability
A comparator of an analog-to-digital converter can often be
metastable, which means by the end of the conversion period
the comparator has not reached a decision. The metastability
of a comparator can cause zero, one or two ROM lines to be
selected, creating severe error in the digital output code [1].
Other than increasing positive regeneration pole of the com
parator, two other methods can be used to reduce metastability
error. One of the ways to reduce the error is to use pipelined
latches. Pipelined latches located after the comparator outputs
increases the regeneration gain of the comparator [1]. As
shown in Figure 6 and Figure 7, buffers made of two wellsized inverters and a D-flip-flop have been placed between
each stages of the design to increase the regeneration gain of
the comparator and to ensure the full scale voltage at the out
put of each stage.

4
vdd

g5

b5

g4

b4

g3

QuasiGray
Encoder

b3

g2

b2

g1

b1

g0

b0

clk

Figure 7 Quasi-Gray-to-binary decoder schematics.

Furthermore, Gray codes can be used in ROM encoders to

limit the output code error to a single bit. The Gray code en
coding, however, creates extra latency in the Gray-to-binary
decoder as subsequent bits are XOR of previous bits and the
Gray encoded ROM output as shown in the Figure 8. To re
duce the latency of the decoder, Quasi-Gray code can be used
in the encoder ROM instead of Gray code. The decoder for
Quasi-Gray code is much simpler and has less latency com
pared to its Gray counterpart. However, the mitigation of
metastability error using Quasi-Gray code is not as effective as
using Gray-code. Although most of the bits have only 1 bit
difference between each code, there are certain cases with 2 or
3 bit differences as shown in Figure 9. From 29 LSB to 30
LSB, there is only 1-bit difference. However, from 30 LSB to
31 LSB, there is a 3-bit difference. In the end, the decision can
be made by weighing latency against accuracy. The Gray code
encoder has worst latency but greatest accuracy. The binary
code encoder has best latency, as it requires no decoder, but
worst accuracy as its more prone to metastability error. The
Quasi-Gray code is in between the two methods for both
latency and accuracy. In this design, the Quasi-Gray encoder
has been selected as a result of more conservative approach.

g5

b5

g4

b4

g3

Gray-toBinary
Encoder

b3

g2

b2

g1

b1

g0

b0

clk

Figure 8 Gray-to-binary decoder.

ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC. 2005

30

vdd

...

...

...

...

...

...

20

10

Thermometer Code

Dout [LSB]

29
LSB

30
LSB

-10

-20
31
LSB

-30

10

20

30

40

50

60

70

Time [ns]
30
LSB

Figure 10 The digital output reconstructed for 500 MHz input frequency.
64 points are sampled for the subsequent FFT analysis.
g0

...

g1

...

g2

...

g3

...

...

g4

...

g5

Figure 9 Quasi-Gray-to-binary decoder.

-20

V.SIMULATION RESULTS

DYNAMIC PERFORMANCE SUMMARY

-40

Amplitude dB

A.ENOB (SNDR) Tests

Data post-processing is done in MATLAB environment in
order to generate digital bit sequence from HSPICE transients.
Upon decimation by 20 (one every 20 points), we obtain digit
al codes which is subsequently analyzed with FFT routines.
Figure 10 and 11 shows a reconstructed digital code and its
FFT results for an input sinusoidal of 500 MHz.
TABLE II.

64 sample FFT Plot

-60

-80

-100

-120
0

Metrics at 512
MHz

Without offset

With offset

Averaging

SQNR [dB]

36.36

28.38

30.03

SNDR [dB]

36.15

27.75

28.93

THD [dB]

49.45

36.39

35.46

SFDR [dB]

40.84

38.35

38.29

ENOB [bits]

5.71

4.32

4.51

However, offset inclusions severely damage its performance

as tabulated in Table II. ENOB becomes deteriorated by 1.4
bits when static as well as dynamic offsets are added at the
corresponding terminals in HSPICE simulations. Resistive av
eraging schemes as mentioned earlier improve ENOB by 0.2.
Although it is not a significant improvement, its effectiveness
might increase if we further optimize the preamps.
B.Performance measured with offsets
Key performance attributes are given in table III. With stat
ic power of 112 mW and total power of 131 mW, we were
able to achieve ENOBs of 4.3 up to Nyquist frequency at the
clock of 1 GHz.

0.1

0.2

0.3

0.4

0.5

Frequency [GHz]

Figure 11 FFT spectrum for input signal of 500 MHz.

TABLE III.

TARGET SPEC. VS. SIMULATION RESULTS.

Performance Measured with Offset

Specification

Unit

Target Value

Simulation
Value

Resolution

# bits

Sampling Frequency

GS/s

ENOB

# bits

5.5

4.3

Input Capacitance

pF

0.893

Input Common-mode
Voltage

0 Vcm 1.8

0.85V

Ohm

250

250

Total Reference
Ladder Resistance
Supply Voltage
Power Consumption

1.8

mW

Minimum

1.8
131 (total)
112 (static)

VI.CONCLUSION
A 6-bit 1GS/s flash analog-to-digital converter (ADC) for

ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC. 2005
PRML DVD read-channel applications was designed. The
HSPICE simulations show that ENOB of 5.73 bits (without
offset) and 4.3 bits (with offset) are obtained for a 500MHz
frequency input signal. Resistor averaging schemes with an
optimum averaging factor were applied to mitigate the offset
effects, improving ENOB to 4.5 bits.

64 sample FFT Plot

-20

Amplitude dB

-40

-60

-80

-100

APPENDIX
FFT analyses are carried on several input frequencies from
100 MHz up to 600 MHz. The ENOB variations are plotted in
Figure 12, and the corresponding FFT graphs are shown as
follows.

-120
0

0.1

0.2

0.3

0.4

0.5

Frequency [GHz]

Figure 14 FFT analysis on 200 MHz input signals.

64 sample FFT Plot

-20
5

Amplitude dB

ENOB [bit]

-40
4

-60

-80
3
-100
2

0.1

0.2

0.3

0.4

0.5

-120
0

0.6

FIN [GHz]

0.2

0.3

0.4

0.5

Frequency [GHz]

Figure 15 FFT analysis on 300 MHz input signals.

Figure 12 ENOB variations as a function of input frequency.

64 sample FFT Plot

64 sample FFT Plot

0.1

-20
-20
-40

Amplitude dB

Amplitude dB

-40

-60

-60

-80
-80
-100
-100

-120
0

-120
0
0.1

0.2

0.3

0.4

Frequency [GHz]

0.5

0.1

0.2

0.3

0.4

0.5

Frequency [GHz]

Figure 16 FFT analysis on 400 MHz input signals.

Figure 13 FFT analysis on 100 MHz input signals.

ECE598YC CMOS A-D INTERFACE CIRCUITS, FINAL PROJECT REPORT, DEC. 2005

64 sample FFT Plot

-20

Amplitude dB

-40

-60

-80

-100

-120
0

0.1

0.2

0.3

0.4

0.5

Frequency [GHz]

Figure 157 FFT analysis on 500 MHz input signals.

64 sample FFT Plot

-20

Amplitude dB

-40

-60

-80

-100

-120
0

0.1

0.2

0.3

0.4

0.5

Frequency [GHz]

Figure 18 FFT analysis on 600 MHz input signals.

ACKNOWLEDGMENT
Gi Hyun Ko and In Jae Chung express deep appreciations
regarding comprehensive and insightful lectures on a
semester-long lectures offered by Professor Y. Chiu and his
guidance throughout this project.
REFERENCES
[1]
[2]
[3]
[4]

[5]
[6]
[7]

K. Uyttenhove and M. Steyaert, A 1.8-V 6-Bit 1.3-GHz Flash ADC in

0.25-um CMOS, IEEE J. Solid-State Circuits, vol. 38 pp. 1115-1122,
July 2003.
C. W. Mangelsdorf, A 400-MHz Input Flash Converter with Error
Correction, IEEE J. Solid-State Circuits, vol. 25 pp. 184-191, Febru
ary 1990.
B. Razavi, Principles of Data Conversion System Design. Piscataway,
NJ: IEEE Press, 1995.
M. Choi and A. Abidi, A 6-bit 1.3-GSamples/s flash ADC in 0.35-um
CMOS, IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, Dec.
2001.
K. Kattman and J. Barrow, A Technique for Reducing Differential
Nonlinearity Errors in Flash A/D Converters, ISSCC Dig. Tech. pa
pers, pp. 170-171, Feb. 2003.
X. Jiang, Z. Wang, and M. F. Chang, A 2GS/s 6b ADC in 0.18um
CMOS, ISSCC Dig. Tech. papers, pp. 170-171, Feb. 2003.
Y. Chiu, CMOS A-D Interface Circuits Lecture 14, pp. 21, Fall 2005.