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High performance phase-locked-loop (PLL) design method is discussed. Method allows any order PLL but is especially useful for high order PLLs. DPLL realization on a fixed point digital signal processor (DSP) and APLL realization with a commercially available circuit are presented, discussed and compared.
High performance phase-locked-loop (PLL) design method is discussed. Method allows any order PLL but is especially useful for high order PLLs. DPLL realization on a fixed point digital signal processor (DSP) and APLL realization with a commercially available circuit are presented, discussed and compared.
High performance phase-locked-loop (PLL) design method is discussed. Method allows any order PLL but is especially useful for high order PLLs. DPLL realization on a fixed point digital signal processor (DSP) and APLL realization with a commercially available circuit are presented, discussed and compared.
IST / INESC R. Alves Redol, 9,2 1000-029 LISBOA . PORTUGAL Telf. +351.1.3100379/3100339 . Fax +351.1.3145843 Teresa.Almeida@inesc.pt, msp@inesc.pt ABSTRACT An high performance phase-locked-loop (PLL) design method is discussed. In this context high performance means an high or- der PLL with efficient noise reduction and accurate frequency re- sponse achievements. Both analog PLL (APLL) and digital PLL (DPLL) designs may be obtained through the proposed technique. The method allows any order PLL but is especially useful for high- order PLLs because of its difficult design. Explicit formalism for PLL design is established and APLL and DPLL models are also presented. High order design examples are discussed. Experi- mental results obtained through DPLL realization on a fixed point digital signal processor (DSP) and APLL realization with a com- mercially available circuit are presented, discussed and compared. Finally, conclusions are drawn. 1. INTRODUCTION The PLL, both in its analog and digital forms, is a versatile func- tional device widely used in modem communication and control systems as a reliable way for demodulation, synchronization, syn- thesization, tracking or ranging of signals, etc. [ 1,2]. High-order PLLs are of special interest because of their high selective frequency characteristics. Since the input signal may be severely contaminated by noise and some of the PLL components may also introduce non-negligible internal noise, it is desirable to have a very selective frequency response to allow efficient noise reduction. This selectivity may be achieved through an higher or- der specification in the frequency domain as it is proposed here. Higher order PLLs are also of special interest to some practical applications. Nevertheless, due to the lack of appropriate design methods, they are not very often found in practical applications. With the proposed design method it is possible to obtain high per- formance APLLs and DPLLs and cross the usual maximum limit of second and third order PLLs [ 1,2]. The basic configuration of a PLL consists of four functional blocks: a phase detector (PD), a low-pass filter, a digitallvoltage controlled oscillator (DCONCO) and a phaselfrequency divider without delay. The four components are connected to form a feed- back closed loop (fig. 1) [l, 2, 33. Based on this basic loop topology both an analog (section 2) and a digital (section 3) PLL model are established, in order to support the proposed PLL design method. The parallel between the two models is analyzed. High order design examples are pre- sented in section 4 and experimental results are discussed in sec- tion 7. Finally, conclusions are drawn in section 8. 40 Filter Oscillator 9 Phase I @d 4 Detector m Figure 1 : Phase-locked-loop feedback structure. 2. ANALOG PLL MODEL Considering the PLL already in lock with the input signal [l, 21 it is possible to establish a linear model in order to analyze the APLL dynamic behavior. Although some of the components may have nonlinear gain characteristics, a linear characteristic is here assumed. The phase detector produces an output proportional to the phase difference between its inputs (eq. 1). The VCO controls the instantaneous frequency (WO =dqb/ dt ) at its output with a gain factor of k, (eq. 2). (1) (2) ad($) =kd [@E(S) - @n(S)] O( S) =k , / s , WO =Ro +kwVF The loop filter is not restricted to the usual first or second-order pole/zero associations [ 1, 21. Instead, a generic filter structure is considered, allowing any order (eq. 3). Defining a loop gain factor [l, 21, X =kdFok,/N, it is possible to establish the APLL transfer function, G0(s)/@i (s), as: Since the loop transfer function is chosen a priori (eq. 5) , allow- ing any APLL design exclusively based on its specification, the APLL components parameters may be directly associated with the transfer function coefficients (eq. 5 and 6). 0-7803-5471-0/99/$10.0001999 IEEE IV-394 3. DIGITAL PLL MODEL As previously, a linear general DPLL model is now considered. Due to the discrete and feedback characteristics of the loop, a DPLL implementation implies that someplace inside the loop a time delay must exist to avoid a delay-free loop. In order to achieve simplicity and a straightforward realisable model, the time delay is attached to the phase detector feedback branch (eq. 7), because this will be the loop first operation to be performed inside the DSP. (7) Again, assuming a linear PD characterized by kd, a filter char- acterized by F( z ) , a DCO characterized by a generic function O(z) =@o( z ) / af ( z ) and gain factor k, and a frequency/phase division factor N, a generic DPLL Mth-order transfer function, ao( z ) / ai ( z ) , may then be written as: @. d(Z) =kd [@i(Z) - Z-' @,(Z)] For the usual first-order DCO derived from its analogue counter- part VCO, O( z) =k,/(l - z - ' ) , it is possible to express the loop filter coefficients as: Considering the Bilinear Transformation [4] as the method to map the APLL to the DPLL specification and imposing the constraint that the number of DPLL zeros is one less the number of poles ( y ~ =0), it is possible to explicitly identify an APLL zero at 2Fs [5]. This restriction implies that a ( M - l)th-order digital filter is obtained which means a perfect match between the APLL and DPLL components results as desired. Since several of the most common low-pass frequency response characteristics (such as But- terworth, Chebychev, Elliptic (odd order) [4]) have y~ =0 it is always possible to add this extra zero to the APLL specification without affecting the desired DPLL and loop filter orders. On resume, once the APLL frequency response is specified, an additional zero is imposed at 2F.9 and the DPLL transfer func- tion coefficients are obtained via the Bilinear Transformation. The (A4 - l)th-order digital filter coefficients may then be obtained through eq. 9. 4. DESIGN EXAMPLES R o APLL/DPLL illustrative design examples are now consid- ered. A 3'd-order (usually the maximum practical order [l , 21) and a 7th-order PLL with Butterworth [4] frequency response were chosen. In order to allow a perfect match between the APLL and DPLL realizations and their performance stand comparison, the choice of the PLL parameters was mainly restricted due to the dig- ital realization limitations (as explained in section 6). Since it is usual to have a PLL with a very lower cut-off frequency than the oscillator free-running frequency [ 1, 21, due to these limitations, a cut-off frequency of 398Hz (approximately 1/50 of the sam- pling frequency) was chosen for both PLLs. The VCO/DCO free- running frequency was set to fo =3kHz and its desired linear limits to fo f 1.5kH.z. The APLL design takes into account its realization with a commercially available circuit with an exclusive- or (XOR) PD (see section 5). The DPLL design considers its im- plementation on a fixed-point DSP with a direct phase difference PD (see section 6). For the purpose of illustration, the 3Td-order APLL and DPLL design parameters (obtained with the proposed design equations) are derived in the following subsections. 4.1. APLL 3'd-order Butterworth Design For the 3'd-order low-pass Butterworth frequency response with 398Hz cut-off frequency (at 3dB), the theoretical transfer coeffi- cients are: cy0 =PO =1, cy1 =cy2 =cy3 =0, p1 =7.99773583E-4, PZ =3.19818892E-7, p3 =6.39456754E-11, which leads to N = 1. Assuming a power supply with V+ =-V- 5 V is used, the XOR phase detector gain is kd =3.18309886 V/ r ad. With the same power supply and the limits specified in the previous section, the VCO gain is k, =1884.955592 r ad/ s / V. The resulting Znd- order filter is then characterized by: FO =0.20839231, a0 =. bo = 1, a1 =a2 =0, bl =3.99886792E-4, bz =7.99547231E-8, which corresponds to a pole frequency of wp =3536.53482 r adl s with quality factor Qp =0.70710678. The modulus of the desired APLL frequency response aindits filter are depicted (flipped left-right) in fig. 5 (solid lines lalbeled T3 and F3, respectively). The corresponding curves for the 7th- order APLL design are also depicted (T7 and F7). 4.2. DPLL 3'd-~rder Butterworth Design Starting with the APLL transfer function (derived in the previous subsection), after adding the necessary extra zero at 2Fs and ap- plying the bilinear transformation, the DPLL transfer function co- efficients are: yo =4.41303009E-4, y~ =8.82606018E-4, 7 2 = 63 =-7.77315688E-1. Maintaining the parallel with the APLI,, the DPLL parameters are: N =1, kd(ALU) =0.31831 aZu/raa! ( a h means here fictional ALU units), k,(ALUf =0.47505 rad/ s/ aZu . The resulting IIR [4] filter is characterized by: FO =0.404011966, 4.41303009E-4,73 =0,150 =1,61=-2.74842215,62 =2.52750305, CO =7.22338342E-3, CI =1.44467668E-2, ~2 =7.22338342E-3, do =1, dl =-1.74886346, dz =7.77756993E-1. As in the analog case, in fig. 6 are depicted the theoretic curves (solid lines) corresponding respectively to the flipped left-right fre- quency response of the DPLL (T3) and the loop filter (F3). The corresponding curves for the 7th-order DPLL design are als'o de- picted ("7 and F7). 5. APLL REALIZATION The APLL realization was based on the commercially available phase locked loop 4046 circuit [6]. It includes a VCO andl two PDs (a XOR and an edge-controlled digital memory network). The XOR was chosen for two reasons. Its characteristic is identical to the one of the digital direct phase difference detector [3] and it has an higher immunity to noise [6]. In order to obtain a rectangu- lar wave clean from interference, a voltage comparator circuit [7] was also included at the input (see fig. 2). The external compo- nents that control the VCO characteristic ( &, & and C a b ) were chosen to obtain a frequency offset [6] and to satisfy the design requirements. Since the VCO experimental gain was higher than the desired value, an attenuator with a variable resistor (a) was included (fig. 2). IV-395 4046 " +T-Thornas H T-Thomas HT-Thomas Biquad 1 Biquad 2 Biquad 3 vco vo Figure 2: Simplified block diagram of the APLL realization. The external loop filter was realized with Tow-Thomas biquad sections (fig. 3) which are versatile and easy to design [7]. The 3Td-~rder APLL is implemented with only one biquad. The 7t h- order filter includes three biquads. The first section has unity gain and the lowest quality factor. The second section gain was adjusted to maximum unity gain. The last section has the highest quality factor and its gain was adjusted to provide the remaining global filter gain. The values of the used components differed 15% at most from the theoretic values. - R Figure 3: Tow-Thomas biquadratic section. The loop filter frequency responses proved to be very accurate showing that the filter was not affected by the finite gain bandwidth product of the operational amplifiers [7] for the frequency range of interest. The 7th and 3Pd-~rder filter theorical frequency response modulus are depicted in fig. 5 (solid lines labeled F7 and F3). 6. DPLL REALIZATION The DPLL realization was accomplished using the 16 bit fixed- point DSP TMS320C25 and its software development system en- vironment [4]. An analog interface board with two analog in- putloutput channels which is based on the TLC32040 analog in- terface circuit [5] was used. This circuit has a reconstruction anti- XIN DCO, XOUT Figure 4: Simplified block diagram of the DPLL realization. aliasing lowpass filter that was software programmable to half the sampling rate which in turn is also software changeable but limited by the 12 bit ADC and DAC supported rate. A sampling frequency of FS =19.84kHz was chosen. Due to the one input channel and one output channel with anti-aliasing filter limitation, besides the DPLL structure two extra block were added (fig. 4). An input DCO (Dco,,) simulates the input phase signal ($,,) to which, for instance, external noise (ztn) may then be added to analyze the DPLL performance in the presence of noise. A sine wave gener- ator addressed by the loop DCO output is also included. A direct table lookup scheme with linear interpolation was used, providing an output sine waveform with very low harmonic distortion. A direct realization of the phase difference PD was imple- mented based on the DSP arithmetic logic unit wraparound char- acteristic [4]. Its input phase signals are sawtooth waveforms vary- ing between i l which simulates the phase variation between f r . Both the input DCO and the loop DCO also take advantage of the DSP arithmetic logic unit wraparound characteristic. The filter was implemented through the cascade of second- order canonic IIR sections with coefficients and node scaling al- lowed [4]. As in the analog case, the 3'd-order DPLL includes only one section, while the 7th-order includes three sections. The 7th and 3Pd-~rder filter theorical frequency response modulus are depicted in fig. 6 (solid lines labeled F7 and F3). 7. EXPERIMENTAL RESULTS Since in the DPLL a direct phase difference realization was imple- mented ($1 and $0 aresawtooth signals - fig. 4) and a XOR PD (211 and vo are rectangular waves - fig. 2) was used in the APLL, it is difficult to experimentally obtain T( ej UT8) or T ( j w) in a di- rect way. An additional transfer function relating the filter output P-OdWf i H*] 5 3 1 0 7 0 5 0 3 0.1 0 . 0 7 0 0 5 Figure 5: APLL 7th and (flipped left-right) 3rd-order experimen- tal (dotted lines) and theoretic (solid lines) frequency responses modulus: T - PLL; F - filter; H - filtered phase error function. with the input phase signal was defined (respectively H(eJ wTs) and H(jw)). This transfer function is named here as the filtered phase error function. Both the loop filter and filtered phase error function frequency response modulus were experimentally characterized and are de- picted in fig. 5 and 6. Tomaximize the charts dynamic range for both the 7t h and 3'd-order PLLs, the 3'd-order plots were flipped left-right and are depicted with different scales (top and right scales) from those of the 7th-order (bottom and left scales). A direct comparison with the theoretic curves (solid lines) shows both APLL and DPLL precise frequency response achieve- IV-396 Figure 6: DPLL 7th and (flipped left-right) Srd-order experimen- tal (dotted lines) and theoretic (solid lines) frequency responses modulus: T - PLL; F - filter; H - filtered phase error function. H I Figure 7: APLL Noise Performance: input signal (dotted line) and VCO output (solid lines) spectrums (7th and 3'd-orders). ments. In spite of the PLLs high order a very accurate realization was obtained in both cases. In order to avaliate high order APLL and DPLL performance in the presence of noise, experimental measures were conducted with the input signal contaminated by white noise with 20kHz bandwidth. In the analog case, a sinusoidal signal ( 2Vpp , 3kHz) was added with white noise, before the input comparator. The in- put signal (present at the APLL input, after the comparator) spec- trum is depicted in figure 7 and labeled input (dotted line). The VCO output signal (for the 7th and 3rd-order APLL) were then measured and are depicted as solid lines. It is possible to envisage the shape of the APLL frequency response to the left and right of the loop free-running frequency. Since the output signal is a rect- angular wave, the replicas around the 2nd and 3Td harmonics are also present. As it was expected, the 7th-order APLL allows an higher external noise reduction than the 3'd-order APLL. Unlike the analog case, where the noise was added before the comparator in order to disturb the APLL input signal zero crossing points, in the digital realization the noise signal was introduced via the input analog interface channel. Then, already inside the DSP, -d n Figure 8: DPLL Noise Performance: noise input signal (dotted line) and DCO output (solid lines) spectrums (7th and 3'd-orders). it was directly added to the DCO,, phase signal, which was set to 3kHz . The input noise signal spectrum (after crossing both the input and output paths to and from the DSP) is depicted in fig. 8 (dotted line) and labeled input. The loop DCO output sawtooth signal was used to address the sine wave generator. It is this (output sine wave spectrum that is represented in fig. 8 (solid lines) and analyzed as the indicator of the DPLL performance in the presence of external noise. As in the previous case, both the 7t h and 3'd- order DPLL output spectrums are depicted in fig. 8. Once again, the loop frequency response is envisaged around the free-running frequency. Since in this case the output signal is sinusoidal. there are no harmonic replicas present. 8. CONCLUSION A design method for high performance analog and digital PLL was presented. Explicit formalism for APLL and DPLL design was es- tablished. Higher order PLLs may then be designed and realized eliminating the lower limit of second and third-order PLLs usually considered. The performance of practical applications with PLLs will then benefit from the proposed technique. Design examples of an APLL implemented with a commercially available circuit and a DPLL implemented on a fixed point DSP were provided. Eixper- imental results obtained for the design examples were presented and discussed and corroborate the developed formalism. 9. REFERENCES [ 11 Phaselock Techniques, F. M. Gardner, J ohn Wiley Sons, 1979. Phase-Locked Loops, R. E. Best, McGraw-Hill, 1993. DPLL Design and Realization on a DSP, Teresa M. Almeida and MoisCs S. Piedade, Proc. of the 1997 ICSPAT, San Diego, Digital Signal Processing - A Practical Approach, E. C. Ifea- chor and B. W. J ervis, Addison-Wesley, 1996. From APLL to DPLL via the Bilinear Transformation, Teresa M. Almeida, INESC Internal Report, 1998. 4046 Data Sheet, Philips, May 1983. Microelectronic Circuits, A. S. Sedra and K. C. Smith, Saun- ders College Publishing, 3rd Ed., 1991. CA, 1997, vol. 2, pp. 1624-1628. IV-397