E-mail: sales@modelithics.com 1 of 8 ACCURATE NON-LINEAR MODELS ENABLE SUCCESSFUL PIN LIMITER DESIGN
SUMMARY This application note focuses on the design and measurement validation of a 1.8 GHz PIN diode limiter circuit. The design utilizes Aeroflex/Micrometrics MLP7100 limiter diodes (CS19-1 package) mounted on 16 mil-thick Rogers 4003 microwave laminate. The MLP7100 device has a breakdown voltage in the 20-45 V range and a typical threshold power level (1 dB increase in insertion loss) of +10 dBm at 1 GHz. A non-linear model from the Modelithics NLD Library V3.1 was used in the design process. Other Aeroflex/Micrometrics diode models in the V3.1 library currently include those for the MLP7110, -7120, and -7101 devices. The following sections summarize the MLP7100 model development and validation, the dual- diode limiter, lumped-element matching circuit design, and frequency- and time-domain characteristics of the 1.8 GHz limiter. Small- and large-signal measurements of the limiter correspond very closely to the predicted performance. The anti-parallel diode configuration used in the design provides a symmetric response to an input AC waveform, thus suppressing the generation of even-order harmonics this characteristic is verified using simulations of the output spectrum and time-domain waveforms.
MLP7100 NON-LINEAR MODEL CHARACTERISTICS
The non-linear model for the MLP7100 diode was extracted from a series of measurements that included C-V, I-V, RF impedance and small- and large-signal S-parameters. The measurements were performed at 25 and 85 degrees Celsius. A comparison between measured and simulated small-signal S-parameters for a 2-port series mounted diode is given in Figure 1. The performance is shown for 0-Volt and 100 mA bias conditions.
The MLP7100 model is applicable to die and CS19-1 packages; the package style is selected via a user-level input parameter in the model. The performance differences between package styles are illustrated in Figure 2 for a series 2-port configuration. At 4 GHz, package parasitics result in ~2 dB difference in the return loss and insertion loss.
Power-sweep measurements were performed at 1 GHz on die-level parts that were mounted to a carrier and connected using bond-wires (Figure 3). A typical Agilent Technologies Advanced Design System schematic for large-signal simulations, and a comparison between measured and simulated S 21 swept-power performance are given in Figure 4 and Figure 5, respectively.
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1 2 3 4 5 6 7 8 9 0 10 -10 -5 -15 0 -100 -80 -60 -40 -20 -120 0 freq, GHz M A G
( d B )P h a s e S11 Mag and Phase 1 2 3 4 5 6 7 8 9 0 10 -25 -20 -15 -10 -5 -30 0 -20 0 20 40 60 80 -40 100 f req, GHz M A G
( d B )P h a s e S21 Mag and Phase 1 2 3 4 5 6 7 8 9 0 10 -30 -20 -10 -40 0 20 40 60 0 80 f req, GHz M A G
( d B )P h a s e S11 Mag and Phase 1 2 3 4 5 6 7 8 9 0 10 -0.8 -0.6 -0.4 -0.2 -1.0 0.0 -40 -20 -60 0 f req, GHz M A G
( d B )P h a s e S21 Mag and Phase
Figure 1 - Series 2-port S-parameters for the MLP7100 diode in a CS19-1 package at 25C. Legend: Top Row 0V; Bottom Row 100 mA. Red lines = model magnitude; Violet lines = model phase; Dark blue markers = measured data magnitude; Light blue markers = measured data phase.
2 4 6 8 0 10 -12 -10 -8 -6 -4 -2 -14 0 -100 -80 -60 -40 -20 -120 0 freq, GHz M A G
( d B ) P h a s e S11 Magnitude and Phase 2 4 6 8 0 10 -30 -20 -10 -40 0 -20 0 20 40 60 80 -40 100 freq, GHz M A G
( d B ) P h a s e S21 Magnitude and Phase
Figure 2 - Model series 2-port S-Parameter comparison between the chip and package performance of the 7100 diode at 0 Volts bias. Legend: Red = magnitude package; Violet = phase package; Blue = magnitude chip; Light blue = phase chip.
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Figure 3 - MLP7100 mounted in 2-port shunt configuration.
Figure 4 Advanced Design System schematic configuration for large-signal testing of the MLP7100 diode chip. Bond-wire effects were de-embedded from the measurement data.
Figure 5 - Measured (markers) and simulated large-signal S 21 at 1 GHz.
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1.8 GHZ LIMITER DESIGN
The diode topology chosen for the limiter design is the shunt, dual-diode configuration shown in Figure 6. The diodes are arranged in an anti-parallel pair and attached to either side of a microstrip line. The microstrip cross junction, vias and other interconnect elements are included to emulate the physical layout as closely as possible. The small-signal S-parameter sweep results indicate an input impedance of 38.8-j20.8 at 1.8 GHz, thus requiring the addition of a matching circuit for best performance.
MSUB MSub1 Rough=0 mm TanD=0.0038 T=1.7 mil Hu=1.0e+033 mm Cond=1.0E+50 Mur=1 Er=3.5 H=16 mil MSub VIA V2 dio_MLP7100_ADS_diode_package X3 Temp=25 MCROSO Cros1 VIA V1 dio_MLP7100_ADS_diode_package X2 Temp=25 MTAPER Taper4 MLIN TL2 MTAPER Taper3 MLIN TL4 Term Term2 Z=50 Ohm Num=2 MTAPER Taper7 MLIN TL7 Term Term1 Z=50 Ohm Num=1
Figure 6 - Dual-diode limiter schematic (left). Simulated S11 for the dual-diode limiter schematic; the input impedance at 1.8 GHz is 38.8 - j20.8 (right).
The matching circuit selected for the limiter is a shunt L series C configuration shown in Figure 7. The shunt inductor is a 3.9 nH Toko 0603 part and the series capacitors is a 3.3 pF ATC 0805 part. The impedance looking into port 2 is set to the complex conjugate of the dual-diode input impedance (see inset) to achieve the impedance match.
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2008 MODELITHICS, INC. www.modelithics.com E-mail: sales@modelithics.com 5 of 8 MSUB MSub1 Rough=0 mm TanD=0.0038 T=1.7 mil Hu=1.0e+033 mm Cond=1.0E+50 Mur=1 Er=3.5 H=16 mil MSub Term Term2 Z=50 Ohm Num=2 Term Term1 Z=50 Ohm Num=1 MTAPER Taper8 MLIN TL6 IND_TKO_0603_001_MDLXCLR1 TKO_LL1608FSL_L1 VIA V3 MTEE Tee1 MLIN TL8 MTAPER Taper5 MLIN TL5 MTAPER Taper6 CAP_ATC_0805_001_MDLXCLR1 ATC_600F_C1
Figure 7 - Matching circuit for the limiter. The shunt inductor is 3.9 nH and the series capacitor is 3.3 pF. Port 2 (right-hand side) will connect to the dual-diode configuration.
1.8 GHZ LIMITER SIMULATION AND MEASUREMENT VALIDATION
The layout for the limiter design, generated using the schematic capture feature in Advanced Design System, is shown in Figure 8. As noted above the circuit was assembled on a 16 mil- thick Rogers 4003 substrate. The comparison between measured and simulated small-signal S-parameter measurements (Figure 9) confirms the broad-band accuracy of the modeling approach.
Swept-power, or large-signal S-parameter measurements were subsequently performed at 1.8 GHz. As demonstrated in Figure 10, excellent agreement between the model and measurement data was achieved. At an input power of 15 dBm there is ~4 dB compression in S 21 .
The simulated output spectrum given in Figure 11 indicates that significant 3 rd and 5 th order products are generated using the dual-diode configuration (left-hand side of figure). If a single- diode configuration were used instead, both odd and even harmonics are produced (right-hand side of figure). In order to simulate the single-diode configuration the upper diode in Figure 6 was deactivated.
The impact of the harmonic products on the time-domain waveform is illustrated in Figure 12. This figure shows the output voltage under 1.0V and 15V excitations at 1.8 GHz. As would be expected, there is little difference in the output voltage between the dual- and single-diode
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2008 MODELITHICS, INC. www.modelithics.com E-mail: sales@modelithics.com 6 of 8 configurations when driven by a 1.0V source. For the 15V excitation, the time-average power delivered to the load and the peak voltage are considerably larger for the single-diode design.
Port 1 Port 2 CAP IND PIN PIN
Figure 8 - Limiter layout generated from ADS schematic.
1 2 3 4 0 5 -30 -25 -20 -15 -10 -5 -35 0 Freq (GHz) d B ( S 1 1 ) 1 2 3 4 0 5 -8 -6 -4 -2 -10 0 Freq (GHz) d B ( S 2 1 ) Simulation BLUE Measurement - RED Simulation BLUE Measurement - RED
Figure 9 - Measured and simulated small-signal S-parameters for the limiter.
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2008 MODELITHICS, INC. www.modelithics.com E-mail: sales@modelithics.com 7 of 8 -5 0 5 10 -10 15 -4 -3 -2 -1 -5 0 I/P Power (dBm) d B ( S 2 1 ) Simulation BLUE Measurement - RED Swept Power S21
Figure 10 - Measured and simulated large-signal S21 data for the limiter.
2 4 6 8 0 10 -10 0 10 -20 20 Frequency (GHz) P o w e r
O u t
( d B m ) 2 4 6 8 0 10 -10 0 10 -20 20 Frequency (GHz) P o w e r
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( d B m )
Figure 11 - Simulated output spectrum using 1.8 GHz input signal at Pin = 15 dBm: using the dual- diode (anti-parallel) configuration (left) and using a single-diode configuration (right).
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2008 MODELITHICS, INC. www.modelithics.com E-mail: sales@modelithics.com 8 of 8 0.5 1.0 1.5 0.0 2.0 -0.4 -0.2 0.0 0.2 0.4 -0.6 0.6 Time (ns) O u t p u t
V o l t a g e
( V ) 1.8 GHz, Vinput = 1.0 V, Dual-Diode 0.5 1.0 1.5 0.0 2.0 -5 0 5 -10 10 Time (ns) O u t p u t
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( V ) 1.8 GHz, Vinput = 15 V, Dual-Diode 0.5 1.0 1.5 0.0 2.0 -10 -5 0 -15 5 Time (ns) O u t p u t
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( V ) 1.8 GHz, Vinput = 15 V, Single-Diode 0.5 1.0 1.5 0.0 2.0 -0.4 -0.2 0.0 0.2 0.4 -0.6 0.6 Time (ns) O u t p u t
V o l t a g e
( V ) 1.8 GHz, Vinput = 1.0 V, Single-Diode
Figure 12 - Time-domain output voltage waveforms at 1.8 GHz: dual-diode (anti-parallel) configuration (top) and single-diode configuration (bottom); 1.0V source voltage (left) and 15V source voltage (right).
ABOUT THIS WORK
This work was performed as a collaboration between Micrometrics and Modelithics, Inc, funded by Aeroflex-Micrometrics. University of South Florida MS student Aswin Jayaraman assisted with the development of this material under grant funding provided by Modelithics, Inc.
For more information about Modelithics Products and Services, call (813) 866-6335 2008 - Modelithics, Inc. This document may not be copied without the written permission of Modelithics, Inc.