CAD for VLSI 1

Homework #1




1. Install and run iverilog and GTKWave for the input files listed below:
1. fibonacci.v and fibonacci_tb.v
2. halfadder.v . Write your own testbench.
3. fulladder.v . Write your own testbench. Write brief notes on how you think
simulation works in each of these cases. Note down problems that you face in installing and
using the tool. Write a 2 page report about your experiences in using the tools. Turn in a
neatly hand-written or a printed copy. Do not attach waveforms or Verilog source code.
fibonacci.v



/ / Fi bonacci sequence i s 0 1 1 2 3 5 8 . . . . . . 233
/ / act i ve l ow r eset , ot her wi se count on posi t i ve t r i gger of cl k
modul e f i bonacci ( out put [ 7: 0] f i bseq, i nput r st , i nput cl k) ;

wi r e [ 7: 0] f i bseq;
r eg [ 7: 0] Reg1;
r eg [ 8: 0] Reg2;

/ / bi t pat t er n i s pr i nt ed i n deci mal f or conveni ence
i ni t i al
begi n
$moni t or ( $t i me , " : Fi bSeq = %d " , f i bseq) ;
end

al ways@( posedge cl k or negedge r st )
begi n
/ / on r eset , i ni t i al i ze r eg1 t o 0
i f ( r st == 1' b0) begi n
Reg1<=8' b00000000;
Reg2<=8' b00000001;
end
el se i f ( cl k==1' b1)
begi n
/ / Reg1 and Reg2 wi l l i nf er r egi st er s
Reg1 <= Reg2;
Reg2 <= Reg2 + Reg1;
i f ( Reg2[ 8] == 1)
$di spl ay( " \ t \ t out of r ange ERROR" ) ;
end
end

/ / Copy Reg1 t o out put
assi gn f i bseq = Reg1;
endmodul e
fibonacci_tb.v

`i ncl ude "f i bonacci . v"
/ / Test Bench
modul e f i bonacci _t b; / / st i mul us f or Fi bonacci gener at or
r eg cl k, r st ;
wi r e[ 7: 0] f i bseq;

/ / I nst ant i at i ng t he Fi bonacci Modul e of f i bo. v
f i bonacci u1( f i bseq, r st , cl k) ;

i ni t i al begi n
#0 cl k=1' b0;
r st =1' b1;
#12 r st =1' b0;
#10 r st =1' b1;
#150 $f i ni sh; / / at t i me=172 st op si mul at i on
end

/ / cl k t hat t oggl es f or ever y 5 uni t s of t i me
al ways
#5 cl k=~cl k;

/ / moni t or t he out put s
i ni t i al
begi n
$dumpf i l e( " f i bonacci . vcd" ) ;
$dumpvar s;
$dumpon;
#172 $dumpof f ;
end

endmodul e
halfadder.v

modul e hal f adder ( sum, cout , a, b) ;
/ / por t l i st does not di f f er ent i at e i nput s and out put s
/ / do so now

i nput a, b;
out put sum, cout ;

/ / concur r ent si gnal assi gnment on sum
/ / uses a dat af l ow expr essi on

assi gn sum = a ^ b;

/ / AND pr i mi t i ve i s used her e
/ / i mpl i es st r uct ur e
and( cout , a, b) ;
endmodul e
fulladder.v

modul e f ul l adder ( out put sum, out put cout , i nput a, i nput b, i nput ci n) ;
/ / por t l i st di f f er ent i at es i nput s and out put s

/ / some t ool s expect t he i nput s and out put s t o be decl ar ed as wi r es t oo

wi r e a, b, ci n, sum, cout ;


wi r e s1;

/ / sum i s gener at ed as ( a xor b) xor ci n
/ / s1 i s a wi r e t hat st or es a xor b

xor ( s1, a, b) ;
xor ( sum, s1, ci n) ;

/ / a concur r ent si gnal assi gnment st at ement t akes car e
/ / of t he assi gnment on cout

assi gn cout = ( a&ci n) | ( b&ci n) | ( a&b) ;

endmodul e