12MECV15 (Compatibility Mode)

SoC Development Containing Teststructures
for SiVal of Memories/IOs/Efuse/Std Cells

TM
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are
the property of their respective owners. Freescale Semiconductor, Inc. 2008.
14/03/2014
Presented by:
Gaurav Lalani
12MECV15
M.Tech-VLSI
Intern at : FSL
Guided By:
Mr. Parvez Zaman
Internal Guide:
Dr. N.P.Gajjar
for SiVal of Memories/IOs/Efuse/Std Cells
Topics Covered Topics Covered
ASIC Design Flow
RTL Synthesis Flow
Synthesis Environment
Synthesis Flow in RC compiler
TM
Multi-Corner Synthesis
Work Done till Date
Future Work
An ASIC/VLSI Design Flow An ASIC/VLSI Design Flow
TM
An RTL Synthesis Flow An RTL Synthesis Flow
TM
What is Synthesis ? What is Synthesis ?
Translation from higher abstraction level to lower abstraction
level
It is the process of converting RTL to gate level netlist
3 types of synthesis:
Behavior Synthesis
TM
Behavior Synthesis
RTL Synthesis
Physical Synthesis
Does RTL Synthesis Really Matter? Does RTL Synthesis Really Matter?
Bad synthesis results can have far
What if I have Bad
Netlist ?
Poorly structured paths
Higher cell area
Unroutable
Congestion
Too slow
Crosstalk
More
Iterations
Too big
Back-end Issues
TM
Bad synthesis results can have far
reaching consequences.
Larger
Die
High Power
Consumption
Increased
Engineering Costs
Slower
Speed
Project Issues
Late To
Market
High Part
Costs
High
Development
Costs
Market Issues
Inputs
RTL: Verilog,
VHDL, directives, pragmas.
Constraints: .sdc or .g
Library: .lib
Physical: LEF, DEF, Captable
Logic Synthesis Environment Logic Synthesis Environment
Encounter
RTL
Compiler
RTL Code
Captable
LEF
.LIB Constraints
TM
Outputs
Optimized netlist
Constraints : .sdc or .g
First Encounter
input files
Physical
Design
Optimized
netlist
Constraints
RTL Lib
Read RTL
Elaborate &
Uniquify
Scan Stitching
Incremental Optimization
Synthesis Flow in RC Compiler
TM
Timing & Design Constraints
Synthesize to Generic Logic
Map to Technology Library
Netlist Constraints
Elaboration Elaboration
During Elaboration RC compiler performs following tasks:
1) Builds data structure
2) Infers registers in the design
3) Performs high level HDL optimizations
4) Checks Semantics
TM
Uniquification Uniquification
Top Module For FA
HA
Instantiation
1
HA
Instantiation
2
TM
Module
Definition
For
HA
Module
Definition
For
HA
Design Constraints Design Constraints
Clock signal specification
period
duty cycle
transition time
Skew
Delay specifications
TM
Maximum
Minimum
Timing exception
false path
multicycle path
Boundary Optimization & Constant Propagation Boundary Optimization & Constant Propagation
Constants can modify structure inside an hierarchy and change net
connections across hierarchical boundaries.
Rewiring of equivalent signals across hierarchy
If two outputs of a module are identical, RC may disconnect one of them and
use the other output to drive the fanout logic for both.
Optimize away unloaded flops and associated logic
TM
Optimization of flop-driven hierarchical boundaries
Flops with constants in the D lines are equivalent to constants depending on reset
method.
clk
FF
D
Q
rst
1b0
Optimization
1b0
Equivalent assign
statement in
verilog
Equivalent assign
statement in
verilog
Hierarchy boundary Hierarchy boundary
unused unused
1b0
Also driven away Also driven away
TM
Multi Corner Synthesis Multi Corner Synthesis
REQUIREMENT : -
For C65 and below technologies, due to temperature inversion ,delay of a cell is maximum
at wcscold corner, whereas transitions are better at low temperature. CPF with multiple
library domain can be used in such scenarios.
TM
Multi Corner Synthesis . Multi Corner Synthesis .
Encounter
RTL
Compiler
RTL Code
Captable
LEF
.LIB Constraints
TM
Physical
Design
Optimized
netlist
Constraints
Interacting signals in Multi Power Domain Design Interacting signals in Multi Power Domain Design
Power Domain 1
(1.2V)
Power Domain 2
(1.0V)
Memory
Isolation
Normal V
L
e
v
e
l

S
h
i
f
t
e
r
TM
1.2V
Domain
Power Domain 3
(1.8V) switchable
Memory
Low V
t
(High Speed)
Normal V
t
High V
t
(low leakage,
lower Speed)
Isolation
Isolation
Isolation
QOR METRICS QOR METRICS
AREA
TIMING
POWER
TM
POWER
YIELD
Physical Physical synthesis : For better Timing convergence synthesis : For better Timing convergence
Floorplan Def is read in to RC.
RC does actual placement by
invoking Encounter
Rs & Cs are extracted on basis of
actual placement data from a placed
def.
Annotate RC
Chip Place Prototype
Post optimization netlist
TM
def.
These values are annotated to timing
data.
Shows better correlation for the final
placement results in synthesis stage.
Incremental Optimization
Based on RC
Annotate RC
LMTV ARCHITECTURE LMTV ARCHITECTURE
Core
Control
Registers
Freq_ Counters Bus MUXs
Padring
Address
System
Control
Chip ID RO
Input
Data
Output
Data
EFuse
Array
TM
MFTR
Memory
Functional
Test
and
Repair
Block
STD and
I/O Cells
Core
Address
Pwr/Gnd
Memory Control
MTM
Memory
Timing
Measureme
ntBlock
Ref.: FSL Internal Doc
Work Done till Date Work Done till Date
Presently working on Synthesis of LMTV SoC
Understood the basic concepts of Static Timing Analysis
Blocks Synthesized:
All_Cell
Ring Oscillator
TM
Ring Oscillator
Memory Test and Repair (MTR)
Frequency Counter
Padring
Efuse, SRAM, ROM, 2PRF, 1PRF
Future Work Future Work
Execute Synthesis on LMTV SoC with relevant optimizations.
Performing Verification of PROMO test-chip.
TM
THANK YOU
TM

12MECV15 (Compatibility Mode)

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SoC Development Containing Teststructures

for SiVal of Memories/IOs/Efuse/Std Cells

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