Transmission gates,

latches
and ipops
Transmission gates
A transmission gate (Fig. 1) is an analog switch controlled by logic signals. It consists of a n
and a p type MOS transistor. When the EN = 1 the gate conducts and shorts the input and
the output, otherwise it cuts o and the output oats.
The characteristic equations of the n and p type MOS transistors are:
I
Dn
=
W
n
L
n

ox
t
ox

(V
GSn
V
Tn
) V
DSn

V
2
DSn
2

and
I
Dp
=
W
p
L
p

ox
t
ox

(V
GSp
V
Tp
) V
DSp

V
2
DSp
2

respectively, where the threshold voltage of the n type transistors (V

Tn
) is positive while that
of the p types (V
Tp
) is negative.
In order to understand the operation of transmission gates, the entire input range of V
in
needs to be investigated at both true and false values of the enable signal (EN).
Figure 1: A transmission gate
Lets examine the EN = 1 case rst and
lets assume that
V
DD
> V
Tn
+ |V
Tp
|
as in Fig. 2.
In this case the gate potential of the n type
transistor is at V
DD
and that of the p type is
at ground potential. When the input (V
in
) is
below |V
Tp
|, the p type transistor is closed as
it needs to have a V
GSp
= V
Gp
V
Sp
V
Tp
to
conduct. The n type transistor on the other
hand conducts as its gate-source voltage is
large enough: V
GSn
= V
Gn
V
Sn
.
If the input voltage goes above |V
Tp
| the p
type transistor starts to conduct. When the
input voltage rises above V
DD
V
Tn
the gate-source voltage of the n type transistor becomes
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less than V
Tn
so it cuts o. But by this time the p type transistors channel is created and
it connects the input and the output. In summary we can conclude that at least one of the
transistors conducts during the entire input range when the enable input is true.
Figure 2: The threshold voltages
when V
DD
> V
Tn
+ |V
Tp
|
When the enable input is false (EN = 0) the gate
of the n type transistor is at ground potential, that of
the p types is at V
DD
. This means that in the entire
[0, V
DD
] voltage range of the input voltage the gate-
source voltage of the n type transistor is less or equal
to zero, so the transistor cuts o. The same is true for
the p type as its source potential is less or equal than its
gate potential in the entire range, thus its gate-source
voltage is always non-negative.
We have found that when EN = 0 the transis-
sion gate is equivalent to an open circuit between its
input and output.
When
V
DD
V
Tn
+ |V
Tp
|
the conducting regions of the transistors overlap when
EN = 1, which means that there is a voltage range
where both transistors conduct. This makes the series resistance of the gate even less, which is
advantageous.
The RS latch
The RS latch (Fig. 3.) is the simplest sequential logic element that can be used to store one
bit. It consists of two NOR gates and contains feedbacks from both of gates outputs. It is a
bistable circuit, which means that it has two stable states.
Figure 3: An RS latch
The truth table of a NOR gate can be seen
in Table 1. The operation of the latch can be
analysed using the table.
Lets assume that the output of the
RS latch is false (Q = 0 and Q = 1). This
means that 1 is fed back to the upper NOR
gate and 0 to the lower gate. When R = 0
and S = 0 then the upper NOR gate provides
0 at its output and the lower one gives 1, so
the circuit is in a stable state.
When S is set to 1, the lower NOR gate
has 0 and 1 at its inputs so its output turns
to 0. As a consequence, the input of the upper
NOR gate becomes 0 0, so its output changes
from 0 to 1. When S becomes 0 again, the lower NOR gate has 1 0 at its inputs, so it still
provides a 0 at its output. This means that the latch is in a stable state again but its output
has changed from 0 to 1. S stands for set for this reason.
If R becomes 1, the output of the upper gate changes to 0. The lower gate now has 0 0 at
its inputs so its output goes high. The input of the upper NOR gate thus becomes 1 1 but this
combination doesnt result in a change at its output, it remains 0. When R goes back to 0,
the upper gates input combination becomes 0 1, which still results in a 0 at its output, so the
latch falls back to a stable state with an output value of 0. So the R input resets the output.
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If both inputs go high, then both outputs will go low independently of the circuits state
as the NOR gate has a 0 at its output if any of its intputs is 1. When they fall back to 0,
the output will become either 0 or 1 depending on which signal falls back faster. This is an
unpredictable operation, so an RS latch should never have logic 1 at both inputs at the same
time.
Table 1: The truth table of a NOR
gate
A B A|B
0 0 1
0 1 0
1 0 0
1 1 0
D latch with transmission gates
A D latch has two inputs: a data input (D) and an
enable or clock input (EN). When then enable input
is true it copies its input to its output. When the enable
becomes false the output freezes and stays at the logic
level the input had at the time of enable inputs falling
edge.
A D latch can be realized using an RS latch simply
by connecting S to the R input. However, several other
ways D latches can be realized exist due to the fact that
it is probably the most important latch.
Figure 4: A D latch with transmission gates
A very simple circuit can be seen in Fig. 4.
It consists of only two transmission gates and
two inverters (8 transistors altogether). The
two inverters will copy the input (D) to the
output (Q) when the upper transmission gate
is on. Q is also available from between the
two inverters.
The basis of the operation is that the two
transmission gates operate alternatively. This
is obvious if one looks at the way the enable
input is connected to them: EN is connected
to the n type transistor of the upper gate,
while it is connected to the p type transistor
in the lower one.
Thus when EN falls to 0, the transmission
gate at the input of the latch cuts o and
separates the input from the output. At the
same moment, the other gate in the feedback
branch starts to conduct and will connect the output to the input of the rst inverter. This is
a stable circuit where the input capacitance of the inverters hold the information.
Dynamic D ipop
With the same number of transistors (8) a D ipop can be realized (Fig. 5). A ipop is a
1-bit memory that changes its output only at the rising or falling edge of the enable or clock
signal.
A latch is transparent during one of the logic levels of the clock. This is unwanted as the
output value cannot be read with certainty during this half period.
Flipops consist of two latches in series controlled by inverted clock signals. The rst latch
monitors the input during the true level of the control signal and freezes at the falling edge,
while the second copies the output of the rst to the output during the false level of the control
3 November 7, 2012
and freezes at the rising edge. It never experiences changes during these half periods as its
input, the output of the rst latch is frozen. This way changes only occur at the falling edge
of the control signal, when the rst latch freezes and the second one copies its output to the
ipops output.
Figure 5: A dynamic D ipop
This is exactly what is done in the cir-
cuit in Fig. 5. The somewhat surprising fea-
ture of this circuit is that there is no feedback,
so it might seem unclear where the informa-
tion is stored. The answer is that the input
capacitance of the inverters is charged and
discharged during the half-periods when the
transmission gates at their inputs are on and
when the inverters inputs oat in the other
half, the accumulated charges will ensure that
the inverters remain in the same state that
they were last driven to.
When EN = 1 the transmission gate at
the input conducts and charges the input capacitance of the rst inverter to the value of the
input. When EN falls to 0, this gate cuts o and the other one conducts. The rst inverter
remains at the value it was charged to and drives the second inverter. This way the input at
the time of the falling edge gets to the output after two inversions, i.e. unchanged. When EN
rises again, the second inverter is separated from the rst one and during this half-period its
input capacitance stores the output.
Every capacitor gets discharged in time. Parasitic parallel resistors can always be found
around capacitors and charges ow away from the plates gradually. This means that if such a
D iop is left on its own, i.e. the enable signal doesnt change often enough, then the input
capacitances get discharged and the output is set to 1 independently of the original value stored
in the circuit.
Actually the situation is even worse: a oating node (e.g. the input of the second inverter
when EN = 1) is very susceptible to noises. If a high impedance node is not driven, very weak
signals are able to change its potential. This means that in a noisy environment, the output of
such a ipop is set to a random value if the enable signal is left unchanged for a long time.
For these reasons, dynamic logic circuits are only used in parts of a system where the clock
signal is very fast and thus the input capacitances are frequently recharged to a correct value.
4 November 7, 2012