COE/EE 244

Logic Circuit Lab

Lab #3; Page 1/9

Spring 2003

Implementing Combinational Circuits

Due: By 6:00pm on Wednesday March 12.

1 Objectives
In this lab you will design combinational circuits to perform more useful digital functions. You will
design the circuit, and then implement it using the Xilinx ISE tools, simulate it and then download your
design to the FPGA on the Digilab board for testing.

2 Downloading Your Design to the Digilab Board

You need to modify your basic circuit design slightly from the one you used in Lab #2. In lab #2 you used
what the Xilinx tools refer to as hierarchy connectors to control your inputs and outputs. Now you need
to set up your design so it can be programmed onto the FPGA. This requires mapping your inputs and
outputs to specific pins on the FPGA. The FPGA input and output pins are mapped to switches, LEDs,
Vdd, or ground on the Digilab board as shown in the table below. For now use the switches (SW1-8) as
inputs and the LEDs (LD1-8) as outputs.

2.1 Design and Download Steps

This is similar to what you performed in Lab 2, with a few changes made to the final few steps so that it
can be downloaded to the FPGA.
1. Click on the Project Navigator to start the software.
Note: If you can create your schematic at home, copy it onto a floppy disk and bring it in to the
lab (bring the file with extension *.SCH). You can incorporate it into the new project by using the
steps outlined in the conversion process in Lab 2.
2. Select File -> New Project. Assign a project name, and for project location, use d:\projects\
<yourprojectname>. Next, under the Device Family value, select Spartan2, then for Device
value, select xc2s30-6tq144. Finally, select Design Flow value as XST VHDL and click okay.
3. Next, select Project -> New Source. Select schematics as the source type. Type in the filename
making sure you dont use VHDL keywords or operators. Now in the Project Navigator, double
click on the schematic entry in the project tree which will open up the schematic capture tool.
4. From the palette on the right you can select logic gates and symbols.
5. Dont forget to add the input and output buffers to your inputs and outputs, respectively. These are
needed to map to the FPGA. Leave space for wires.

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Logic Circuit Lab

Lab #3; Page 2/9

Spring 2003

6. Select Add -> Wires and Input/Output markers to add wires and I/O Terminals. Use the draw
wires to add wires, or the draw buses to add buses. Use the Add IO Marker to add the IO Markers
to your inputs and outputs.
7. Save your design and then select Tools -> Check Schematic to check your design. Once you are
done you can minimize or close the schematic.
8. Next from the Project Navigator window in the Process for Current Sources window expand the
design entry utilities then under user constraints double click on edit implementation constraints
file. From the menu select Edit, Select All and hit the delete key to clear everything written there
and then assign your pin numbers as shown below. For an example, a 2 input AND gate would
have 2 inputs (a, b) and output (c). You would want to map the inputs to switches and output to led
like this:
Net a loc = p57; (57 is pin number for switch 1)
Net b loc = p59; (59 is pin number for switch 2)
Net c loc = p93; (93 is pin number for led 1)
9. Now you should be able to synthesize and implement your design (again make sure you have the
correct FPGA selected (xc2s30-6tq144)). The synthesis tool is run using the process menu by
double clicking on the Synthesize branch or by right-clicking on Synthesize and selecting Run. Be
sure to check the output window for error messages.
10. You can then perform the functional simulation as you did in lab #2, and you may want to perform
a timing simulation.
11. Now you are ready to download your design. The implementation stage created a bit file that can
be downloaded. Right click on Generate Programming File and select properties. Click on Start
Up options and change the Start Up clock to JTAG clock and the close the window.
Make sure that your board is ready for you to download. Switch 1 (SW1) is located near the middle
of the board. Make sure that the switch SW1 is in the JTAG position (as marked on the board).
12. Expand the Generate Programming icon and double click Configure Device (iMPACT).
13. This will open up another window. Right click on the FPGA and select program. It may pop
a window up that has a verify box unchecked with everything else on the window greyed out.
Dont select verify or it will produce errors. This will program the FPGA. Low and Behold the
design is on the board now. Do you believe it?!!!! If it didnt work, make sure all the steps were
followed, and if all else fails ask the Lab Instructor - we dont want your fun ruined.
14. Verify the functionality.

COE/EE 244
Logic Circuit Lab

Lab #3; Page 3/9

Spring 2003
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

FPGA Pin #

122
121
120
118
117
115
114
113
112
103
102
100
99
96
95
94
93

Function
GND
VU
VCC
LDG
NC
LD8
NC
LD7
NC
LD6
NC
LD5
A4
LD4
A3
LD3
A2
LD2
A1
LD1

Pin # FPGA Pin #

21
87
22
86
23
85
24
84
25
83
26
80
27
79
28
78
29
77
30
75
31
74
32
67
33
66
34
65
35
63
36
62
37
60
38
59
39
58
40
57

Function
BTN4
BTN3
BTN2
BTN1
DP
SW8
CG
SW7
CF
SW6
CE
SW5
CD
SW4
CC
SW3
CB
SW2
CA
SW1

3 Multiple Output Circuits

The next several sections are included to provide you with some additional examples to aid you in the
completion of the lab assignment.
It is fairly simple to apply the processes we have studied to create useful digital circuits. Quite often
the circuit will have more than one output. An example of this is a code converter. Consider a circuit
designed to convert BCD code to a 5311 weighted code1 . The truth table showing the required functions
is given in Figure 1.
The first step is to use K-maps to minimize each output as a separate function. Note that in this
case, even though BCD codes use 4 bits, not all 4 bit combinations are used. Assuming the unused
combinations will not be presented as inputs to our code converter, we can treat them as dont cares.
When this is done we arrive at the K-maps shown in Figure 1. Separately minimizing each K-map leads
1 Instead

and 1.

of the bits carrying the weights 8, 4, 2 and 1 as they do in BCD, the bits of a 5311 code carry the weights 5, 3, 1

COE/EE 244
Logic Circuit Lab
A
B
C
D

Code
Converter

BCD
ABCD
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1

Lab #3; Page 4/9

Spring 2003
W

W
X
Y
Z

AB
00 01 11 10
CD
00 0 0 1

5311
WXYZ
0 0 0 0
0 0 0 1
0 0 1 1
0 1 0 0
0 1 0 1
1 0 0 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 0 1

AB
00 01 11 10
CD
00 0 1 1

01 0

01 0

11 0

11 1

10 0

10 0

AB
00 01 11 10
CD
00 0 0 0

AB
00 01 11 10
CD
00 0 1 0

01 0

01 1

11 0

11 0

10 1

10 1

Figure 1: BCD to 5311 Converter Design

to the following set of functions.
W = A + BD + BC
X = A + BC D + BCD
Y = BCD + BCD
Z = BD + BCD + BC + CD
If implemented directly, this set of equations would together require 10 AND gates and 4 OR gates.
However, it is often possible to share product terms between the various functions. For example, the
term BC can be shared between W and Z. Also, the term BC D from X can be used in place of the
term BD in Z. This is obviously not a prime implicant for Z, but since the term BC D is required in the
implementation of X, sharing it with Z saves the cost of another AND gate. Similarly, the term BCD
from Y can replace the term CD in Z. All the shared terms are shaded grey in Figure 1. The resulting
implementation shown in Figure 2, requires only 7 AND gates.
While there is a formal procedure by which several functions can be jointly minimized, quite often
the minimal implementation can be determined by simply individually looping each K-map and then
identifying terms, not necessarily prime-implicants, that can be shared among the various K-maps.
Some logic implementations allow outputs for product terms to be shared, others do not.

COE/EE 244
Logic Circuit Lab

Lab #3; Page 5/9

Spring 2003
D

BD

BC

BCD

BCD
BCD
Y
BCD
Z
BCD
Figure 2: BCD to 5311 Code Converter

4 Arithmetic Circuits
Consider next, the problem of making a circuit capable of performing binary addition on two binary
numbers. To add two n bit numbers would require a circuit with 2n inputs. Since it is difficult (at least by
hand) to minimize functions of more than 6 variables, we might not be able to design adders for numbers
larger than 3 bits! Obviously we need another approach. If we examine the process we use to add two
binary numbers by hand, we see that at each step we add two binary bits and a possible carry-in term
producing a single bit result, and a possible a carry-out term that carries at most one bit position to the
left.
Once we have made these observations, it is fairly simple to construct a circuit to do the addition.
First we construct a circuit that will perform a 3 bit addition on bits An , Bn , and Ci (where An and Bn
are the nth bits from the two binary words to be added, and Ci is the carry-in bit) and produce Sn and
Co (where Sn is the nth bit in the resulting sum and Co is the carry bit that is carried one position to the
left). To do this we first describe the three bit adder (commonly called a full adder) with a truth table and
then we use K-map techniques to simplify the boolean functions. Note that this circuit only has three
inputs, and can be easily designed. This is done in Figure 4. Examining the K-maps in Figure 4, at first

COE/EE 244
Logic Circuit Lab

Lab #3; Page 6/9

Spring 2003
Co
Ak
Bk
Sk

Ak;1
Bk;1
Sk;1

...
...
...

Ci

-.
An
Bn
Sn

...
...
...

A1
B1
S1

A0
B0
S0

Figure 3: Binary Addition

An
0
0
0
0
1
1
1
1

Bn
0
0
1
1
0
0
1
1

Ci
0
1
0
1
0
1
0
1

Sn
0
1
1
0
1
0
0
1

Co
0
0
0
1
0
1
1
1

Sn

An Bn
00 01
Ci
1
0 0
0
1 1

11
0
1

10
1
0

Co An Bn
00 01
Ci
0 0
0
1 0
1

11
1
1

10
0
1

Sn = AnBnCi + AnBnCi +
AnBnCi + AnBnCi

Co = AnBn + BnCi + AnCi

Figure 4: A Full Adder Truth Table and K-Maps

we do not see any way to share terms and simplify the implementation. However, the circuit for the full
adder can be made considerably more simple if we realize that the expression for Sn can be written as
Sn = An Bn Ci where is the exclusive-OR boolean function. The exclusive-OR (EXOR) operation
is associative and commutative, but not distributive over the other basic boolean functions. Some useful
exclusive-OR expressions, the EXOR and EXNOR symbols and representative K-maps are shown in
Figures 5 and 6.
Having an idea of how EXOR functions look in K-maps helps us to recognize situations in which
EXORs might be useful in simplifying circuits. It is easy to see that Sn = An Bn Ci by comparing
the K-maps for Sn in Figure 4 and F3 in Figure 5. Also, if we plot Bn Ci on a three variable K-map (as
in the K-map for F5 in Figure 5), we can see that Co = An (Bn Ci )+ BnCi which is useful because we
can share the (Bn Ci ) operation with the one used to compute Sn . This results in the simple full adder
circuit shown in Figure 7. This circuit can now be used to construct multibit adders as is done in Figure
8.

5 Summary
In summary, there is always more than one way to design a circuit. Once you have completed a design,
you should always look for possible simplifications and other ways to implement the design. Be creative!

COE/EE 244
Logic Circuit Lab

Lab #3; Page 7/9

Spring 2003

F2

F1 X
0
Y
0 0
1 1

1
1
0

F3

XY
00
0

F1 = X Y

01
1

11
0

10
1

XY
00
Z
0 0
1 1

F2 = X Y

11
0
1

10
1
0

F3 = X Y Z

F4

WX
00
YZ 00 0
01 1
11 0
10 1

01
1
0

F5
01
1
0
1
0

11
0
1
0
1

XY
00
Z
0 0
1 1

10
1
0
1
0

01
1
0

11
1
0

10
0
1

F5 = Y Z

F4 = W X Y
Figure 5: EXOR and EXNOR functions

X
Y
Z

X
Y
Z

X
X
Y

Y
X
Y

Z = (X

Y)

=X

=X

X
Y

Figure 6: EXOR and EXNOR symbols and equivalent circuits

An
Bn
Ci

Sn

Co

Figure 7: Full Adder Circuit

COE/EE 244
Logic Circuit Lab

Lab #3; Page 8/9

Spring 2003
A3 B3

A2 B2

F.A.

Co S3

A1 B1
Ci

Ci

F.A.

Co

S2

Ci

F.A.

Co

S1

A0 B0
Ci

F.A.

Co

S0

Figure 8: Four Bit Adder Constructed from Full Adders

6 Preliminary Questions
1. Design a circuit to convert from a BCD (Binary Coded Decimal) to 631(-1) weighted code2 as
given in the following truth table. Assume that the input combinations not shown in the table
represent illegal BCD codes and can be treated as dont cares.
Minimize your design to minimize the number of gates. Look for product terms that can be shared
between the various outputs when you minimize. Use circuits consisting NAND gates to realize
your design. Draw the diagram of the circuit and include it with your preliminary questions.
2. Design a circuit to compare two two bit binary numbers and produce three outputs G, L and E
which indicate whether or not binary number 2 is Greater than, Less than or Equal to binary
number 1. The first number is represented by the input combinations A and B in the truth table
below, and the second number is represented by input combination C and D.
Use all NAND circuits to implement your minimized design. Hint, since you know every combination must an output of 1 in either G, L, or E, you can base the one of these on the values of the
other two. Draw the diagram of the circuit and include it with your preliminary questions.

7 The Lab
1. Implement your design from preliminary question #1 using the Xilinx ISE tools and perform a
functional simulation. Confirm that it matches the truth table. Turn in a sample waveform with
your report showing 4 different input combinations and the outputs. Download your design onto
the Digilab board and have your circuit passed off by the teaching assistant.
2

In a 631(-1) code the bits of the code have the weight 6, 3, 1, and -1.

COE/EE 244
Logic Circuit Lab

Lab #3; Page 9/9

Spring 2003

BCD
A B C
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0

D
0
1
0
1
0
1
0
1
0
1

E
0
0
0
0
0
1
1
1
1
1

631(-1)
F G
0 0
0 1
1 0
1 0
1 1
0 0
0 0
0 1
1 0
1 0

H
0
0
1
0
0
1
0
0
1
0

A
B
C
D

Code
Converter
Circuit

E
F
G
H

2. Implement your design from preliminary question #2 using the Xilinx ISE tools and perform a
functional simulation. Confirm that it matches the truth table. Turn in a sample waveform with
your report showing 4 different input combinations and the outputs. Download your design onto
the Digilab board and have your circuit passed off by the teaching assistant.
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

G L
0 0
0 1
0 1
0 1
1 0
0 0
0 1
0 1
1 0
1 0
0 0
0 1
1 0
1 0
1 0
0 0

E
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1