1

CMOS Digital Integrated Circuits

Ch6 CMOS Inverters:
Switching Characteristics
and Interconnect Effects I

2
CMOS Inverters Dynamic Analysis and Design
Goals
Understand the detail dynamic analysis of the
CMOS inverter.
Understand one set of design from CMOS
equations.
Understand the basic CMOS design process
using the CMOS static and CMOS design form
dynamic equations.
6.1 Introduction
3
CMOS Dynamic Analysis: Capacitance Model for CMOS
V
out
V
DD
V
in
Cgs,p
Cint
Csb,p
Cgs,n
Cgd,n
Cgd,p
Csb,n
Cdb,p
Cdb,n
Cg
FO
Fig. 6.1 Cascoded CMOS Inverter stages
4
CMOS Dynamic Analysis: Capacitance Model for CMOS
The aggregate capacitance driven by the output
node of a CMOS inverter is in detail working from
left to right,
C
load
= C
input
+ C
int
+ C
g
in which
C
input
= C
gd,n
+ C
gd,p
+ C
db,n
+ C
db,p
(intrinsic
component)
C
int
= interconnect capacitance
C
g
= thin-oxide capacitance over the gate area
(extrinsic component)
6
CMOS Dynamic Analysis: Delay-Time Definitions
PHL
VOH
V50%
VOL
Vin
t
idealized
step input
VOH
V50%
VOL
Vout
t
Vout
PLH
t0 t1 t2 t3
fall
V90%
V10%
t
rise
tA tB tC tD
V
50
%
= V
OL
+(V
OH
-V
OL
)/2
. = (V
OH
+V
OL
)/2

PHL
= t
1
-t
0

PLH
= t
3
-t
2

P
= (
PHL
+
PLH
)/2
V
10%
= V
OL
+0.1(V
OH
-V
OL
)
V
90%
= V
OL
+0.9(V
OH
-V
OL
)
fall = t
B
-t
A
rise = t
C
-t
D
Fig. 6.3
Fig. 6.4
7
CMOS Dynamic Analysis
Delay-Time Calculation (First Order Estimates)
The simplest approach of calculating the propagation
delay is based on estimating the average capacitance
current during charge down/up.
where
I
V V C
I
V V C
LH avg
OL load
PLH
HL avg
OH load
PHL
,
% 50
,
% 50
) (
) (

[ ]
[ ] ) , ( ) , (
2
1
) , ( ) , (
2
1
% 50 ,
% 50 ,
V V V V i V V V V i I
V V V V i V V V V i I
OL out OL in C out OL in C LH avg
out OH in C OH out OH in C HL avg
= = + = = =
= = + = = =
6.3 Calculation of Delay Times
8
CMOS Dynamic Analysis
Delay-Time Calculation (More Accurate)(1/4)
The propagation delay can be found more accurately by
solving the state equation of the output node. The current
flowing through C
load
is a function V
out
as

PHL
: PMOS is off. The equivalent circuit during high-to-
low output transition is
i i i
dt
dV
C n D p D C
out
out , ,
= =
V
in
nMOS
i
D,n
C
load
V
out
i i
dt
dV
C n D C
out
out ,
= =
V
in
V
out
i
C
i
D,p
i
D,n
Fig. 6.5
9
CMOS Dynamic Analysis: Delay-Time Calculation (2/4)
The nMOS operates in two regions, saturation and linear,
during the interval of
PHL
.
Saturation Region
i
D,n
=(k
n
/2)(V
in
-V
T,n
)
2
=(k
n
/2)(V
OH
-V
T,n
)
2
Plug i
D,n
into C
load
dV
out
/dt=-i
D,n
, and integrate both sides,
we get
t
1

-t
0
= 2C
load
V
T,n
/[k
n
(V
OH
-V
T,n
)
2
]
PHL
V
OH
=V
DD
V
50%
V
OH
-V
T,n
V
out
t
t
0
t
1
nMOS in saturation
nMOS in linear region
t
1

Fig. 6.6
10
CMOS Dynamic Analysis: Delay-Time Calculation (3/4)
Linear Region
i
D,n
= (k
n
/2)[2(V
in
- V
T,n
)V
out
- V
out
2
]
= (k
n
/2)[2(V
OH
- V
T,n
)V
out
- V
out
2
]
Plug i
D,n
into C
load
dV
out
/dt=-i
D,n
, and integrate both
sides, we have
Finally, since V
OH
=V
DD
and V
OL
=0, we have
, ,
, ,
4( )
2
ln 1
( )
T n DD T n load
n DD T n DD T n D
HL
D
P
V V V C
V V V V V

= +




PHL
VOH
V50%
VOH -VT,n
Vout
t
t
0
t
1
nMOS in saturation
nMOS in linear region
t
1

,
, 50%
4( )
ln
( )
DD T n load
n DD T n
V V C
V V V

'
1 1
t t
Fig. 6.6
11
CMOS Dynamic Analysis: Delay-Time Calculation (4/4)

PLH
: NMOS is off. The equivalent circuit during low-to-
high output transition is
With the similar way (t
0
t
1

t
1
0|V
T,p
|V
50%

saturation linear ), we can have

V
in
pMOS
i
D,p
C
load
V
out
V
DD
, ,
, ,
2 4( )
ln 1
( )
T p DD T p
load
p DD T p D D
L
D T p
P H
D
V V V
C
V V V V V

= +





12
CMOS Inverter Design
Design for Performance
Keep capacitance small
Increase transistor size
Watch out for self-loading!
Increase V
DD
6.4 Inverter Design with Delay Constraints
14
CMOS Inverter Design: Delay as a Function of V
DD
V
DD
increases
PHL
/
PLH
decreases. However,
the power consumption also increases.
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
DD
(V)

p
H
L
(
n
o
r
m
a
l
i
z
e
d
)
15
CMOS Inverter Design: Device Sizing (1/5)
2 4 6 8 10 12 14
2.
0
2.2
2.4
2.6
2.8
3.2
3.4
3.6
3.8
x 10
-11
S

p
(
s
e
c
)
3.0
Self-loading effect:
Intrinsic capacitances
dominate
(for fixed load)
16
CMOS Inverter Design: Device Sizing (2/5)
NMOS/PMOS Ratio
R = W
p
/ W
n
1 1.5 2 2.5 3 3.5 4 4.5 5
3
3.5
4
4.5
5
x 10
-11
R

p
(
s
e
c
)

PLH

PHL

P
17
CMOS Inverter Design: Device Sizing (3/5)
Self-Loading Effect
C
load
= C
gd,n
(W
n
) + C
gd,p
(W
p
) + C
db,n
(W
n
) + C
db,p
(W
p
) + C
int
+C
g
= f(W
n
,W
p
)
Using the junction capacitance expressions in Chapter 3, we have
C
db,n
= (W
n
D
drain
+x
j
D
drain
)C
j0,n
K
eq,n
+(W
n
+2D
drain
)C
jsw,n
K
eq,n
C
dp,n
= (W
p
D
drain
+x
j
D
drain
)C
j0,p
K
eq,p
+(Wp+2D
drain
)C
jsw,p
K
eq,p
Therefore, C
load
can be rewritten as
C
load
=
0
+
n
W
n
+
p
W
p
where

0
= D
drain
(2C
jsw,n
K
eq,n
+2C
jsw,p
K
eq,p
+x
j
C
j0,n
K
eq,n
+x
j
C
j0,p
K
eq,p
)+C
int
+C
g

n
= K
eq,n
(C
j0,n
D
drain
+C
jsw,n
)

p
= K
eq,p
(C
j0,p
D
drain
+C
jsw,p
)
small
18
CMOS Inverter Design: Device Sizing (4/5)
Therefore,
PHL
and
PLH
are
The ratio between the channel widths W
n
and W
p
is
usually dictated by other design constraints such as
noise margins and the logic inversion threshold.
Lets this transistor aspect ratio be defined as R
W
p
/W
n
. Then, the propagation delay can be
represented as
( )
( )
( )
( )
, ,
, ,
, ,
, ,
0
0
4
2
ln 1
4 2
ln 1
DD T n T n n
PHL
ox DD T n DD T n DD n
DD T p T p p
P
n n p p
n
n
LH
DD T p DD ox DD T p n
n p p
p
W W
W
W
V V V L
C V V V V V
V V V L
V V V C V V
W
W

= +

=
+ +


+ +

0
0
( )
( )
PHL
PLH
n p n
n
n
n
p p
p
p
R W
W
W
R
W

+ +

+ +




=
=
19
CMOS Inverter Design: Device Sizing (5/5)
As we continue increase the values of W
n
and
W
p
, the propagation delay will asymptotically
approach a limit value for lager W
n
and W
p
,
The propagation delay times cannot be
reduced beyond the above limits, and the
limit is independent of the extrinsic
capacitances.
( )
( )
limit
PHL
limit
P
n n p
n
p
H
p
L
R
R

=
=
+

20
CMOS Inverter Design: Impact of Rise Time on Delay

p
H
L
(
n
s
e
c
)
0.35
0.3
0.25
0.2
0.15

rise
(nsec)
1 0.8 0.6 0.4 0.2 0
( )
( )
2
(stepinput)
2
(stepinput)
2
2
2
2
PHL PHL
P
r
f
LH PLH

= +
= +
Propagation delay increases
since both PMOS and
NMOS are on during the
charge-up and charge-down
events.
21
CMOS Inverter Design
Impact of Channel Velocity Saturation
The drain current is linearly dependent on V
GS
I
sat
= W
n
(V
GS
-V
T
)
Propagation delay only has a weak dependence on the
supply voltage V
DD
( )
( )
50%
/2
load DD
n
load
PH
D T
L
sat
D
C V
W V
C V
I
V

22
CMOS Dynamic Analysis: Dynamic Power Dissipation (1/2)
The dynamic power dissipation can be derived as
follows.
P
dyn,avg
= V
DD
I
DD,avg
With I
DD,avg
taken over one clock period T. The
capacitance current which equals the current from the
power supply (assuming I
Dn
= 0 during charging) is
Rearranging and integrating over one clock period T
Gives
I
DD,avg
T = C
load
V
DD
dt
dV
C I
out
load D
=

=
V
out load
T
D
DD
dV C
dt
I
0 0
23
CMOS Dynamic Analysis: Dynamic Power Dissipation (2/2)
Solving for I
DD,avg
and substituting in P
avg
:
In terms of SPICE simulation, the authors offer
a circuit called power meter.
It should be noted here the our simple Cload
may underestimate the power dissipated.
In terms of SPICE simulation, it offers a circuit
called power meter.
f
V C V C
T
P
DD load DD load avg
2 2
1
= =
24