Guide to the CMPEN 411 Lab and Cad tools

1. Introduction
The objective of this tutorial is to give you an overview to (1) setup the Cadence and Synopsys hspice tools for your
account in IST 218 ab! (2) use the sche"atic editor! (#) use the hspice tool! (#) use the chip layout editor $ Cadence
%irtuoso! and (&) use '(C! )*tract! %S tools+ This guide "ay be updated as needed during the se"ester+
2. Set up the tool environment
,efore you can start using design tools! there are a few configuration files needed in your wor-ing directory+ These files
deter"ine the environ"ent in which tools run! and what libraries are to be included in your designs+ The setup given
below is for ./I0 "achines in ab 218+ So"e ./I0 co""ands will be included in this tutorial+ 1lease be fa"iliar with
basic ./I0 co""ands to wor- efficiently+
Step1.
ogin to a "achine in roo" 218 IST ,uilding+ ,ring up a ter"inal window where you can type a ./I0 co""and+ Then
type the following2
3 4ho"e4faculty4-yusun4c&114bin4class&11setup
This setup needs to be done only once for this se"ester+
/ow for the setup to ta-e effect! you logout and login again+
Step 2.
5a-e your own wor-ing directory for C51)/ &11 class+ I "ade2
3 "-dir c&11
The 6c&117 is the na"e of your wor-ing directory+ 8ou can use any na"e you li-e+
Step.
Change your current directory to c&11 by typing2
3 cd c&11
8ou need to set up your directory for the C9' tool use+ So type2
3 runcds
This co""and needs to be done only once for this se"ester and all the subdirectories created by the Cadence tool is
covered+ (If you want to do your %SI design in another directory later in the se"ester! you would need to 6cd7 to that
directory and do 6runcds7 once for that directory+)
/ow start the Cadence tool by typing the following2
3 virtuoso :
Then the CI; (Co""and Interpreter ;indow) and the library "anager should pop up+
<igure 1a CI; ;indow
<igure 2b CI; ;indow with proper starting! ibrary 5anager pops up
<igure 1c ibrary "anager
<igure #d CI; ;indow with /=T proper starting! ibrary 5anager does /=T pops up
If you see the ibrary 5anager on your screen! your set up is proper+ If you do /=T see the ibrary 5anager and see the
>?;9(/I/@?A "essage in CI; window! your set up is not proper! you can still use Cadence %irtuoso tool and do the wor-
but you need to see the lab$support staffs in roo" 111 IST ,uilding to update your account+ 8ou need to also send e"ail
to2
helpdes-Bcse+psu+edu
Step4. !ptional " connectin# to the Lab 21$ IS% machines &rom home or campus
8ou can connect to the ab 218 IST "achines fro" ho"e ;indows 1C and do the %SI design wor- at ho"e+ 8ou will
need the following2
%1/ $ http244 downloads+its+psu+edu
SSC $ http244 downloads+its+psu+edu
1lus you will need one of the following 011 clients running on your ;indows 1C2
0"ing
0"anager
0win#2
)*ceed fro" Cu""ingbird
cygwin
=nce you have the above progra"s installed on your ;indows 1C! follow the steps below to connect to the ab 218 IST
"achines2
(un %1/! set >IS1 to 1S.A
(un 011 client progra"
(un ssh! login one of the following "achines2
alderaan dra'h lumati romulan
alphan dra(i melma' scalosian
andorian #alli&re) metron taelon
beta(ed #amalon minbari tamaria
bor# horta moni'an tholian
breen invid narn ubese
cardassian 'a(on pa'led venticar
centauri 'lin#on planet1* vo#on
c)lon 'ronos protoss +oo'ie
de#obah 'r)pton raisa (er#
'ouble clic- on the ssh shell to start the ssh+
Clic- on the >SettingsA and be sure to chec- on the >Tunnel 011 connectionA as shown below+
=nce the ssh shell started! clic- on >Duic- ConnectA and type the followings! for e*a"ple2
Cost /a"e2 alderaan+cse+psu+edu
.ser /a"e2 yourEcseEuserEid
1ort /u"ber2 22
9uthentication 5ethod2 1assword
=nce you are logged$in! type >*cloc- :A to see if 011 is properly wor-ing+ 8ou will see a new cloc- on your screen+
=therwise 011 is not wor-ing+
. ,or'in# +ith Cadence tool - virtuoso
.sing the Cadence tool! the overall %SI chip design flow can be outlined as follows2
1+ Sche"atic design and entry F transistors! sy"bols! input pins! output pins vdd pin! and gnd pin
2+ Sche"atic chec- F chec- and save
#+ Sche"atic spice netlist file creation
&+ Cspice si"ulation of the netlist file fro" the sche"atic
G+ Sche"atic sy"bol creation
H+ ayout design and entry F p"os! n"os! ptap! /T91! input pins! output pins! vddI pin! and gndI pin
J+ ayout '(C ('esign (ule Chec-)
8+ )*traction of circuits fro" the layout including parasitic ele"ents
K+ Spice netlist file creation fro" the layout$e*tracted circuit
1L+ Cspice si"ulation of the spice netlist file fro" the layout$e*tracted circuit
11+ %S (ayout %ersus Sche"atic) chec-ing F co"parison of the layout e*tracted circuit with the sche"atic
So"e useful tutorials posted at2
http244users+ece+gatech+edu4"ooney4cadence4lab14lab1+ht"l
http244www+ee+siue+edu4Mcdsad"in4tutorial+ht"
http244www+ee+virginia+edu4M"rs8n4cadence4tutorial1+ht"l
http244www+ee+virginia+edu4M"rs8n4cadence4tutorial2+ht"l
http244webster+engr+pitt+edu4electrical4faculty$staff4levitan411K24inde*+ht"l
8ou "ay also google yourself to find what you want to -now about the Cadence tool+
4. Generate schematic
;e use latest Cadence tool! however the al"ost all the older Cadence sche"atic and layout editing tool procedures are
the sa"e+ In this section! we will create our own library and generate a sche"atic of inverter+
Step1.
Create a library that holds all our designs na"ed "ylib+
In the CI; window!
a) Select <ile $N /ew $N ibrary+
b) )nter the library na"e "ylib+
c) Select the option 9ttach to an e*isting technology library+
<igure & Create a library
d) 1ress =O! another window will pop up+ Choose the library /CS.ETechlibEai"LH and press =O+ Then! a library using
the 9I5 L+Hu" technology is created+
<igure G 9ttach the e*isting library+
Step2.
Create a new sche"atic view of inverter+
a) Select <ile $N /ew $N Cellview+
b) Choose "ylib and enter the cell na"e inv in the pop$up window+
<igure H Create a new she"atic
Sche"atic editor will pop up+
<igure J Start the sche"atic editor
Create instance of n"os&4p"os& fro" the analogib library+
=n the sche"atic editor! select Create $N Instance or use toolbar +
Choose library /CS.E9nalogE1arts in the pop$up Co"ponent ,rowser window+
Choose p"os& fro" the 1ETransistors directory+
<igure 8 Co"ponents ,rowser
Then! the 9dd Instance window will pop up as the following figure+ eave all para"eters as default+ Then! place the
p"os& instance+ Si"ilarly! place n"os&! gnd and vdd+ /ote that the gnd and vdd are under the directory of SupplyEnets +
9fter placing an instance! press 6)SC7 to e*it the placing "ode+
<igure K p"os& instance

<igure 1L vdd instance
Create $N 1in or use toolbar + Choose appropriate direction+
<igure 11 9dd pin
9dd wire to the source of n"os&4p"os&! pin! etc to connect the" together+ 8ou can select Create $N ;ire (narrow) or use
toolbar +
Chec- the design+ Select Chec- $N Current Cellview to chec- the design+ )rrors will be displayed in the CI;+ Correct any
errors+
8ou can find further instruction fro" 6Celp7 option in CI;+ There are "any detailed tutorials in this option+
.. Generate netlist &rom the schematic and simulate it +ith /SPICE
Step1.
=pen the sche"atic view of inverter+
Step2.
Select aunch $N 9') ! the 9nalog 'esign )nviron"ent window pop up+
<igure 12 9') ;indow
Step.
Select Setup$N5odel libraries! add two "odels 6a"iLH/7 and 6a"iLH17 fro" ncsu4"odels4hspice4public4public5odel4
<igure 1# 9dd "odels
Step4.
Select Si"ulation$N/etlist$NCreate to generate the following netlist2
<igure 1& @enerated netlist window
Step..
;ithout any changes! Save the file as inv+s using the <ile $N Save 9s "enu+ /ow you "ust create inv+hsp file with the
following content2
%'' G+L
CO G+L
(IS) L+1
<9 L+1
in L1L1L
++cload out L 2Lf<
8ou "ay use any te*t editor of your choice+ Save the file+
Then type 6hspGL inv7 to create 6inv+sp7 file+ ,oth 6inv+s7 file and 6inv+hsp7 file are co"bined into the 6inv+sp7 file+
Step0.
/ow hspice si"ulate your sche"atic netlist using the following co""and2
3 hspice inv+sp
,e sure to read the hspice output! it "ust say it co"pleted and not aborted+ The tpd value in the result is the propagation
delay of the inverter+ =nce the hspice is successfully co"pleted! you can see the input and output wavefor"+ Type the
following co""and2
3 sc inv+trL :
Choose the inv+trL fro" the =utput %iew window of the SpiceChec- (sc) window and e*pand it+ Then select 6in7 and 6out7
signals! drag the" to the ;aveview window+ 8ou "ay e*plore other features of the SpiceChec- progra" to "easure the
signal statistics+
0. Generate la)out
In this section! we will draw the layout view of the inverter+ 9 layout describes the "as-s fro" which your design will be
fabricated+ The layers in a layout describe the physical characteristics of the device and have "ore details than a
sche"atic+ Therefore! layout verification of your design is critical+ There are two types of layout design2 <ull$Custo" and
9uto"ated+ <ull$custo" layout is when the user physically draws all of the layers for the individual transistor+ This is a very
tedious process! but it usually enables results in a co"pacter design than the auto"ated process+ The auto"ated
process! on the other hand! is done by instantiating standard cells (reusing basic bloc-s) and usually ta-es "ore area but
it is "uch faster+ ;e only introduce custo" layout design here+
8ou should follow 5=SIS SC5=S design rule for 9I5 L+HP"2
http244www+"osis+co"4Technical4'esignrules4sc"os4sc"os$"ain+ht"l
The inverter consists of three parts $$ p$transistor! n$transistor! and connections+
0.1 Generate la)out +ith macro in the librar)
Step1.
Create a layout view for the inverter+
a) Select <ile $N /ew $N Cellview+
b) Choose "ylib! select the cell na"e inv! and select layout view+
<igure 1G Create layout view
c) Clic- =O+ S; and ayout )ditor windows will pop up as shown below+
d) /e*t! Setting 'isplay 1ara"eters2
Select =ptions $N 'isplay+
Set the following options2 (1) 1in na"es2 =n (2) 'isplay levels2 <ro"2 L To2 2L
<igure 1H Set display
Step2.
Create a instance of p"os transistor+
1+ Select Create$Ninstance+ Then clic- on the ,rowse++ button+ ;ait for the ibrary ,rowser to pop up+
2+ In the ibrary ,rowser! Choose /CS.ETechibEa"iLH! select the cell na"e p"os! and select layout view+
#+ 1lace the p"os in the layout editor and get the following layout2
<igure 1J p"os instance
Step.
1lace a n"os as in step2+
Step4.
'raw the gnd ne*t to the /"os
1+ Select the pselect layer fro" the S; windowQ we will draw the pselect enclosing the substrate (connected to the gnd)
contact for the / transistor
2+ Select the Create$N(ectangle
#+ 'raw the pselect on the cellviewQ it will have to enclose the contact p$active by at least L+H+The pselect abuts directly to
the nselect of the / transistor! but they should not overlap+
&+ Select the pactive layer fro" the S; window
G+ 'raw the pactive island on the cellview to be 1+2 wide by 1+G tallQ it "ust be enclosed by the pselect by L+H+
H+ 9dd contacts in the center of the substrate$contact island+
Step..
'raw the %dd ne*t to the n"os as in the previous step+
Step0+
1+ Connect the source of p$transistor to the well$contact using the "etal 1 layer+
2+ Connect the source of n$transistor to the substrate$contact with the "etal 1+
#+ 9dd a contact to the gate (poly)
<igure 18 ayout of inverter
0.2 Generate la)out la)er b) la)er
Step1.
Sa"e as step1 in &+1
Step2.
ayout of 1$transistor with RL+HP" and ;R1+G P"+
Since we are using the /well process technology! the substrate will be p$substrate+
;e will create a p"os transistor first+ To do that we need an /well in which the p"os
transistor will be for"ed+
a) 'raw the well
1Select the n$well layer fro" the S; window
2+ Select the Create$N(ectangle (or use hot-ey ()+
#+ 'raw the n$well on the cellview to be J+2 wide by J+2 tall+

b) 'raw the p$ select regions for the p transistor
1+ Select the pselect layer fro" the S; windowQ we will draw the pselect enclosing the transistor
2+ Select the Create$N(ectangle+
#+ 'raw the pselect on the cellviewQ &+8 wide and 2+J tallQ its eft$ and
(ight$edges should be L+H away fro" well edges+ The pselect should be placed within the n$well! even if the siSe should
vary (you can use the )dit$N"ove or hot-ey " co""and to "ove the layer) +
c) 'raw 'iffusions
1+ Select the pactive layer fro" the S; windowQ draw the active region of the p$device with siSe 1+G 0 #+H
2+ 9dd a contact in the center of the well$contact island with the siSe L+H 0 L+H
d) Si"ilarly! draw the n"os transistor and connect the"+
e) 'raw the substrate$contact as in step & of &+1+
f) 'raw "etal Connections as in step H of &+1 and get the sa"e layout as in figure 1&+
Step.
'raw the vdd and gnd as in section G+1+
0. 12C rule chec'.
'(C is used to chec- that all process$specific design rules (such as spacing) have been "et+ There are process$specific
design rules that describe how close layers can be placed together and what the siSes of the areas can be+ These rules
are giving the "ini"u" reTuire"ent to avoid a catastrophic failure of your circuit due to fabrication faults+ 8ou can use the
following 5=SIS SC5=S design rules as a guideline+ The design rules are different for different processes+
In the layout editor! select %erify$N '(C
<igure 1K '(C
If your design has violated any design rules! '(C will reports the errors in the CI;+
)rrors are indicated by the "ar-ers (white color) on the circuit+ 8ou "ay then proceed to correcting the errors according
to the design rules+ <or huge layouts! the "ar-er "ight not be easily located+ To find "ar-ers! choose %erify $N
5ar-ers $N <ind in layout window+
9 pop$up "enu will appear+ Select on the Uoo" to 5ar-ers bo*+
Clic- on the 9pply button and Cadence will Soo" in to the errors or warnings as desired+
3. Generate netlist &rom the la)out and simulate it +ith /SPICE
Step1.
=pen the layout view of inverter+
Step2.
@et the e*tracted view of the layout2
Select %erify $N )*tract
Clic- the Set Switches button+
Select )*tractEparasiticEcaps option+ If you use capacitors or resistors! li-e in "any
analog applications! select )*tractEcap and )*tractEresistor also+
Step
=pen the e*tracted file+ =pen $N cell na"e2 "yEinv $N view na"e2 e*tracted+ 8ou will
see a e*tracted view2
<igure 2L )*tracted %iew
Step4.
Si"ilar to section &! Select aunch $N 9') ! and select "odels
<igure 21 9') ;indow
Select Setup$N5odel libraries! add two "odels 6a"ioH/7 and 6a"iLH17 fro" ncsu4"odels4hspice4public4public5odel4
<igure 22 9dd "odels
Step..
Select Si"ulation$N/etlist$NCreate to generate the following netlist+ Co"pare with that in section &+
<igure 2# @enerated netlist window
Step..
Save the file as invElayout+s using the <ile $N Save 9s "enu+ /ow you "ust create invElayout+hsp file with the following
content2
%'' G+L
CO G+L
(IS) L+1
<9 L+1
in L1L1L
++cload out L 2Lf<
8ou "ay use any te*t editor of your choice+ Save the file+ Then type 6hspGL inv7 to create 6invElayout+sp7 file+ ,oth
6invElayout+s7 file and 6invElayout+hsp7 file are co"bined into the 6invElayout+sp7 file+
Step0.
/ow hspice si"ulate your sche"atic netlist using the following co""and2
3 hspice invElayout+sp
,e sure to read the hspice output! it "ust say it co"pleted and not aborted+ The tpd value in the result is the propagation
delay of the inverter+ =nce the hspice is successfully co"pleted! you can see the input and output wavefor"+ Type the
following co""and2
3 sc invElayout+trL :
Choose the invElayout+trL fro" the =utput %iew window of the SpiceChec- (sc) window and e*pand it+ Then select 6in7
and 6out7 signals! drag the" to the ;aveview window+ 8ou "ay e*plore other features of the SpiceChec- progra" to
"easure the signal statistics+
The tpd value in the result is the propagation delay of the inverter+ Co"pare with the result fro" section &+
$. Create s)mbol vie+ and #enerate la)out &rom the s)mbol
Step1. Create the symbol from the schematic
Open the schematic view of inverter, and choose Create->Cellview->From Cellview
Keep the default set up and create the symbol view of inverter.
Step2. @enerate layout fro" the sy"bol
Create a new schematic view and add create two instances of inverters symbols.
In the schematic view window, select Launch->Layout XL. We will see the X !ditor and two
layout instances in the ri"ht window. #ote that you should connect the two layout of inverters
with $etal% layer manually &the automatic layout "enerator doesn't create wire connections(.
4. L5S
)he *+ rule chec, is to verify the consistence between the layout and the schematic. )he layout
should veri-ed before the further simulation.
+ince now we have already "ot the schematic and extracted views of inverter. We could do the
*+ chec, with the extracted view. Open the extracted view and choose Verify->LVS, the
followin" window will pop up. .e/select the rule library and input the *+ Rule fle
0home0faculty0,yusun0c1220ncsu/cd,/2.3.4.beta0tech-le0diva*+.rul
5i"ure %1 *+
6ress R!. If the layout is consistent with the schematic, we could "et the followin" promotion7
5i"ure %8 *+ succeeded
It means that the *+ process succeeded, but it doesn't mean that the schematic and layout
match each other. 6lease choose !rror .isplay from the *+ panel to see whether there are
errors. 9ere is an e:ample, let's -rst ma,e a mista,e in the layout of the inverter as shown in the
followin" -"ure and e:tract it.
5i"ure %3 ayout mismatch
;fter doin" the *+ and chec, errors, we could "et si: errors &actually they are all caused by the
disconnection mismatch(, shown as in the followin" -"ures. <ou could =oom to the problem place
and -nd that the problem is hi"hli"hted &pin, part(. )hen, you can -: the problem.
5i"ure %> *+ !rror .isplay
.isconnection
mismatch
5i"ure %? *+ !rror 9i"hli"ht