7 views

Uploaded by GECM85

- CS-303-Unit-II.pdf
- Design & Performance Analysis of 8-Bit Low Power Parity Preserving Carry-Look Ahead Adder
- Dc Detector
- 4 Bit Bcd Adder Abstract
- digital
- CS6211 Digital manual.pdf
- Rain Sensor (ECE 403) Documentation
- Dc Versus AC
- QCA Binary Adder Implementation on FPGA
- Design of QSD Multiplier Using VHDL
- simpson task4b mals
- hw5sol
- Ch12_Datapath
- Vlsi Implementation of 32
- l6_2 [Compatibility Mode].pdf
- End of Year Test Grade2
- week 8 20 2012 lessons and assignments
- Printscreen Tugas Pak San
- Max 5069
- Lfr

You are on page 1of 8

AIM: To design and implement 4-bit adder, subtractor and BCD adder using IC 7483.

APPARATUS REQUIRED:

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It

can be constructed with full adders connected in cascade, with the output carry from each full

adder connected to the input carry of next full adder in chain. The augends bits of A and the

addend bits of B are designated by subscript numbers from right to left, with subscript 0

denoting the least significant bits. The carries are connected in chain through the full adder.

The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data

input B and the corresponding input of full adder. The input carry C0 must be equal to 1

when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common

binary adder. The mode input M controls the operation. When M=0, the circuit is adder

circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an input carry

from a previous stage. Since each input digit does not exceed 9, the output sum cannot be

greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must

be represented in BCD and should appear in the form listed in the columns.

ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,

together with the input carry, are first added in the top 4 bit adder to produce the binary sum.

EC GEC, MODASA

EC GEC, MODASA

EC GEC, MODASA

EC GEC, MODASA

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit adder, subtractor and BCD adder using IC 7483 was designed and

implemented.

EC GEC, MODASA

EXPERIMENT NO. 5: DESIGN AND IMPLEMENTATION OF

MAGNITUDE COMPARATOR

AIM: To design and implement

(i) 2 bit magnitude comparator using basic gates.

(ii) 8 bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

THEORY:

The comparison of two numbers is an operation that determines if one number is greater than,

less than or equal to the other number.

A magnitude comparator is a combinational circuit that compares two numbers A and B and

determines their relative magnitudes. The outcome of comparison is specified by three binary

variables that indicate whether A>B, A=B or A<B.

Consider two numbers A=A

3

A

2

A

1

A

0

and B=B

3

B

2

B

1

B

0

where each subscripted letter

represents one of the digits in the number.

Two numbers are equal if all pairs of significant digits are equal i.e. A

3

=B

3

, A

2

=B

2

, A

1

=B

1

and A

0

=B

0

.

To determine if A is greater than or less than B, we inspect the relative magnitudes of pairs of

significant digits starting from the most significant position. If two digits are equal we

compare the next lower significant pair of digits. This comparison continues until a pair of

unequal digits is reached. If the corresponding digit of A is 1 and that of B is 0, we conclude

that A>B. If the corresponding digit of A is 0 and that of B is 1, we have A<B.

EC GEC, MODASA

EC GEC, MODASA

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the 2 bit magnitude comparator using basic gates and 8 bit magnitude comparator

using IC 7485 was designed and implemented.

- CS-303-Unit-II.pdfUploaded byRaja Kushwah
- Design & Performance Analysis of 8-Bit Low Power Parity Preserving Carry-Look Ahead AdderUploaded byEditor IJRITCC
- Dc DetectorUploaded byikaro181083
- 4 Bit Bcd Adder AbstractUploaded bySrinivas Srinu
- digitalUploaded byawesomejk
- CS6211 Digital manual.pdfUploaded byDeiva Sigamani
- Rain Sensor (ECE 403) DocumentationUploaded byAlissajyn Calzita
- Dc Versus ACUploaded byJandric Nebojsa
- QCA Binary Adder Implementation on FPGAUploaded byIOSRjournal
- Design of QSD Multiplier Using VHDLUploaded byEditor IJRITCC
- simpson task4b malsUploaded byapi-270858573
- hw5solUploaded byVinh Cuong
- Ch12_DatapathUploaded byRajesh Bathija
- Vlsi Implementation of 32Uploaded byAli Baig
- l6_2 [Compatibility Mode].pdfUploaded byMohammad Muntasir Hassan
- End of Year Test Grade2Uploaded byAbdul Manaf
- week 8 20 2012 lessons and assignmentsUploaded byapi-166838519
- Printscreen Tugas Pak SanUploaded byMandjah Sheo
- Max 5069Uploaded byh1169104
- LfrUploaded byOjibwe Unanimes
- curriculum topic study pbiUploaded byapi-204175754
- Math Made a Bit Easier Lesson Plans: A Guide for Tutors, Parents, and HomeschoolersUploaded byLarry Zafran
- problem solving lessonUploaded byapi-317248075
- VHDL Digital Full ADDER Logic Using NAND Gate ProgramUploaded byPreeti Budhiraja
- Cpu Ch04 Irv EnglanderUploaded byDina Cordeiro
- Complex Number Algebra SoftwareUploaded byGoldenKstar
- Pro-face Direct Access Communication.pdfUploaded byRata Ion
- Low Power CMOS AD ConvertersUploaded byguitarfrido
- edu 465 - order of operations with fractionsUploaded byapi-242348832
- Complex Number Algebra SoftwareUploaded byGoldenKstar

- Microstrip AntennaUploaded byGECM85
- Ansoft HFSS Online HelpUploaded byCu Liều
- Ansoft HFSS Online HelpUploaded byCu Liều
- A novel dual frequency triangular microstrip patch antenna with one slot.pdfUploaded byGECM85
- Getting Started With HFSSUploaded byGECM85
- Electromagnetics 2nd John D.KrausUploaded byMohammed Nour
- MTech_RF_Syllabus.pdfUploaded byGECM85
- Countries CapUploaded byShobhit Rastogi
- Triangular Microstrip AntennaUploaded byGECM85
- Waveguide Paper-3.pdfUploaded byGECM85
- Waveguide Paper-4.pdfUploaded byGECM85
- hfssUploaded byRahul Agarwal
- Rectangular Waveguide Design Using HFSSUploaded byGECM85
- B Tech Project ReportUploaded byPulakhamdam Vidhya Sagar Reddy
- B Tech Project ReportUploaded byPulakhamdam Vidhya Sagar Reddy
- Coxial Line Analysis Using HFSSUploaded byGECM85
- Waveguide Propagation.pdfUploaded byGECM85
- Smith ChartUploaded byapi-3831995
- PE-Lab Manual-3.pdfUploaded byGECM85
- PE-Lab Manual-2.pdfUploaded byGECM85
- CylindricalWaveguideUploaded byamithabhm
- Coax-1Uploaded byGECM85
- VIMAL Researchpaper Mode Patterns of Parallel Plates &Rectangular Wave GuidesUploaded byYogesh Meena
- Microstrip_Stripline_and_CPW_Design.pdfUploaded byGECM85
- Gupta Et Al. 1996 - Microstrip Lines and Slotlines. 2nd Ed.Uploaded bysolervi
- 0712ijdps05.pdfUploaded byanjugadu
- Planar Transmission Lines.pdfUploaded byGECM85
- 2161006Uploaded byGECM85
- PSpice ExamplesUploaded byshatila
- Coax-1Uploaded byGECM85

- 4229961Uploaded bykamalmatsaid
- Casio CTK-750 Service ManualUploaded byFelix Vega
- viyerUploaded byArne1234
- 722.file_ref.811.1632.pptUploaded byYassineZkl
- Panel Chimei Innolux v236bj1-Le1 0 [Ds]Uploaded byFabián Adhémar Dutra
- Samsung Un40eh6000fxza Owners ManualUploaded byyoursdhansh
- AtmUploaded bySebastin Ashok
- ch05Uploaded bySobhagya Mohanty
- Eee41 Dc3 More Diode CircuitsUploaded bybravotolits
- SADIBA Recommendation on DTT MigrationUploaded byjbl140
- BBC Micro Service Manual 1985Uploaded byDave
- DC Test TheoryUploaded bySrivatsava Guduri
- slot antennas material.pdfUploaded byAjayaHS
- A Zener Diode by Muhammad Arif RattarUploaded byMuhammad Arif Rattar
- Wireless High Receiver 1100XH-WUploaded byJose Duran
- Inventory List - as of Sept 2018Uploaded byTanti Outsider
- The Truth About Arc DetectionUploaded byErman
- APPLICATIONS OF RELAYS IN ELECTRONIC CIRCUITSUploaded byBrent Smith
- L165VUploaded byapi-3825669
- Transmission Line Applications in p SpiceUploaded byFrancesco Cordella
- PCB ModificationsUploaded byCharleen Boodhai
- 309220Uploaded byTariq Waseem
- (CHAPTER+6-10)+SINGLE+û+SIDEBAND+COMMUNICATIONS+SYSTEMS(41-70)Uploaded byRalph Reyes Santelices
- Chapter-1_Introduction_to_Laser_Security.docxUploaded byLucky Lucky
- Harmful x86Uploaded bynpssg
- PIC ProgrammerUploaded bydardaryu
- R30D Drehwinkelaufnehmer EnUploaded byJay R SV
- E-Paper ESL Tag 2 Inch GDE0210C1 SpecificationUploaded bycdxhg11
- Manan Dcs PptUploaded bymridulparikh
- gskUploaded bysrimallikarthik