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GEC 2000 Tutorial

10 Gigabit Ethernet Physical Layer


Presented by: Rich Taborek, Corp.
2500-5 Augustine Dr., Santa Clara, CA 95054; 408-845-6102; rtaborek@nserial.com
Presentation Material derived from:
IEEE 802.3ae Task Force
10 Gigabit Ethernet Alliance
n n
n n
n n
n n
Serial Serial
10 GbE Physi cal GEC 2000 Tutorial
Tutorial Agenda
Introduction to the 10 GbE Physical Layer
Layered Model
MAC/PHY Interfaces
Physical Coding Sublayer - Coding
Physical Medium Attachment - Signaling
Physical Medium Dependent - Opto-Electronics
UniPHY Overview
Alternative Ethernet WAN Support
Acknowledgements
10 GbE Physi cal GEC 2000 Tutorial
Introduction to 10 GbE Physical
10 GbE is a supplement to an existing standard
Target completion date: March 2002
Purpose:
1. Extend 802.3 protocol to 10 Gbps
2. Expand the Ethernet application space to WAN links
3. Maintain compatibility with the 802.3 installed base, previous
investment in R&D, and principles of network operation and
management.
Scope:
1. Define Physical layer characteristics and management parameters
for transfer of LLC and Ethernet format frames at 10 Gbps using
full duplex operation as defined in the 802.3 standard.
2. Add features that enable deployment of Ethernet over the WAN
including SONET
10 GbE Physi cal GEC 2000 Tutorial
PHY Related Objectives 1 of 2
Preserve the 802.3/Ethernet frame format
Preserve 802.3 minimum and maximum Frame Size
Support full-duplex operation only
Support star-wired local area networks using point-to-point
links and structured cabling topologies.
Specify an optional Media Independent Interface (MII).
Support a speed of 10 Gbps at the MAC/PLS
Define a LAN PHY, operating at a data rate of 10 Gbps
Define a WAN PHY, operating at a data rate compatible
with the payload rate of OC-192c/SDH VC-4-64c
u Define a mechanism to adapt the MAC/PLS data rate to the data
rate of the WAN PHY
10 GbE Physi cal GEC 2000 Tutorial
PHY Related Objectives 2 of 2
Provide Physical Layer specifications which support link
distances of:
u At least 100 m over installed MMF
u At least 300 m over any MMF
u At least 2 km over SMF
u At least 10 km over SMF
u At least 40 km over SMF
Support fiber media selected from the second edition of
ISO/IEC 11801
u 802.3 to work with SC25/WG3 to develop appropriate
specifications for any new fiber media
10 GbE Physi cal GEC 2000 Tutorial
802.3 Layer Model to 1 GbE
PHYSICAL
DATA LINK
NETWORK
TRANSPORT
SESSION
PRESENTATION
APPLICATION
OSI
REFERENCE
MODEL
LAYERS
PMA
PLS
PMA
PLS
Reconciliation
PMD
PMA
PCS
Reconciliation
PMD
PMA
PCS
Reconciliation
MAC
MAC CONTROL (Optional)
LLC
MEDIUM MEDIUM MEDIUM MEDIUM
AUI
MAU
PHY
MII GMII
MDI MDI MDI MDI
AUI
MII
LAN
CSMA/CD
LAYERS
HIGHER LAYERS
AUI = Attachment Unit Interface
MDI = Medium Dependent Interface
MII = Media Independent Interface
GMII = Gigabit Media Independent Interface
MAU = Medium Attachment Unit
1 Mb/s, 10 Mb/s 10 Mb/s 100 Mb/s 1000 Mb/s
PLS = Physical Layer Signaling
PCS = Physical Coding Sublayer
PMA = Physical Medium Attachment
PHY = Physical Layer Device
PMD = Physical Medium Dependent
10 GbE Physi cal GEC 2000 Tutorial
802.3 Proposed 10 GbE Layer Model
PHYSICAL
DATA LINK
NETWORK
TRANSPORT
SESSION
PRESENTATION
APPLICATION
OSI
REFERENCE
MODEL
LAYERS
Reconciliation
MAC
MAC Control (Optional)
LLC
XAUI
LAN
LAYERS
HIGHER LAYERS
MDI = Medium Dependent Interface
XGMII = 10 Gigabit Media Independent Interface
XAUI = 10 Gigabit Attachment Unit Interface
PCS = Physical Coding Sublayer
XGXS = XGMII Extender Sublayer
PMA = Physical Medium Attachment
PHY = Physical Layer Device
PMD = Physical Medium Dependent
PMD
MEDIUM
MDI
XGXS
XGMII
PMA
PCS
XGXS
10 GbE Physi cal GEC 2000 Tutorial
MAC/PHY Interfaces - XGMII/XAUI
PHYSICAL
DATA LINK
NETWORK
TRANSPORT
SESSION
PRESENTATION
APPLICATION
OSI
REFERENCE
MODEL
LAYERS
Reconciliation
MAC
MAC Control (Optional)
LLC
XAUI
LAN
LAYERS
HIGHER LAYERS
MDI = Medium Dependent Interface
XGMII = 10 Gigabit Media Independent Interface
XAUI = 10 Gigabit Attachment Unit Interface
PCS = Physical Coding Sublayer
XGXS = XGMII Extender Sublayer
PMA = Physical Medium Attachment
PHY = Physical Layer Device
PMD = Physical Medium Dependent
PMD
MEDIUM
MDI
XGXS
XGMII
PMA
PCS
XGXS
10 GbE Physi cal GEC 2000 Tutorial
Implementation Example
TXC
TXD
RXC
RXD
PHY
MAC RS
36
36
XAUI
XGMI I
X
G
X
S
MDI
XGXS
P
C
S
P
M
A
P
M
D
Big Chip
Little
Chip
Transceiver
Form Factor varies
from daughter card
to small-form-factor
Management
MDC
MDI O
Management
10 GbE Physi cal GEC 2000 Tutorial
XGMII 1/4
eXtended Gigabit Media Independent Interface
Tx: 32 data bits, 4 control bits (one per byte), one clock
Rx: 32 data bits, 4 control bits (one per byte), one clock
Dual Data Rate (DDR) signaling, with data and control
driven and sampled on both rising and falling clock edges
Control bit per byte:
u Allows use of embedded delimiters rather than discrete signals
u Allows interface to be scaled in speed and width
10 GbE Physi cal GEC 2000 Tutorial
XGMII 2/4
Control bit (C) is 1 for delimiter and special characters
Control bit (C) is 0 for normal data characters
Delimiter and special character set includes:
u IDLE: Signaled in the absence of data and IPG
u SOP: One byte duration at start of packet
u EOP: One byte duration at end of packet
u ERROR: Signaled upon received error or when an error needs to
be forced into the transmit signal
Delimiters and special characters are distinguished by the
value of the 8 bit data bundle when the corresponding
control bit is 1
10 GbE Physi cal GEC 2000 Tutorial
XGMII 3/4
10 GbE Physi cal GEC 2000 Tutorial
XGMII 4/4
XGMII can be scaled in speed and width
u 32 data bits, 4 control bits
u 16 data bits, 2 control bits
u 8 data bits, 1 control bit
Stub Series Terminated Logic for 2.5 Volts
u SSTL_ 2
u EIA/ JEDEC Standard EIA/ JESD8- 9
u Class I (8 ma) output buffers
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS
XAUI: 10 Gigabit eXtended Attachment Unit Interface
XGXS: XGMII eXtender Sublayer
Based on original Hari proposals
CDR-based, 4 lane serial, self-timed interface
3.125 Gbaud, 8B/10B encoded over 20 FR-4 PCB traces
PHY and Protocol independent scalable architecture
Convenient implementation partition
May be implemented in CMOS, BiCMOS, SiGe
Direct mapping of Reconciliation Sublayer to/from PCS
Both XGMII and XAUI/XGXS are optional
u Neither, either or both may be implemented
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS Applications
Increased XGMII reach
Low pin count interface = implementation flexibility
Ease link design with multiple jitter domains
Lower power consumption re: XGMII
Common transceiver module interface
u Enables small form factor transceivers
PCS/PMA agent for MultiChannel PHYs
u Agent to WWDM, Parallel Optics
u Avoids excessive penalties for all other PHYs
Self-timed interface eliminates high-speed interface clocks
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS Highlights
Increased reach
u XGMII is ~3 (~7 cm)
u XAUI is ~20 (~50 cm)
n Equalization may further increase distance
Lower connection count
u XGMII is 74 wires (2 sets of 32 data, 4 control & 1 clock)
u XAUI is 16 wires (2 sets of 4 differential pairs)
Better jitter control
u XGMII does not attenuate jitter
u XAUI self-timed interface enables excellent jitter control at PCS
10 GbE Physi cal GEC 2000 Tutorial
10G Link Architecture/Jitter Budget
XGXS
EnDec
SerDes
PCS
PMA
PMD
.35 .65 Independent .35 .65 (UI)
Jitter Budget 1 Jitter Budget 2 Jitter Budget 3
Medium Jitter Budget is independent of XAUI
Requires XGXS functionality at both XAUI link ends
XAUI/XGXS simplifies 10 GbE link development
Medium XAUI XAUI
XGXS
EnDec
SerDes
Local
Device
Remote
Device
S
e
r
D
e
s
1
S
e
r
D
e
s
1
E
n
D
e
c
2
E
n
D
e
c
2
E
n
D
e
c
2
S
e
r
D
e
s
2
E
n
D
e
c
2
S
e
r
D
e
s
2
TP2 TP3 TP3
TP4 TP1 TP3 TP2 TP4 TP1
TP2 TP1
TP4
1
Optional XGXS retiming functionality
2
Optional PCS/PMA
PCS
PMA
PMD
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS Benefits
MAC
RS
XGXS
XAUI
0.25 micron
CMOS feasible
to 20
FR-4 PCB
Low power
SerDes
Low pin count
System Layout
Flexibility
Multi- Protocol
Commonal i ty
10 GbE
10 GFC
I nfi ni Band
OIF
Scalability
Self- Ti med
I ndependent
Jitter budget
PCS/ PMA
Integration
I nto MAC
PMD
I ndependence
Sali
Inside
X
G
X
S
MDI
P
C
S
P
M
A
P
M
D
10 GbE Physi cal GEC 2000 Tutorial
XGXS Functions
Use 8B/10B transmission code
Perform column striping across 4 independent serial lanes
u Identified as lane 0, lane 1, lane 2, lane 3
Perform XAUI lane and interface (link) synchronization
Idle pattern adequate for link initialization
Perform lane-to-lane deskew
Perform clock tolerance compensation
Provide robust packet delimiters
Perform error control to prevent error propagation
10 GbE Physi cal GEC 2000 Tutorial
Data Mapping Example
Lane 0 K R S d
p
d d --- d d d d
f
A K R K
Lane 1 K R d
p
d
p
d d --- d d d
f
T A K R K
Lane 2 K R d
p
d
p
d d --- d d d
f
K A K R K
Lane 3 K R d
p
d
s
d d --- d d d
f
K A K R K

XGXS Encoded Data
XGMII
D<7:0,K0> I I S d
p
d d --- d d d d
f
I I I I
D<15:8,K1> I I d
p
d
p
d d --- d d d
f
T I I I I
D<23:16,K2> I I d
p
d
p
d d --- d d d
f
I I I I I
D<31:24,K3> I I d
p
d
s
d d --- d d d
f
I I I I I


10 GbE Physi cal GEC 2000 Tutorial
Basic Code Groups
Similar to GbE
u No even/odd alignment, new Skip and Align
/A/ K28.3 (Align) - Lane deskew via code-group alignment
/K/ K28.5 (Sync) - Synchronization, EOP Padding
/R/ K28.0 (Skip) - Clock tolerance compensation
/S/ K27.7 (Start) - Start-of-Packet (SOP), Lane 0 ID
/T/ K29.7 (Terminate) - End-of-Packet (EOP)
/E/ K30.7 (Error) - Signaled upon detection of error
/d/ Dxx.y (data) - Packet data
10 GbE Physi cal GEC 2000 Tutorial
Extra Code Groups
The following are included in related proposals:
/Kb/ K28.1 (Busy Sync) - Synchronization/Rate control
/Rb/ K23.7 (Busy Skip) - Clock tolerance comp/Rate control
/O/ K28.2 (FCOS) - Fibre Channel Ordered Set
The following remaining 8B/10B special code-groups are
are not used:
K28.4, K28.6, K28.7*
* (Be careful not to follow /K28.7/ with /K28.x/, /D3.x/, /D11.x/, /D12.x/,
/D19.x/, /D20.x/, or /D28.x/, as a comma is generated across the boundaries of
the two adjacent code-groups and may result in false code-group alignment)
10 GbE Physi cal GEC 2000 Tutorial
XGXS Idle Encoding
Idle is conveyed by the repeating sequence:
AKRKRKRKRKRKRKRKAKRKR....
on each of 4 XAUI lanes
/A/ used to deskew and align XAUI lanes at receiver
/K/ contains a comma. The alternating sequence KRKR
contains both running disparity versions of comma
(comma+, comma-).
/R/ is disparity neutral enabling insertion/removal without
affecting lane running disparity.
/A/, /K/ and /R/ hamming distance is 3
Latest Idle proposal effectively scrambles /A/K/R/ stream
10 GbE Physi cal GEC 2000 Tutorial
Synchronization
XAUI 4-lane link synchronization is a 5 step process
1-4 acquire sync on all 4 lanes individually
5 align/deskew synchronized lanes
Loss of sync on any lane results in XAUI link loss-of-sync
Lane sync acquisition similar to 1000BASE-X PCS
u Employ hysteresis to preclude false sync and loss-of-sync due to bit
errors
u Hot-sync not an appropriate implementation technique
u Periodic Align (/A/-column) check a good link health check
XAUI Link Sync is fast, straightforward and reliable
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS Deskew
Skew is imparted by active and passive link elements
Deskew process accounts for all skew present at the receiver
Lane deskew performed by alignment to deskew pattern present in
Idle stream: Align code-groups in all lanes
/A/ columns are issued a minimum of 16 columns apart
40 UI deskew pattern needs to be 80 bits. Idle is 160 bits.




Skew Source # Skew Total Skew
SerDes Tx 1 1 UI 1 UI
PCB 2 1 UI 2 UI
Medium 1 <16 UI <16 UI
SerDes Rx 1 20 UI 20 UI
Total <39 UI


10 GbE Physi cal GEC 2000 Tutorial
XGXS Deskew
Lane 3 K R K A K R K R K R K R

Lane 0 K R K A K R K R K R K R

Lane 1 K R K A K R K R K R K R

Lane 2 K R K A K R K R K R K R

Skewed data at receiver input. Skew ~18 bits
Lane 1 K R K A K R K R K R K R


Lane 2 K R K A K R K R K R K R


Lane 3 K R K A K R K R K R K R


Lane 0 K R K A K R K R K R K R


Deskew lanes by lining up Align code-groups
10 GbE Physi cal GEC 2000 Tutorial
Clock Tolerance Compensation
The XGXS provides jitter and noise isolation by retiming or
attenuating jitter by the use of a high quality repeater
Retiming is optional, but may help control jitter
Idle pattern Skip (/R/) columns may be inserted/removed to
adjust for clock tolerance differences due to retiming
u Skip columns may be inserted anywhere in Idle stream
u Proper disparity Skip required in each Lane
u Any Skip column may be removed
Clock tolerance for 1518 byte packet @ 100 ppm is 0.76
UI/lane
u A few bytes of elasticity buffering is sufficient to wait for many
frames in case a Skip column is not available for removal
10 GbE Physi cal GEC 2000 Tutorial
Skip Column Insert Example
Lane 0 K R S d
p
d d --- d d d d
f
A K R K
Lane 1 K R d
p
d
p
d d --- d d d
f
T A K R K
Lane 2 K R d
p
d
p
d d --- d d d
f
K A K R K
Lane 3 K R d
p
d
s
d d --- d d d
f
K A K R K

Lane 0 K R S d
p
d d --- d d d d
f
A R K R
Lane 1 K R d
p
d
p
d d --- d d d
f
T A R K R
Lane 2 K R d
p
d
p
d d --- d d d
f
K A R K R
Lane 3 K R d
p
d
s
d d --- d d d
f
K A R K R

Skip column inserted here
10 GbE Physi cal GEC 2000 Tutorial
XAUI/ XGXS Error Control
Packets with detected errors must be aborted
u 8B/10B code violation detection may be propagated forward
u IPG special code-groups stop error propagation (e.g. /A/, /K/, /R/)
Rule: Signal Error code upon detected error or in column
containing EOP if the error is detected during the IPG.
Error signaling is a lane function since disparity is checked
per lane.
XGXS checks received packets for proper formation
u Rules TBD, should be PHY/Protocol independent
8B/10B code violation functionality may be used for link
integrity testing
u May be used in conjunction with loopback modes
10 GbE Physi cal GEC 2000 Tutorial
XAUI Electrical
Electrical interface is based on low swing AC
coupled differential interface
AC coupling is required at receiver inputs
Link compliance point is at the receiver
Transmitter may use equalization as long as
receiver specifications are not exceeded
10 GbE Physi cal GEC 2000 Tutorial
XAUI Rx/Tx & Interconnect




Transmitter Parameter Value
Vo Dif(max) 800 mv
Vo Dif(min) 500 mv
Voh AC
Vol AC
Input nominal 6.5 ma
Differential Skew(max) 15 ps


Receiver Parameter Value
Vin Dif(max) 1000 mv
Vin Dif(min) 175 mv
Loss 50

9.1 dB
Differential Skew(max) 75 ps


Interconnect Parameter Value
Tr/Tf Min, 20%-80% 60 ps
1

Tr/Tf Max, 20%-80% 131 ps
1

PCB Impedance 100 10


Connector Impedance 100 30


Source Impedance 100 20


Load Termination 100 20


Return Loss 10 dB
2



1. Optional if transmitter meets the receiver
jitter and eye mask with golden PCB
2. SerDes inputs must meet the return loss
from 100 MHz to 2.5 GHz (0.8 x 3.125
Gbaud)
10 GbE Physi cal GEC 2000 Tutorial
XAUI Loss Budget




Item Loss
Connector Loss 1 dB
Next + Fext Loss 0.75 dB
PCB Loss 7.35 dB
Loss Budget 9.1 dB


PCB Condition 1 Normal Worst
MSTL Loss Max (dB/in) 0.32 0.43
Max Distance (in) 23 17.1


PCB Condition 2 Normal Worst
STL Loss Max (dB/in) 0.41 0.55
Max Distance (in) 18 13.4


Normal PCB was assumed with loss tangent of 0.22,
worst case it was assumed high temperature and
humidity 85/ 85. Better grade of FR4 may reduce the
loss by as much as 50%.
HP test measurement for 20" line showed 5.2 dB loss or
0.26dB/ in based on the eye loss, the loss assumed here
is very conservative.
10 GbE Physi cal GEC 2000 Tutorial
XAUI Jitter




Jitter Compliance Point Tx
1
Rx
Deterministic Jitter 0.17 UI 0.41 UI
Total Jitter 0.35 UI
2
0.65 UI
1-sigma RJ @ max DJ for 10
-12
BER
3
4.11 ps 5.49 ps
1-sigma RJ @ max DJ for 10
-12
BER
3
3.92 ps 5.23 ps


1. Tx point is for reference. Rx point is for compliance.
2. The SerDes component should have better jitter performance than specified
here to allow for system noise.
3. 1-Sigma value listed here are at maximum DJ, if the DJ value is smaller then
the 1-Sigma RJ may increase to the total jitter value.
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS Summary
PHY and Protocol independent scalable architecture
XAUI/XGXS provide PHY, Protocol & Application independence
Common interface/rules for 10 GbE LAN PHY and UniPHY, 10
Gigabit Fibre Channel & InfiniBand
Based on generic 10 Gbps chip-to-chip interconnect architecture
Architecture resembles simple and familiar 1000BASE-X PHY
Low complexity, low latency, quick synchronizing reliable
interface
Enabler for early 10 GbE PHYs
May be integrated into MAC/RS ASIC, eliminating XGMII
10 GbE Physi cal GEC 2000 Tutorial
PCS, PMA & PMD Sublayers
PHYSICAL
DATA LINK
NETWORK
TRANSPORT
SESSION
PRESENTATION
APPLICATION
OSI
REFERENCE
MODEL
LAYERS
Reconciliation
MAC
MAC Control (Optional)
LLC
XAUI
LAN
LAYERS
HIGHER LAYERS
MDI = Medium Dependent Interface
XGMII = 10 Gigabit Media Independent Interface
XAUI = 10 Gigabit Attachment Unit Interface
PCS = Physical Coding Sublayer
XGXS = XGMII Extender Sublayer
PMA = Physical Medium Attachment
PHY = Physical Layer Device
PMD = Physical Medium Dependent
PMD
MEDIUM
MDI
XGXS
XGMII
PMA
PCS
XGXS
10 GbE Physi cal GEC 2000 Tutorial
PHY Guts
OK, weve got 10 Gbps of data lined up at the end
of these PCB traces. Now how do we get it into
that little piece of glass?
Enter the 3 Sublayers:
Physical Coding Sublayer (PCS)
Physical Medium Attachment (PMA)
Physical Medium Dependent (PMD)
10 GbE Physi cal GEC 2000 Tutorial
Proposed LAN PMDs
Serial @ 10.3125 Gbaud @ 1300/1550 & 850 nm
u 100 m using uncooled 1300 nm FP over standard MMF
u 300 m using 850 nm VCSELs with enhanced MMF
u 2 km using uncooled unisolated 1300 nm FP over SMF
u 10 km using uncooled 1300 nm DFB over SMF
u 40 km using cooled 1300/1550 nm DFB over SMF
Parallel proposals
u Parallel Optics (including fibers) @ 850nm
u 4 x 3.125 Gbps WDM @ 1300 nm (WWDM) over MMF or SMF
Multilevel Analog Signaling (MAS) using PAM5
Leading Proposals indicated in Red
10 GbE Physi cal GEC 2000 Tutorial
1300/1550 nm Serial PMD
Directly modulated uncooled DFB laser for typical
LAN distances
Single mode fiber, 1 m to 40 km
10.3125 Gbps line rate with 64B/66B PCS
Optical Transceiver components from current
production may be adapted to 10 GbE LAN
10 GbE Physi cal GEC 2000 Tutorial
Wide WDM (WWDM)
4 x 3.125 Gbaud eases transmission and jitter
specifications
1300 nm DFB single interface supports:
u 300 m of installed or new 62.5 MMF and 50 MMF
u 10 km of SMF
WWDM's large channel spacing enables low cost
optical demultiplexers
Larger number of lower speed devices than Serial
Requires lasers having separated wavelengths;
adding complexity to the specification
10 GbE Physi cal GEC 2000 Tutorial
Serial LAN PHY Proposal
The following slides describe one leading proposal
in front of the IEEE 802.3ae Task Force.
This proposal includes includes PCS, PMA and
PMD elements and supports all interfaces to the
MAC and is the basis of the UniPHY proposal.
Tutorial time does not permit full descriptions of
all PHY proposals in front of the Task Force.
u See http://grouper.ieee.org/groups/802/3/ae/index.html
for all proposals presented to date.
10 GbE Physi cal GEC 2000 Tutorial
Serial LAN PHY Block Diagram
8B/10B
CDR
(XGXS)
8B/10B
CDR
(XGXS)
O/E
(PMD)
O/E
(PMD)
SerDes
(PMA)
SerDes
(PMA)
XAUI
64B/66B
Coding
(PCS)
64B/66B
Coding
(PCS)
(PCB
Traces)
MDI
10 GbE Physi cal GEC 2000 Tutorial
Serial PCS
Physical Coding Sublayer (PCS)
Supports 10 Gbps data transport + high efficiency coding
Directly maps XAUI/XGXS data to/from PMA
Performs 64B/66B Encoding/Decoding
u DC-balanced, high transition-density, quick-sync code
u Frame and IPG control delineation preserved
u Supports clock tolerance compensation functionality
66-bit word PMA Service Interface defined (PCS n n PMA)
10 GbE Physi cal GEC 2000 Tutorial
XAUI/XGXS-to-PCS Mapping
Lane 0 K R S d
p
d d --- d d d d
f
A K R K R
Lane 1 K R d
p
d
p
d d --- d d d
f
T A K R K R
Lane 2 K R d
p
d
p
d d --- d d d
f
K A K R K R
Lane 3 K R d
p
d
s
d d --- d d d
f
K A K R K R


XAUI/XGXS columns partitioned into 64B/66B sub-frames
d d d d d d d d

d d d d d d d d


1 0 1 --- 0
78 d
p
d
p
d
p
d
p
d
p
d
p
d
s


1E K K K K R R R R


0 1 0 1
64B/66B sub-frames in serial transmission order
1E A A A A K K K K


D2 d d
f
d
f
d
f
d
f
K K


0 1 0 1
10 GbE Physi cal GEC 2000 Tutorial
Why 64B/66B?
Provide full 10.000 Gb/s bandwidth for LAN applications
u No flow-control necessary for LAN applications
u Extends LAN to 40 km+ applications
Interface directly to XAUI with control code transparency
u Allows interoperability with other common backplane coding schemes
(Fibre Channel, InfiniBand as well as XAUI)
Ensure robust DC-balance, transition density, and frame
synchronization properties suitable for optical transmission
u Two-bit preamble allows frame synchronization AND sets maximum
degenerate run length at 66 bits (<<SONET)
u May be implemented in <5k gates.
u 4-bit Hamming protection over packet, data, and control
Low overhead allows compatibility with existing SONET
optical transceivers
10 GbE Physi cal GEC 2000 Tutorial
Building 64B/66B Frames
10 GbE Physi cal GEC 2000 Tutorial
64B/66B Code Overview
Data Codewords have 01 sync preamble
Mixed Data/Control frames are identified with a "10" sync
preamble. Both the coded 56-bit payload and TYPE field
are scrambled
00,11 preambles are considered code errors and cause the
packet to be invalidated by forcing error (E) symbols on
the output
10 GbE Physi cal GEC 2000 Tutorial
64B/66B Code Summary
10 GbE Physi cal GEC 2000 Tutorial
Serial PMA
Physical Medium Attachment (PMA)
Directly maps PCS data to/from PMD
Translates PCS 66B sub-frames to/from a PMD serial bit
stream
1-bit PMD Service Interface defined (PMA n n PMD)
Intra-PMA physical interfaces not specified (i.e. may be 16b,
4b, etc.)
Serializer, Deserializer and Clock/Data Recovery unit
specified
PCS clocks Tx data to PMA, PMA clocks Rx data to PCS
u PMA based reference clock provides PCS/PMA master clock
10 GbE Physi cal GEC 2000 Tutorial
Implementation Example
XGXS Rx
CDR
DESERIALIZE
ALIGN
SYNC
DESKEW
8B/10B DECODE
PCS
64B/66B
FRAME
ENCODE
ELASTIC
BUFFER
Hari Rx
RefCLK
Hari Rx
CLKout
Hari Rx
CLKin
66B Tx
CLKin
66B Tx
CLKin
PMA
66B:16B
GEARBOX
16B Tx
CLKin
XGXS Tx
SERIALIZE
8B/10B ENCODE
PCS
SYNC
DECODE
ELASTIC
BUFFER
Hari Tx
CLKin
Hari Tx
CLKin
66B Rx
CLKin
66B Rx
CLKin
PMA
66B:16B
GEARBOX
16B Rx
CLKin
16
Tx Data
TCLK
Tx CMU
66B Tx CLK
16B Tx CLK
Hari Rx
CLKin
Tx Path
Rx Path
Hari Rx RefCLK
Rx CMU
16B Rx CLK
Hari Tx CLK
66B Rx CLK
OIF
XAUI
MDIO
MDC
Hari
SysCLK
OIF
SysCLK
(Reqd)
Hari
CLKout
Signal
Detect
Tx
Disable
Loop
Back
Data
In
16
Rx Data
RCLK
MADR
5
GPIO 4
Data
Out
PMA
MUX
VCO
PLL
PMA
DEMUX
CDR
PMD
DRIVER
LASER
PMD
PIN
PREAMP
AGC
OIF
SysCLK
MDI
10 GbE Physi cal GEC 2000 Tutorial
Another Implementation Example
LAN PHY
Optics
Ser Des
64/66
Encode/ Decode
Seri al i zer/
Deseri al i zer
Opti cal
Transmi tter/Recei ver
XGMI I / XAUI
(Sal i / Hari )
10 GbE Physi cal GEC 2000 Tutorial
Serial PMD - Five Candidates
1. 300 m., 850 nm, VCSEL, new multimode
2. 2 km, 1310 nm, FP laser, singlemode
3. 10 km, 1310 nm, DFB or VCSEL, singlemode
4. 40 km, 1310 nm, DFB, cooled, singlemode
5. 40 km, 1550 nm, DFB, singlemode*
Leading Proposals indicated in Red
* A sui tabl e method of speci fyi ng the requi red cabl e pl ant qual i ty i s under
consi derati on.
10 GbE Physi cal GEC 2000 Tutorial
Link Power Budget & Penalties
- SMF SMF SMF SMF New
MMF
Fiber type
nm 1530 to
1560
1300 to
1315
1290 to
1325
1290 to
1330
840 to 860 Wavelength (range)
dB 2.76 1.84 1.50 1.68 1.80 Unallocated margin in
link power budget
dB 4.27 3.02 2.30 6.15 3.61 Link power penalties
dB 13.82 21.98 7.04 3.01 2.59 Channel insertion loss
m 40000 40000 10000 2000 300 Operating distance
dB 20.84 26.84 10.84 10.84 8.00 Link power budget
Unit Type 5 Type 4 Type 3 Type 2 Type 1 Description
Note: Baseline wander is measured in terms of the standard deviation of the distribution, then
normalized to of the vertical eye opening at TP4. It is assumed to be 2.5%.
10 GbE Physi cal GEC 2000 Tutorial
Transmit Characteristics
dB 30 30 30 - - SMSR
dBm +2 +7 +2 +2 -1.3 Avg. launch power
(max)
nm 0.05 0.20 0.40 2.75* 0.20*** RMS Spectral Width
(max)
ps 20 40 40 40 30 Trise/Tfall (20%-
80%)
nm 1530 to
1560
1300 to
1315
1290 to
1325
1290 to
1330
840 to 860 Wavelength (range)
GBd 10.3125
+/- 100
ppm
10.3125
+/- 100
ppm
10.3125
+/- 100
ppm
10.3125
+/- 100
ppm
10.3125
+/- 100
ppm
Signaling Speed
(range)
LW laser LW laser LW laser LW laser SW laser Tx type
Unit Type 5 Type 4 Type 3 Type 2 Type 1 Description
10 GbE Physi cal GEC 2000 Tutorial
Tx Characteristics (contd)
Unit Type 5 Type 4 Type 3 Type 2 Type 1 Description
dBm -2 +4 -4 -4 -5.5 Avg. launch power
(min)
dB 6 6 6 6 7 Extinction Ratio**
(min)
dB/Hz -140 -130 -130 -130 -125 RIN (max)
dBm -30 -30 -30 -30 -30 Avg. launch power of
OFF transmitter (max)
*Requires k factor 0.5 max.
** Alternate, OMA-like representation is under review
***Under review. Some experimental evidence suggests that a much larger linewidth may
be specified.
10 GbE Physi cal GEC 2000 Tutorial
Receive Characteristics
dB TBD TBD TBD TBD TBD Vertical eye closure
penalty
dBm -16.25 -18.41 -11.47 -7.44 -8.52 Stressed receive
sensitivity
GHz 12.36 12.36 12.36 12.36 12.36 Receive electrical 3
dB upper cutoff
frequency (max)
dB 12 12 12 12 12 Return loss (min)
dBm -22.84 -22.84 -14.84 -14.84 -13.5 Receive sensitivity
dBm +2 TBD +2 +2 -1.3 Avg. receive power
(max)
nm 1530 to
1560
1295 to
1315
1290 to
1325
1290 to
1330
840 to 860 Wavelength (range)
GBd 10.3125
+/- 100
ppm
10.3125
+/- 100
ppm
10.3125
+/- 100
ppm
10.3125+
/- 100
ppm
10.3125
+/- 100
ppm
Signaling speed
(range)
Unit Type 5 Type 4 Type 3 Type 2 Type 1 Description
10 GbE Physi cal GEC 2000 Tutorial
Further Serial PMD Work
Define Jitter specifications
Improve MPN model
Consolidate some link types
Validate link model with experiments
Study dynamic range vs. sensitivity tradeoffs
Research better ways of specifying cable plant
quality
10 GbE Physi cal GEC 2000 Tutorial
UniPHY Overview
A Proposal for a PHY architecture suitable for
serial transmission on both LAN and WAN
u Operating in a LAN or WAN at a data rate of 10 Gbps
u Upgrade to existing enterprise networks with:
n Minimal cost
n Minimal complexity
n Maximum compatibility with 10/100/1000 Mbps
u Operating in a WAN at a data rate which is compatible
with the payload rate of OC-192c/SDH VC-4-64c
n Carry native Ethernet packets over the SONET WAN
infrastructure, which has an installed base with a specific
architecture and specific signaling requirements
10 GbE Physi cal GEC 2000 Tutorial
MEDIUM
Physical Medium Dependent (PMD)
Physical Coding Sublayer (PCS)
Physical Medium Attachment (PMA)
Reconciliation
Media Access Control (MAC)
MAC Control (Optional)
Upper Layers
10 Gigabit Ethernet
Reference Model
SerDes
XGMII/XAUI
UniPHY Proposal
64/ 66 CODEC
SONET Framing
& scrambler
WI S
}
8B/10B CODEC
10 GbE Physi cal GEC 2000 Tutorial
WAN Interface Sublayer (WIS)
Enabled when attached to a WAN
Disabled (bypassed) when attached to a LAN
Performs:
u SONET Framing
u SONET Overhead processing
u x
7
+ x
6
+1 scrambler
In short, everything you need to adapt the 64/66
Serial LAN PHY to a WAN interface
10 GbE Physi cal GEC 2000 Tutorial
UniPHY Benefits
Robust frame delimiters
Robust scrambler
Excess code space for special codes
Low complexity encode/decode
Commonality between LAN & WAN PHY silicon
PHY doesnt need to know the length of the frame
PHY doesnt need to overwrite Preamble
10 GbE Physi cal GEC 2000 Tutorial
UniPHY Block Diagram
8B/10B
CDR
(XGXS)
8B/10B
CDR
(XGXS)
64B/66B
Coding
(PCS)
64B/66B
Coding
(PCS)
XAUI
WIS
WIS
MDI
O/E
(PMD)
O/E
(PMD)
SerDes
(PMA)
SerDes
(PMA)
10 GbE Physi cal GEC 2000 Tutorial
UniPHY = LAN PHY + WIS
LAN PHY
Optics
Ser Des WI S
64/66
Encode/ Decode
Seri al i zer/
Deseri al i zer
Opti cal
Transmi tter/Recei ver
WAN
Interface
Subl ayer
XGMI I / XAUI
(Sal i / Hari )
10 GbE Physi cal GEC 2000 Tutorial
Integrated UniPHY
LAN PHY
Optics
+WI S
Ser Des
64/66
Encode/ Decode
Seri al i zer/
Deseri al i zer
Opti cal
Transmi tter/Recei ver
WAN
Interface
Subl ayer
XGMI I / XAUI
(Sal i / Hari )
10 GbE Physi cal GEC 2000 Tutorial
Really Integrated UniPHY
LAN PHY
Optics
+WI S
+Ser Des
64/66
Encode/ Decode
Seri al i zer/
Deseri al i zer
Opti cal
Transmi tter/Recei ver
WAN
Interface
Subl ayer
XGMI I / XAUI
(Sal i / Hari )
10 GbE Physi cal GEC 2000 Tutorial
UniPHY Nirvana
Optics
LAN PHY
+WI S
+SerDes
64/66
Encode/ Decode
Seri al i zer/
Deseri al i zer
Opti cal
Transmi tter/Recei ver
WAN
Interface
Subl ayer
XGMI I / XAUI
(Sal i / Hari )
10 GbE Physi cal GEC 2000 Tutorial
DWDM Transponder
M
D
I TU DWDM
Opt i cs
LAN PHY
+WI S
+SerDes
XAUI
(Hari )
Cheap LAN
Opt i cs
To
Rout er
or Swi t ch
To Phot oni c
Net work
10 GbE Physi cal GEC 2000 Tutorial
Switch or Router Using UniPHY
SFF
XCVR
SFF
XCVR
SFF
XCVR
SFF
XCVR
Quad
SerDes
4 x 1 G
XGXS
UniPHY
Nirvana
SFF
XCVR
SFF
XCVR
SFF
XCVR
SFF
XCVR
Quad
SerDes
4 x 1 G
XGXS
UniPHY
Nirvana
Switch Fabric
XAUI
XGMII
10 GbE Physi cal GEC 2000 Tutorial
Data and Signal Rate Comparison
LAN PHY 64B/66B UniPHY 64B/66B
MAC Data Rate 10 Gbps 9.29419 Gbps
XGMII Signal Rate 156.25 MHz DDR 156.25 MHz DDR
XGMII Data Rate 10 Gbps 9.29419 Gbps
XAUI Signal Rate 4 x 3.125 GBaud 4 x 3.125 GBaud
XAUI Data Rate 10 Gbps 9.29419 Gbps
Encoded Data Rate 10.3125 GBaud 9.58464 GBaud
Serial Line Rate 10.3125 GBaud 9.95328 GBaud


UniPHY works with all rate adaptation proposals:
u Open loop
u Word Hold
u Busy Idle
10 GbE Physi cal GEC 2000 Tutorial
UniPHY Benefits
Common interface can be used for both LAN/WAN PHY
Common functions can shared between LAN/WAN PHY
Common optics can be shared between LAN/WAN PHY
LAN PHY advocates get what they want:
u Minimal cost
u Minimal complexity
u Maximum compatibility
WAN PHY advocates get what they want:
u Compatibility with photonic infrastructure
u Compatibility with OAM&P
10 GbE Physi cal GEC 2000 Tutorial
Alternative Ethernet WAN Support
Proposal for optional Layer 1 signaling capability
by using InterPacket Gap (IPG)
XGENIE: 10 GbE Network Interface Extension
http://grouper.ieee.org/groups/802/3/ae/public/mar00/ishida_1_0300.pdf
Provides Ethernet Native WAN capability
Provides SONET OAM&P-like capability
Uses standard Ethernet Management Interface
u MDIO/MDC
10 GbE Physi cal GEC 2000 Tutorial
Ethernet Native WAN capability
remote monitor
To provide reliable & maintainable PHY connections over
multiple spans of fibers and media converters in WAN.
802. 1D Rel ay
MAC
PHY
customer site
provider sites
LAN WAN LAN
customer site
fault localization
AU AU AU AU AU AU AU AU AU AU
802.1D Relay
MAC
PHY AU AU
AU: Attachment Unit
MMF SMF 1.3 WDM SMF 1.5 SMF 1.5 SMF 1.3 MMF
Physical
Media:
10 GbE Physi cal GEC 2000 Tutorial
Optical Cross-Connect Application
Router
SW
Media
converter
Array
Inter-office fibers
Optical
matrix
switch
MAC
Reconciliation
XGXS
XGMII
XAUI
XGXS
PCS
PMA
PMD
MDI
400 x 400
switch
slot-
in
unit
slot-
in
unit
slot-
in
unit
backboard
Media
converters LAN
Port
MMF, SMF, or WDM
MMF
Intra-Office
100 - 300 m
Inter-Office
- 10 km (Local Access)
- 120 km (without Amp.)
- 500 km (with Optical Amp.)
Inter-office Attachment Unit
Intra-office Attachment Unit
Attachment
Unit
Layer Model
Providers Router
Customers SW
Provider
Site
10 GbE Physi cal GEC 2000 Tutorial
XGENIE Functionality
802. 1D Rel ay
MAC
PHY AU AU AU AU AU AU AU AU AU AU
802.1D Relay
MAC
PHY AU AU
End-End global
Identifier
Provider A
Provider B Provider C
Check
Provider-local
Identifier Insert Check &
removal
Insert
Insert Check &
removal
Insert Check &
removal
Crossconnect-
local Identifier
Insert Check &
removal
Insert
Check &
removal
SONET
analogy
Path
Line
Section
XC XC
10 GbE Physi cal GEC 2000 Tutorial
Why Layer1 Signaling?
MAC
Reconciliation
XGXS
XGMII
XAUI
XGXS
PCS
PMA
PMD
Layer Model
MDI
400 x 400
switch
slot-
in
unit
slot-
in
unit
slot-
in
unit
backboard
Media
converters
LAN Port
MMF, SMF, or WDM
MMF
Not desirable to
u Customize devices other than AU, nor touch Layer 2 and higher.
u Implement buffers in AU beyond the need for clock tolerance.
u Hack client packets, nor overwrite preamble and length field.
Customize
MAC
Touch Layer-2
at Attachment Unit
Insert/Hack
packets
10 GbE Physi cal GEC 2000 Tutorial
XGENIE Protocol 1/2
Optional Layer 1 signaling by using IPG
packet I PG
No influence on Layer-2 and higher.
u XGXS/PCS to RS translates XGENIE data into Idle
Et her packet Et her packet I PG
Replace IDLE with signaling data
Check the signaling data
IPG:
InterPacket Gap
packet Et her packet Et her packet
packet Et her packet Et her packet
another signaling data
10 GbE Physi cal GEC 2000 Tutorial
XGENIE Protocol 2/2
On XAUI, Idles may be replaced with Ordered-Sets at most
every other column.
K
K
K
K
R
R
R
R
S
d
p
d
p
d
p
d
p
d
p
d
p
d
p
d
d
d
d
...
...
...
... d
d
d
d
d
d
d
d
d
d
f
d
f
d
f
d
f
T
K
K
A
A
A
A
K
K
K
K
R
R
R
R
K
K
K
K
...
...
...
... R
R
R
R
R
R
R
R
K
K
K
K
S
d
p
d
p
d
p
d
p
d
p
d
p
d
p
d
d
d
d
...
...
...
... d
d
d
d
d
d
d
d
d
d
f
d
f
d
f
d
f
T
K
K
A
A
A
A
K
K
K
K
R
R
R
R
K
K
K
K
...
...
...
... O
d
1
d
2
d
3
XGENIE data inserted into IPG
d1, d2, d3: valid data bytes for signaling
Lane 1
Lane 2
Lane 3
Lane 0
Lane 1
Lane 2
Lane 3
Lane 0
XAUI
XAUI +
XGENIE
Signaling bandwidth Bs > 9.8 Mbps can be expected
Influence on buffer size for clock tolerance is negligible
10 GbE Physi cal GEC 2000 Tutorial
Conclusion
10 Gigabit Ethernet is Real
10 Gigabit Ethernet Physical Layer proposals for the LAN
and WAN are complete and well defined
The schedule is looking more realistic every day
Leveraging of as much technology as possible
u 8B/10B coding, Scrambling, OC-192 optics, Ethernet Management
Interface, InfiniBand, DDR clocking, SSTL-2, etc.
10 GbE will be 100% Ethernet LAN compatible
10 GbE will support SONET directly as well as function as
a native MAN/WAN
10 GbE Physi cal GEC 2000 Tutorial
Acknowledgements
IEEE 802.3 members who have directly/indirectly
contributed to key 10 GbE PHY proposals
Jonathan Thatcher, World Wide Packets; Brad Booth, Intel; John Ewen, IBM;
Ben Brown, Nortel; Howard Frazier, Cisco; Rick Walker, Agilent;
Don Alderrou, nSerial; Vipul Bhatt, Finisar; Osamu Ishida, NTT;
Richard Dugan, Agilent; Walt Thirion, JatoTech Ventures; Bob Grow, Intel;
Henning Lysdal, Giga; Bill Woodruff, Giga; Schelto van Doorn, Infineon;
Mark Ritter, IBM; Joel Goergen, Lucent; David Cunningham, Agilent;
Paul Kolesar, Lucent; Del Hanson, Agilent; Piers Dawe, Agilent;
Dave Dolfi, Agilent; Brian Lemoff, Agilent; Fred Weniger, Vitesse;
Mike Dudek, Cielo; Jack Jewel, Picolight; Russ Patterson, Picolight;
Shawn Rogers, TI; Shimon Mueller, Sun; Nariman Yousefi, Broadcom;
Steve Haddock;
and the hundreds of others who are playing critical roles in developing the
10 GbE Standard