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AMBA
Overview
AMBA AHB
AMBA APB
AMBA AXI
PCIe
Advanced Microcontroller Bus
Architecture (AMBA)
The Advanced Microcontroller Bus Architecture (AMBA) specification
defines an onchip communications standard in terms of bus protocols
for communication between various system devices and peripherals.
AMBA is a registered trademark of ARM Limited and is an open
standard, on-chip interconnect specification for the connection and
management of functional blocks in a System-on-Chip (SoC). There
are different bus protocols to satisfy different requirements such as
speed, power, complexity depending on the type of devices or
peripherals that need to be connected. AMBA was introduced by ARM
Ltd in 1996. The first AMBA buses were Advanced System Bus (ASB)
and Advanced Peripheral Bus (APB). In its 2nd version, AMBA 2, ARM
added AMBA High-performance Bus (AHB) that is a single clock-edge
protocol. In 2003, ARM introduced the 3rd generation, AMBA 3,
including AXI to reach even higher performance interconnect and the
Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug

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Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug
and trace solution. In 2010 the AMBA 4 specifications were introduced
starting with AMBA 4 AXI4, then in 2011[2] extending system wide
coherency with AMBA 4 ACE. In 2013[3] the AMBA 5 CHI (Coherent
Hub Interface) specification was introduced, with a re-designed high-
speed transport layer and features designed to reduce congestion.
The AMBA 4 specification defines following buses/interfaces:
AXI Coherency Extensions (ACE) - widely used on the latest
ARM Cortex-A processors including Cortex-A7 and Cortex-A15
AXI Coherency Extensions Lite (ACE-Lite)
Advanced eXtensible Interface 4 (AXI4)
Advanced eXtensible Interface 4 Lite (AXI4-Lite)
Advanced eXtensible Interface 4 Stream (AXI4-Stream v1.0)
Advanced Trace Bus (ATB v1.1)
Advanced Peripheral Bus (APB4 v2.0)
AMBA 3 specification defines four buses/interfaces:
Advanced eXtensible Interface (AXI3 or AXI v1.0) - widely used
on ARM Cortex-A processors including Cortex-A9
Advanced High-performance Bus Lite (AHB-Lite v1.0)
Advanced Peripheral Bus (APB3 v1.0)
Advanced Trace Bus (ATB v1.0)
AMBA 2 specification defines three buses/interfaces:
Advanced High-performance Bus (AHB) - widely used on ARM7,
ARM9 and ARM Cortex-M based designs
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB2 or APB)
AMBA specification (First version) defines two buses/interfaces:
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB)
Advanced High-performance Bus (AHB)
The AMBA AHB is for high-performance, high clock frequency system
modules. The AHB acts as the high-performance system backbone
bus. AHB supports the efficient connection of processors, on-chip
memories and off-chip external memory interfaces with low-power
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memories and off-chip external memory interfaces with low-power
peripheral macrocell functions. AHB is also specified to ensure ease of
use in an efficient design flow using synthesis and automated test
techniques.
Advanced System Bus (ASB)
The AMBA ASB is for high-performance system modules. AMBA ASB
is an alternative system bus suitable for use where the high-
performance features of AHB are not required. ASB also supports the
efficient connection of processors, on-chip memories and off-chip
external memory interfaces with low-power peripheral macrocell
functions.
Advanced Peripheral Bus (APB)
The AMBA APB is for low-power peripherals. AMBA APB is optimized
for minimal power consumption and reduced interface complexity to
support peripheral functions. APB can be used in conjunction with
either version of the system bus.
Advanced eXtensible Interface (AXI)
AXI, the third generation of AMBA interface defined in the AMBA 3
specification, is targeted at high performance, high clock frequency
system designs and includes features that make it suitable for high
speed sub-micrometer interconnect. AXI is faster and better
performance than AHB. AMBA 4 completely gets rid of AHB and only
defines AXI for high performance requirements.
AXI Coherency Extensions (ACE)
ACE, defined as part of the AMBA 4 specification, extends AXI with
additional signalling introducing system wide coherency. This system
coherency allows different processor clusters to share memory and
enables technology like ARM's big.LITTLE processing.
A typical AMBA-based microcontroller
An AMBA-based microcontroller typically consists of a high-
performance system backbone bus (AMBA AHB or AMBA ASB), able
to sustain the external memory bandwidth, on which the CPU, on-chip
memory and other Direct Memory Access (DMA) devices reside. This
bus provides a high-bandwidth interface between the elements that are
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bus provides a high-bandwidth interface between the elements that are
involved in the majority of transfers. Also located on the
highperformance bus is a bridge to the lower bandwidth APB, where
most of the peripheral devices in the system are located (see Figure).
AMBA APB provides the basic peripheral macrocell communications
infrastructure as a secondary bus from the higher bandwidth pipelined
main system bus. Such peripherals typically:
have interfaces which are memory-mapped registers
have no high-bandwidth interfaces
are accessed under programmed control.
The following terms are used throughout this specification:
Bus cycle: A bus cycle is a basic unit of one bus clock period and for
the purpose of AMBA AHB or APB protocol descriptions is defined from
rising-edge to rising-edge transitions. An ASB bus cycle is defined from
falling-edge to falling-edge transitions. Bus signal timing is referenced
to the bus cycle clock.
Bus transfer: An AMBA ASB or AHB bus transfer is a read or write
operation of a data object, which may take one or more bus cycles.
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operation of a data object, which may take one or more bus cycles.
The bus transfer is terminated by a completion response from the
addressed slave. The transfer sizes supported by AMBA ASB include
byte (8-bit), halfword (16-bit) and word (32-bit). AMBA AHB additionally
supports wider data transfers, including 64-bit and 128-bit transfers. An
AMBA APB bus transfer is a read or write operation of a data object,
which always requires two bus cycles.
Burst operation: A burst operation is defined as one or more data
transactions, initiated by a bus master, which have a consistent width
of transaction to an incremental region of address space. The
increment step per transaction is determined by the width of transfer
(byte, halfword, word). No burst operation is supported on the APB.
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