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VHDL
VHDL stands of VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.
It was designed with the principles of structured programming. It allows you to dene the
interface of a hardware module and hide its internal details. VHDL Entity is the declaration
of modules inputs and outputs. VHDL Architecture is a detailed description of the modules
internal structure of behavior.
Program Structure
The structure of a typical VHDL program is listed below. It begins with a library declara-
tion followed by ENTITY and ARCHITECTURE sections. Entity denes the interface while
Architecture denes the real hardware.
LIBRARY ;
Package ;
ENTITY Entity_name IS I nt e r f a c e of Module
PORT ( i nput1 , i nput2 : IN type ; Read onl y
i o1 , i o2 : INOUT type ; Both i nput and ouput . Read and Write
buf1 , buf 2 : BUFFER type ; Output , al s o can be read i ns i de a r c hi t e c t ur e
ouput1 , output2 : OUT type ) ; Write onl y
END Entity_name ;
ARCHITECTURE Arch_name OF Entity_name IS Module s I nt e r anl St r uct ur e
TYPE de c l a r a t i o ns ; You can de f i ne your own data types
SIGNAL de c l a r a t i o ns ; Used to i nt e r c onne c t b/w components
CONSTANT de c l a r a t i o ns ; Constant . Can t be changed
FUNCTION d e f i n i t i o n s ; Takes many i nput s and r e t ur ns a s i ng l e val ue
PROCEDURE d e f i n i t i o n s ; Takes many i nput s and r e t ur e s many val ues
COMPONENT de c l a r a t i o ns ; Sub Module whom you gonna c a l l from t hi s module
BEGIN
assi gnment of Bool ean eqns or c ondi t i onal statements ; Data Flow Desi gn
i ns t a nt i a t i o n of components ; St r uc t ur al Desi gn
pr oc e s s d e f i n i t i o n Behavi or al De s cr i pt i on
END Arch_name ;
TYPES
All signals, variables, and constants in a VHDL program must have an associated type. The
type species the set or range of values that the object can take on, and there is also typically a
set of operators associated with a given type. The predened types are listed below.
BIT : single binary data, can take value 0 or 1
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BIT_VECTOR: multiple bit binary data. BIT_VECTOR(N-1 downto 0) / BIT_VECTOR(1
to N) species an N-bit binary data.
BOOLEAN: single bit, can take value TRUE or FALSE
INTEGER: can specify integer data types. Its value-range depends upon the compiler ie.
2
N1
+ 1 to 2
N1
1
CHARACTER: 8-bit character set
The most commonly used types in typical VHDL programs are user-dened types, and the most
common of these are enumerated types, which are dened by listing their values. Among the
above specied predened types, BOOLEAN and CHARACTER are enumerated types. For
an enumerated type, the value-list may be user identiers or 8-bit characters. The format for
enumerated type declaration is below.
TYPE my_enum_type is (value-list);
Value-list is a comma-separated list of all possible values of the type. The values may be
user-dened identiers or characters.
In standard library, BOOLEAN and STD_ULOGIC are dened as
BOOLEAN STD_ULOGIC
TYPE BOOLEAN IS (TRUE, FALSE); TYPE STD_ULOGIC IS (U, X,0,1,Z,W,L,H,-);
example for enumerated type: type trac_light_state is (reset, stop, wait, go);
Subtypes
VHDL allows users to create subtypes of a type. The values in the subtype must be a contiguous
range of values of the base type. Natural and positive are predened integer subtypes.
subtype subtype_name is type_name start to end; subtype subtype_name is type_name start downto end;
subtype twoval_logic is std_logic range 0 to 1; subtype fourval_logic is std_logic range X to Z;
subtype negint is integer range -2147483647 to -1; subtype bitnum is integer range 31 downto 0;
subtype natural is integer range 0 to highest-integer; subtype positive is integer range 1 to highest-integer;
Arrays
Array is an ordered set of elements of the same type, where each element is selected by an array
index.
Syntax Example
type type_name is array (start to end)
of element-type;
type monthy_count is array (1 to 12) of integer;
type type_name is array (start downto
end) of element-type;
type byte is array (7 downto 0) of integer;
type type_name is array (range_type)
of element-type;
constant WORD_LEN: integer:=32; type bus is
array (WORD_LEN-1 downto 0) of integer;
type type_name is array (range_type
range start to end) of element-type;
type myarr is array (integer range 0 to 15) of
integer;
type type_name is array (rang_type
range start downto end) of
element-type;
type myarr is arry (integer 31 downto 0) of integer;
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Programming Styles
VHDL is having three dierent styles of coding.
Dataow Model
In this style, concurrent signal assignment statement or conditional statement are used to realize
a logic function. All assignments are executed in parallel.
Syntax Example: Full Adder
Ar chi t ect ur e My_Arch of My_Ent i s
s i g na l de c l a r a t i o ns ;
begi n
concur r ent statements ;
x<= l o g i c f unt i on ( i nputs , s i g na l s ) ;
end My_Arch;
Enti ty FA i s port (
A, B, Cin : i n STD_LOGIC;
S , Cout : out STD_LOGIC) ;
end FA;
Ar chi t ect ur e Arch_FA of FA i s
begi n
S<= A xor B xor Cin ;
Cout<= (A and B) or
(B and Cin ) or (A and Cin ) ;
end Arch_FA;
Syntax Examples
Ar chi t ect ur e Arch_name of Ent_name i s
begi n
signal_name<= expr when bool ean expr e l s e
expr when bool ean expr e l s e
. . . . . . . . . . .
. . . . . . . e l s e
expr ;
End Arch_anme ;
Enti ty MUX4to1 i s port
(A, B, C,D : i n s t d_l ogi c ;
S : i n st d_l ogi c_vect or (1 downto 0 ) ;
Y: out s t d_l ogi c ) ;
End MUX4to1;
Ar chi t ect ur e Arch_MUX of MUX4to1 i s
begi n
y<= A when S="00" e l s e
B when S="01" e l s e
C when S="10" e l s e
D;
end Arch_MUX;
Ar chi t ect ur e Arch_name of Ent_name i s
begi n
wi th e xpr e s s i on s e l e c t
signal_name<= s i gnal _val ue when choi ce1 ,
s i gnal _val ue when choi ce2 ,
. . . . . . . . . .
s i ngal _val ue when ot her s ;
End Arch_anme ;
Enti ty MUX4to1 i s port
(A, B, C,D : i n s t d_l ogi c ;
S : i n st d_l ogi c_vect or (1 downto 0 ) ;
Y: out s t d_l ogi c ) ;
End MUX4to1;
Ar chi t ect ur e Arch_MUX of MUX4to1 i s
begi n
wi th S s e l e c t
Y<= A when "00" ,
B when "01" ,
C when "10" ,
D when ot her s ;
end Arch_MUX;
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Structural Model
In this model, the sub-modules are instantiated from the architecture body of the main module.
Port map, Generate and Generic are the important design elements in this style.
Port map is used to instantiate a sub-module. You can use either implicit (positional) or
explicit (using =>) port mapping. For positional port mapping the order of signals in the
component denition should be followed. For explicit mapping you can take any order.
Generate is used to instantiate multiple copies of same structure.
Generic : using Generic you can compile an entity and its architecture while leaving some
parameters like bus width, array size etc.
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syntax example: Three Bit Adder
Ar chi t ect ur e Arch_name of
Ent_name i s
component de c l a r a t i o ns ;
s i g na l de c l a r a t i o ns ;
begi n
di r e c t maping
l abe l 1 : component_name
port map( a , b , c ) ;
p o s i t i n a l maping
l abe l 2 : component_name port
map( a=>a , b=>b , c=>c ) ;
End Arch_name ;
Enti ty TB_adder i s port (
A, B : i n s t d_l ogi c_vect or (2 downto 0 ) ;
Y: out st d_l ogi c_vect or (3 downto 0 ) ) ;
End TB_adder ;
Ar chi t ect ur e Arch_TB of TB adder i s
component FA i s port (A, B, Cin : i n s t d_l ogi c ;
S , Cout : out s t d_l ogi c ) ; end component ;
s i g na l C : st d_l ogi c_vect or (2 downto 1 ) ;
begi n
IN1 : FA port map(A=>A( 0) , B=>B( 0) ,
Cin=>0 , S=>Y( 0) , Cout=>C( 1 ) ) ;
IN2 : FA port map(A=>A( 1) , B=>B( 1) ,
Cin=>C( 1) , S=>Y( 1) , Cout=>C( 2 ) ) ;
IN3 : FA port map(A=>A( 2) , B=>B( 2) ,
Cin=>C( 2) , S=>Y( 2) , Cout=>S ( 3 ) ) ;
end Arch_TB;
or you can do l i k e t hi s al s o .
Both gi ve same c i r c u i t
INST1 : FA port map(A( 0) , B( 0) , 0 ,Y( 0) ,C( 1 ) ) ;
INST2 : FA port map(A( 1) , B( 1) ,C( 1) ,Y( 1) ,C( 2 ) ) ;
INST3 : FA port map(A( 2) , B( 2) ,C( 2) ,Y( 2) , S ( 3 ) ) ;
Syntax f o r Generate
Ar chi t ect ur e Arch_name of
Ent_name i s
component de c l a r a t i o ns ;
s i g na l de c l a r a t i o ns ;
begi n
Label : f o r i d e n t i f i e r i n range
gener at e
concurrent statement ;
end gener at e ;
End Arch_name ;
Enti ty TB_adder i s port (
A, B : i n s t d_l ogi c_vect or (2 downto 0 ) ;
Y: out st d_l ogi c_vect or (3 downto 0 ) ) ;
End TB_adder ;
Ar chi t ect ur e Arch_TB of TB adder i s
component FA i s port (A, B, Cin : i n s t d_l ogi c ;
S , Cout : out s t d_l ogi c ) ; end component ;
s i g na l C : st d_l ogi c_vect or (3 downto 0 ) ;
begi n
C(0) <= 0 ;
GEN: f o r i i n 0 to 2 gener at e
INT: FA port map(A( i ) ,B( i ) ,C( i ) ,Y( i ) ,C( i +1));
end gener at e ;
Y(3)<= C( 3 ) ;
end Arch_TB;
OR you can use c ondi t i ons i ns i de gener at e
GEN: f o r i i n 0 to 2 gener at e
i f ( i =0 or i =1) then
INT: FA port map(A( i ) ,B( i ) ,C( i ) ,Y( i ) ,C( i +1));
e l s e
Y(3)<= C( 3 ) ;
INT: FA port map(A( i ) ,B( i ) ,C( i ) ,Y( i ) ,Y( i +1));
end gener at e ;