INTEGRATED CIRCUITS

A single crystal chip of semiconductor containing both

active and passive elements and their interconnections
ON THE BASIS OF FABI!ATION """"
MONOLITHIC, HYBRID
ON THE BASIS OF O#EATION """"""
LINEAR, DIGITAL, INTERFACING
S$A%% S!A%E INTE&ATION 'SSI(
$E)I*$ S!A%E INTE&ATION '$SI(
%A&E S!A%E INTE&ATION '%SI(
+E, %A&E S!A%E INTE&ATION '+%SI(
Advantages of 2D ICs
Small si-e. /eight and cost0
High reliability0
%o/ po/er consumption0
Improved performance0
Fast operation0
L!"!tat!ons
Functions at fairly lo/ voltage0
%imited po/er dissipation0
)ifficult to achieve lo/ noise and high voltage
operation0
#oor high fre1uency performance0
!apacitors and resistors have lo/er ma2imum
values0
#D ICs
$LSI chip used in present day I! technology0
educes gate delays. increases interconnect delays0
$ain portion of po/er used for CL% distribution0
Ne/ So! concepts not compatible /ith 3") I!s0
4") e2ploits vertical dimension to nullify
interconnect delays0
Heterogeneous integration to reali-e SoC
Here the entire chip is divided into a number of
bloc5s0
SYSTEM ON A CHI& 'SoC(
INTE&ATION OF A%% AS#E!TS OF A S,STE$ )ESI&N ON
A SIN&%E !HI#
60 %arge scale integration uses global /ires7transmission
delays.
30 #o/er consumption increases0
40 Soc introduces significant comple2ity in materials and
process integration0
80 The noise developed at the interface is still a ma9or problem0
:0 So! designs typically reduce the number of I;O pins
compared to a system assembled on a printed circuit board
'#!B(
<0 Integration of mi2ed technologies on a single die re1uires
novel design methodologies and tools ./ith design
productivity being a 5ey re1uirement0
#D ARCHITECTURE
In 4) design architecture. and entire '3)( chips is divided into a
number of bloc5s is placed on separate layer of Si that are stac5ed
on top of each other0 Each Si layer in the 4) structure can have
multiple layer of interconnects '+I%I!s( and common global
interconnects0
AD$ANTAGES
The 4) chip design technology can be e2ploited to build
So!s by placing circuits /ith different voltage and performance
re1uirements in different layers0
The 4) integration can reduce the /iring. thereby
reducing the capacitance. po/er dissipation and chip area and
therefore improve chip performance0
Additionally the digital and analog components in the
mi2ed"signal systems can be placed on different Si layers
thereby achieving better noise performance due to lo/er
electromagnetic interference bet/een such circuits bloc5s0
From an integration point of vie/. mi2ed"technology
assimilation could be made less comple2 and more cost
effective by fabricating such technologies on separate
substractes follo/ed by physical bonding0
A&&LICATIONS
#ortable electronics7digital cameras .digital audio
players. #)As==0
One of the largest constraints to gro/th has been
affordable storage. creating the mar5eting
opportunity for ultra lo/ cost internal and e2ternal
memory0
)evice designers often trade application richness to
meet tight cost targets of e2isting mas5 O$ and
NAN) flash non volatile technology
CONCLUSION
The 4 ) memory /ill 9ust the first of a ne/
generation of dense. ine2pensive chips that promise to
ma5e digital recording media both cheap and convenient
enough to replace the photographic film and audio tape0 >e
can understand that 4") I!s are an attractive chip
architecture. that can alleviate the interconnect related
problems such as delay and po/er dissipation and can also
facilitate integration of heterogeneous technologies in one
chip0 The multilayer chip building technology opens up a
/hole ne/ /orld of design li5e a city s5yline transformed
by s5yscrapers. the /orld of chips may never loo5 at the
same again0
3-D ICs
Presented by
HASHIR.A
ROLL NO.
00104025
BATCH VI - A(b)
S7, ECE