WB Course Part 1

Wafer Bonding
18th June 2009

Course Tutor: Tony Rogers,
Applied Microengineering Ltd, UK
AML – Wafer Bonding Machines & Services

Course Schedule
09:00 Introduction of Tutor and Participants

09:15 Wafer Bonding: Theory and Background (anodic bonding).
09:45 Practical issues for anodic bonding (types of glass, flatness
control, compatible materials, temperature limitations,
interconnect methods, alignment etc.)
10:45 Break
11:00 Wafer Bonding: Theory and Background (Si direct bonding)
11:45 Comparison of various wafer bonding techniques (anodic,
silicon direct, glass frit, adhesive, eutectic).
12:45 Lunch
13:45 Wafer bonding techniques – continued
14:15 Applications of wafer bonding
14:45 Break
15:15 Review of commercially available bonding equipment
16:15 Q+A session
16:45 Close

Types of Wafer Bonding
Wafer bonding processes include:
• Anodic bonding (ref’s 1-12, 48)
• Direct (fusion) bonding (ref’s 19,
34-36, 44-46)
• Glass frit bonding (ref 28)

• Eutectic bonding (ref 29,30,31,50)
•Solder bonding (ref 25)
• Adhesive bonding (ref 19,20,33)
•Thermo-compression bonding (ref
19,20,49)

Energy Content of various Bond Types
Bond type Energy content (kJ/mol)
Ionic bonds 590 – 1050
Covalent bonds 563 – 710
Metallic 113 – 347
Van der Waals 4 – 42 (H2)

(intermolecular) bonds:

Energy Content Vs Interatomic Distance for
various Bond Types
Therefore wafers
need to be polished
to (<few nm Ra)
and flat in order for
direct bonding to be
possible.
Ref 33.

Anodic Bonding Theory &
Background

Anodic Bonding Theory &
Background
•Process discovered in 1969 by Wallis & Pomerantz (1)
•Also known as Electrostatic Bonding, Field-Assisted

Bonding, or Mallory Bonding
•Primarily used for bonding Silicon to Glass
•Other material combinations have been demonstrated (2, 3)

Features of Anodic Bonding
•Bonding temperature is below the softening temperature of
the glass
•Thermal expansion of the two materials needs to be well

matched
•Materials must be polished to less than 5 nm and flat (4)
•Process temperatures typically in the range 300 –500oC
•Applied voltages between 100V and 2kV
•Glass needs to contain mobile ions

Description of the Bonding
Process (1 of 5)
•The two wafers are heated to the required temperature
•The wafers are brought into contact
•Voltage applied (glass negative)
•Ionic movement in the glass due to electrolysis (5)
•Depletion of mobile ions at the Si-glass interface
•Voltage drop in the depleted layer produces large
electrostatic attractive force at the interface

Process (2 of 5)
•Wafers are pulled into intimate contact
•Oxygen liberated at the silicon:glass interface (6,7)
•Anodic oxidation of the silicon occurs leading to high
strength Si-O-Si chemical bond (7,8)
•Bond is irreversible (9)
•Composition of the glass is now inhomogeneous (10, 11)
•Bond is hermetic

Process (3 of 5)
- +
Anode + Cathode
-
- Glass +
- +
- O Na +
Silicon
- +
- +
- +
Depletion layer (high field) Bulk (low field)

Process (4 of 5)
ref. (4)

Process (5 of 5)
ref. (4)

Bonding current and the Sodium
depleted layer (source – SensoNor)
- Thermal activation energy for the sodium ions: 0,97 +/- 0,14 eV
3.5 3.5
Bond temp 400 °C Bonding at
I [mA]
3 1000 V 400 OC 3 1000 V
I [mA]
2.5 2.5
800 V 375 °C
2 2
1.5 600 V 1.5 350 °C
1 400 V 1 300 °C
0.5 0.5
0 0
0 20 40 60 80 100 0 50 100 150 200
Time [sec.] Time [sec.]
depleted layer [µm]

1.2
depleted layer [µm]
1.2
The depth of the

The depth of the
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
0 200 400 600 800 1000 300 325 350 375 400
The applied voltage [V] The bonding temperature [°C]
The bonding pressure for “bulk”
bonding(source – SensoNor)
Bonding pressure ~20000 atm with bonding on bare silicon at 800V
Bonding at 1000 V and 400 degC Bonding at 400 degC

25 40
without oxide without oxide
20
30
The electrostatic pressure

The electrostatic pressure
0.1µm oxide
15
[103 atm]
[103 atm]
20
10 increasing oxide thickness 0.1 µm SiO2
5 10
0
0.3 µm SiO2
0 0.02 0.04 0.06 0.08 0.1 0

0 500 1000
Wafer separation air gap [µm] The applied voltage [V]

Strength of the Anodic Bond
•Difficult to measure because when the bonded

sample is pulled apart, the break occurs in the glass
and not at the Si-glass interface
•Values for pull tests are typically 30- 40Mpa (glass

fracture) (12)

Standard Bonding - Typical conditions
Glass: 100mm diameter borofloat 33, 0.5 mm thick, could
have some metallisation (eg Ti/W:Au)
Silicon: 100mm diameter, 500µm thick, could have etched
features (type (p or n), resistivity, orientation not important)
Temperature: 370°C
Voltage: 800 V
Time (that high voltage is applied): 10 minutes
Pre-clamping pressure: 100N (greater pressure exerted by
electrostatic forces anyway, but pre-pressure helps with I vs t
reproducibility)
Alignment accuracy: +/- 5µm (limited by TCE runout)
Total cycle time: 30 minutes
Benefits of Anodic Bonding

•Low bonding temperature giving more process
flexibility (e.g. can bond to metallised wafers without
suffering diffusion of the metals into the wafer)
•Thermally matched, low stress bond producing stable
mechanical dimensions over a wide temperature range
•Procedure can be optimised for producing flat
assemblies
•No measurable flow of the glass occurs, hence sealing
around previously machined grooves, cavities etc.
without any loss of dimensional control

•Since glass is an electrical insulator, parasitic capacitances are
kept extremely small
•Hermetic seals – the bonding process can readily be
performed in vacuum, allowing hermetically sealed cavities to
be formed (or the sealing-in of a special gas mixture)
•Glass transparency at optical wavelengths enables simple, but
highly accurate, alignment of pre-patterned glass and silicon
wafers. The transparency can also be exploited via optical
addressing, and to see inside microfluidic devices

•High yield process – tolerant to particle contamination
and wafer warp
•Low cost wafer scale process for wafer scale
packaging (note: bonding can be done at the chip level
when required)
•High bond strength – higher than the fracture strength
of the glass
•Multi-stack bonding is possible
•Anodic Bonding Review Paper ref 48
Practical Issues for Anodic
Bonding

Control of Bonding Current (1 of 2)
• Anodic bonding has conventionally been done under
voltage limited conditions
• In this mode there is typically a high current spike
(~40mA) at the start
• With a voltage of ~1kV this spike dissipates ~40W at the
interface
• At the start of the bond only selected wafer areas are in
intimate contact
• Therefore Joule heating is large and concentrated, causing
hot spots
Control of Bonding Current (2 of 2)
•The hot spots change the local stress and result in device to
device variation
• The use of current limiting results in a gentle increase in
voltage, and more uniform, lower power dissipation and
hence better device to device repeatability
• This has been demonstrated to significantly improve the
yield in the manufacture of MEMS gyroscopes for which
stress can significantly affect temperature sensitivity
• Current limiting also results in fewer rejects due to voltage
breakdown in the glass.
Anodically Bonded Structures -
some Design Issues
Diaphragms
When bonding to wafers with thin diaphragms, these can
be electrostatically attracted to the glass during
bonding and become permanently bonded. Possible
solutions are to coat the glass in the cavities with gold,
or to back etch the silicon to thin the diaphragms after
bonding.

Bonding of wafers with flexible
structures (source – SensoNor)
V cathode
V cathode glass
Vd ~ V depleted layer glass silicon
0V
Non-bonding overload protection
silicon
Pel
0V screen electrodeglass
press contact
• Electrostatic collapse silicon

• Bonding for structure
Non-bonding overload protection by
use of shield electrodes
Anodically Bonded Structures -
some Design Issues
Access to the silicon surface (e.g. for bond pads)
This can be achieved either by pre-machining through holes
in the glass or by using additional depth-controlled cuts
during the dicing process.

Suitable Glasses
Need good match of TCE to silicon – hence borosilicate glasses
Manufacturer Designation Comments

Corning 7740 Used to be the standard glass for anodic
bonding, but Corning no longer make it
Corning 7070 Has high bonding temperature and low

softening point.
Hoya SD1, SD2 Expensive. Suffers from severe staining and

electrical breakdown. This can be greatly
reduced by backside metallisation.
Schott Borofloat 33 Float glass. Available in a wide variety of
thicknesses. Std low cost glass for anodic
bonding – all wafer sizes
Pilkington CMZ Specifically made for solar cells. Available
only in thin sections. Expensive.

Glass Properties to Consider
• Thermal Expansion Coefficient
• Volume Electrical Resistivity
• Viscosity (Strain Point)
• Chemical Resistance
• Bulk Modulus (Stiffness)

Silicon – Glass Differential Expansion
Ref
(13)

Electrical Resistivity of Glass
• The glass electrical resistivity is important when bonding to
wafers with oxide or nitride coatings, especially when there
are also micromachined cavities defined in these coatings
This is because the percentage of the applied voltage that is dropped
across the coating / cavity depends on the ratio of the coating
resistance to the glass resistance at the bonding temperature.
• Too high a voltage across thin insulating layers and cavities

can cause electrical breakdown

Resistivity
ref. (13)

Glass Viscosity Considerations
• It is necessary to bond at a temperature well below the
strain point of the glass to achieve bonding around
micromachined cavities whilst preventing any measurable
flow of the glass, which could compromise dimensional
control.
• For 7740 glass (strain point 510oC), with a normal
bonding temperature of ~400oC, glass flow is not a
problem. However, for 7070 glass (strain point 456oC)
with a normal bonding temperature of ~450oC, glass flow
becomes an important consideration.

Wafer Stiffness
The stiffness of the wafers can be measured in terms of the
flexural rigidity which is given by:
F = Eh3/(12(1-ν2)
Where E = Bulk Modulus
h = wafer thickness
ν = Poisson Ratio

Flexural Rigidity of Various
Glass and Silicon Wafers
Glass Thickness Flexural Stiffness Ratio Stiffness Ratio
Type (mm) Rigidity Glass / 0.5mm Glass / 0.5mm
(Nm) <111> Si <100> Si
7740 1 5.45 2.69 3.68
7740 0.5 0.68 0.33 0.46

7070 1 4.47 2.20 3.02
Si <111> 0.5 2.03 - -
Si <100> 0.5 1.48 - -
Si <100> 0.1 0.012 - -

Wafer Flatness Considerations
• Silicon wafers are not necessarily flat. Standard SEMI

specifications for Si wafers allows a warp / bow of +/-25μm
• AML’s experience with glass wafers is that these tend to
be much flatter than the Si (typical bow <5 μm)
• When the wafers are bonded, the bow in the Si may be
removed resulting in stress at the interface – depending on
the relative stiffnesses of the two wafers.

Flatness Control
Two sources of bow – thermal; compositional

Can minimise thermal bow by selecting the optimum
temperature for thermal mismatch (provided this is hot enough
to allow bonding to take place).
Composition of glass is permanently altered by the flow of
current during anodic bonding. Excess of Na+ at free surface,
depletion of Na+ at bond interface. This causes the free
surface to go into compression. This needs to be taken into
account for final flatness.

Compatible Materials
Interbond Metallisation – Al no good (oxidation of the Al)
Bonding to oxides (thermal and LPCVD – OK, PECVD – NO)
Bonding to nitrides (LPCVD OK, PECVD - NO)

Compatible
Materials
ref. (13)

Temperature limitations
Generally must have > 300°C (to get sufficient ionic

conduction)

Interconnect Methods
Can use ordinary metal tracks if hermetic seal not needed, or if

only 1 lead across the seal
If need hermetic seal, can use thin Ti/W:Au (up to 50nm), or

use the buried via technique (SensoNor)
Vertical feedthroughs
These can be either in the glass or in the silicon, and are
perhaps the most versatile and reliable method of providing
electrical connection across the seal.

Example of a vertical feedthrough in glass
ref. (16)

Surface Quality
More tolerant of particle contamination than fusion bonding,

because electrostatic force assists movement of bonding front.
Permitted surface roughness a few nm, versus a few Å for
fusion bonding.
Permitted bow up to 50µm for a standard thickness wafer.
Fusion bonding requires a heavy clamping force if there is
significant bow.

Rucking up
This problem can occur with very thin substrates, especially
where there are few cavities built into the glass or silicon.
When bonding is initiated in several places at once (happens
when using a large area electrode), bond fronts will converge
in places on the wafer, and an unbondable bubble will appear.
Can be prevented by using a single central electrode – but
bonding will be slower. Can arrange to involve one or more
additional rings of electrodes as bond front progresses, but
simplest solution is to use a graphite electrode that produces
uniform bonding over the whole interface

Oxygen Generation
The process causes oxygen ions to accumulate at the
bonding surface of the glass (7)
Where there is no silicon to bind to these, oxygen gas is
liberated. The shallower the cavity it is liberated into, the
greater will be the pressure.
This pressure can be considerable. A useful number is
the product of pressure and cavity depth (approximately
1bar.micron)
This pressure can vary across the wafer, according to
how early during the bonding process any particular
cavity has become sealed.

Oxygen Generation
Things to do about this:
•Make cavities as deep as possible, or provide a channel
to a large volume reservoir
•Leave cavities unsealed, and seal as part of the
packaging process.
•Incorporate a getter inside the cavity

Effect on CMOS Devices
High electrostatic field can have damaging effects on CMOS
devices:
“ … the electrostatic bonding between silicon and glass affects the electrical
characteristics of the silicon. The presence and the movement of the positive and
negative ions through the glass, the formation of a thin oxide layer at the interface
and the related charging effects, cause changes in the resistivity of the silicon
underneath the glass, in the breakdown voltages and the leakage currents of the p-n
junctions.(15)”
AML is currently developing a technique that will allow the

use of anodic bonding with CMOS devices, provided that the
CMOS circuit is designed for compatibility with the anodic
bonding process.

Bonding to Bulk Micromachined Wafers
• Micromachining of both the Si and glass wafers is
possible prior to bonding
• All standard wet and dry etching techniques can be
used for the Si
• Glass machining can be achieved via:
¾Ultrasonic machining
¾Laser processing
¾Water-jet machining
¾Powder blasting
¾Chemical etching

Bonding to Surface
Micromachined wafers
• Bonding to silicon that has surface layers of thermal
oxide and LPCVD nitride has been demonstrated
• PECVD layers can be problematic due to the presence
of hydrogen, which makes the oxygen unavailable for
bonding to the silicon
• Hermetic sealing can be achieved over metallisation
tracks provided that the step height is <50nm (13).
• Readily oxidisable metals such as aluminium should
be avoided (13).

Thin Film Bonding
Can bond two silicon wafers together, using a thin sputtered,
evaporated, or sol-gel deposited glass film.
General problem is there is usually not much thickness of
glass. Therefore limited supply of Na+ and O 2- ions
Sputtering is a slow process, but should result in a layer with
the same composition as the sputtering target.
Evaporation is another method that can be used
Sol-gel is currently under investigation as a possible method

Thin Film Bonding
General issues with thin-film bonding:
• Flatness control
• Thickness control (electrical breakdown)
• Roughness control
•Therefore we recommend that unless there are good specific

reasons for using this technique then it should be avoided

Multi-stack Bonding
• Can build up more complex sandwiches of glass and
silicon.
• Both silicon:glass:silicon & glass:silicon:glass are
possible
• Both can be performed using a two-stage bonding
process
• Often find that 2nd bond is more difficult to make than
the first, usually because a finite amount of bow has
been introduced, and the assembly is now also stiffer
than just the silicon.
With AML bonders we have a simple process for both

Multi-stack Bonding
Si-glass-Si
•This can be done in two stages; i.e. one silicon wafer is
bonded to the glass. Then the 2nd bond is made
•With AML bonders we have a simple process for doing
this 2nd bond
• The bonded wafer pair is mounted on the upper platen,
glass side down, and the 2nd bond done as normal
• It is often necessary to use slightly higher temperature /
voltage to overcome the bow of the first bond
• Alignment can be achieved using IR optics, or visible
if there are appropriate holes machined in the Si

Multi-stack Bonding
glass:Si:glass
•This can be done in two stages; i.e. one glass wafer is
bonded to the silicon. Then the wafers are turned over,
and the other glass wafer is bonded on.
• The problem is making electrical connection to the
central Si wafer
•With AML bonders we have a simple process for doing
this
• Alignment can be achieved for all three wafers
provided the Si wafer is patterned on both sides
• Care needs to be taken not to bond the lower glass to
the platen!
Multi-stack Bonding in
One Step
With appropriate design and switching of the electrode

HT supplies, the operation can be carried out in one step.
This minimises the problem of bow.
More difficult to achieve alignment with one-step
bonding (especially if both glass wafers need to be
aligned to the silicon)

Silicon Direct Bonding
Process
Hydrophylic bonding
Hydrophobic bonding

Schematic of hydrophilic direct bond formation,
before annealing (ref 19)
Silicon Direct Bonding Process
•Bring clean, polished surfaces into intimate contact
• Forms reversible low strength bond

•Heat to form stable / permanent bond
•Results in nearly perfect high-strength bond

Bonding Kinetics – first contact
• Attractive forces – hydrogen bonding / van der
Waals force
• Repulsive forces – strain energy of wafer bow /
warp
• Attractive force across bonded area must
counteract repulsive force of the induced strain in
wafers as the surfaces are brought into intimate
contact
• Initial hydrogen bond converted to higher strength
bond by heat / time / pre bond activation treatment

Direct Bonding Video

Crack Propagation (Si-Si direct bond, post 450C anneal)
Video of crack propagation

Strained Attraction
• Surface bow and waviness can be overcome by elastic

deformation of the wafers. Surface roughness can be
overcome if the range of the hydrogen bonding attraction is
large enough (e.g. water molecule triplets (ref 19 p.59))
• Bonds can self propagate from an initial contact point if the
range and magnitude of the attractive forces is high enough
to overcome the roughness, waviness and bow of the
wafers
• Wafers can be forced into contact. If the bond area is made
large enough the bond may not delaminate (ref 34)

SiO2-SiO2 Hydrophylic Direct Bonding
SiO2 Surface
•Pre-Bond
Hydration–SiO2
terminates in Si
dangling bonds
that react with
water
•Heating (200ºC) –
Hydrogen bond
bridging develops
SiO2 Surface between OH groups
•Post-Bond (>300ºC)
–Hydrogen bonds are
replaced with Si-O-Si
bonds
• Further anneal at
~1000oC for full
strength

Si-Si Hydrophobic Direct Bonding
To prepare wafers for hydrophobic bonding it is necessary

to remove the surface oxide. This is normally done using
an HF dip
After the dip the wafers can optionally be rinsed in DI

water. If this is done then the mechanism for bond front
propagation is essentially the same as for the hydrophylic
case

Si-Si Hydrophobic Direct Bonding
Silicon Surface
•Pre-Bond Hydration
–dangling Si bonds
react with water
•Heating (200ºC) –
Hydrogen bond bridging
develops between OH
groups
Silicon Surface
•Post-Bond (>300ºC) –
Hydrogen bonds are
replaced with Si-O-Si
bonds
•Completion (>500ºC) –
Si-O-Si bonds are
replaced with Si-Si

Si Hydrophylic Direct Bonding –
Process info
Hydrophilic: RCA Clean
25°C - 110°C: Hydrogen bonds
110°C - 200°C:
Si + 2H2O → SiO2 + 2H2
200°C - 700°C:
Si — OH + OH — Si →
Si – O – Si + H2O
>700°C:
Increasing contact area; further
hydrogen removal
Si Hydrophobic Direct Bonding –
Process info
Hydrophobic: (HF Dip)
25°C - 400°C: van der Waals
400°C – 700°C:
H desorption
>700°C:
H completely removed: bond strength
equal to bulk Si

Si-Si Direct Bonding – Bond Strength
Bond strength vs. anneal temperature for hydrophilic /

hydrophobic bonding.
Si-Si Hydrophobic bonding
For applications whereby the bond interface needs to be
oxide-free then it is best to omit the water rinse after HF dip
The bond propagation is the driven by fluoride bonding

rather than hydrogen bonding

Wafer Bond Strength
SiO2-SiO2 Bond Strength
• increases with increasing temperature
• does not depend on oxide thickness

• not a strong function of annealing time for temperatures below 1200ºC
• increases with annealing time for temperatures above 1200ºC
• Easier to form pre bond, lower requirements of wafer surface w.r.t. Si-Si
bond
Si-Si Bonds Strength

• very strong -bonds performed at 500ºC are equivalent to SiO2-SiO2
bonds performed at temperatures > 1000ºC
• Si-Si bonds performed at > 600ºC can be too strong to measure
• More difficult to form pre bond / higher requirements of wafers

Quality of a Si Direct Bond
Silicon Surface
Oxide Interface
Silicon Surface
•Nearly perfect bond

•Fractures do NOT follow bond

Si-Si Bonds using UHV Direct Bonding
If Si wafer are heated up to >850C in UHV

(<2×10Silicon
-8 Torr), Surface
then a super clean Si surface can
be achieved, where OH groups, H2O and H is
Oxide Interface
removed from the surface to leave highly reactive
Si. Two wafers can be bonded under these
conditions to give a true Si-Si hydrophobic direct
Silicon Surface
bond. Alternatively a gas can be allowed into the
chamber to terminate the Si with selected
molecules. This technique can allow the bond to
be tuned for specific applications.

Imperfectly Bonded Wafers
Particulate
•Void Formation (mm-scale)

–insufficient wafer flatness
–surface contamination
–particulates
•Extreme Cleanliness Needed!!
Si-Si Direct Bonding – Wafer
Specifications
¾ Ra Surface Roughness: <1nm (ideally < 0.5nm Ra)

¾ Flatness / TTV: <2μm
¾ Bow: <25 μm (single peak)
Other Requirements
¾ Recessed alignment marks
¾ Class 10 cleanliness

Wafer Cleaning
Schematic of wafer surface before cleaning

Wafer Cleaning _issues with Organic
contamination / H2O inclusion
•Depending on the latter annealing stages, organic
contamination can cause significant defects in the bond. If a high
temeprature anneal step is performed (over 300C) then organics
can result in void formation. Cleaned Si surfaces can easily trap
organics, especially if hydrophobic.
•A UV organic removal cleaning step immediately before
bonding can be recommended.
•Interface H2O can also cause voiding at elevated temperature –
need to optimise surface H2O to minimise voiding, but allow
bond propagation.
•Appropriate anneal temperature ramp rate can minimise H2O
voids (ref 47)

Wafer Cleaning _issues with Organic
contamination / H2O inclusion
IR image of pre bond. Some IR image of post 800C annealed

particle related voids. bond. Voids caused by organic
contamination generating gas
during the anneal
Bonding Criterion
• Successful bonding requires intimate contact of wafers
• Flatness deviations prevent bonding
• Moderate flatness deviations can be accommodated
through elastic deformation
wafer bow surface waviness surface roughness
<10 A
10-100 μm
100-1000 μm
100 mm
Bonding is a competition between surface and strain energy.
Surface Roughness – Ra can be
misleading
Same
Ra.
Overall bond strength is a function of the contact area therefore

the greater the surface contact then the higher the bond strength
Hard to bond surface Easy to bond surface
•Bearing Ratio should be considered in conjunction with Ra

Example of a “easy to bond” surface – Bearing Ratio / Firestone Abbot Curve
Example of a “hard to bond” surface– Bearing Ratio / Firestone
Abbot Curve
Additional Factors
etch pattern mounting
100 mm
100 mm ~1 μm
particles
~1 mm
(Ref’s
35,36)
~1 mm
Modeling Approach
• Surface forces expressed
in terms of work of
adhesion
• Balance between surface
and strain energy
• Each flatness deviation
increases the strain energy
inBonding Criterion:
the bonded stack
dU E
≤W
(Ref’s 35,36) dA
Axisymmetric Analysis of
Bowed Wafers (Ref’s 35,36)
silicon wafers, E=150GPa, ν=0.22, ρ=10m
Strain energy accumulation rate:
where: advance ratio, R=b/a

initial curvature, κo=1/ρo
Wafer thickness is critical
final curvature, κf = 1/ρf Must have one compliant wafer
Effect of Etch Patterns (Ref’s 35,36)
• Reduce bonding area
and energy available
to deform wafers
• Shallow features
– reduce surface
energy
– do not effect
stiffness
• Deep features
– reduce surface
energy
–reduce stiffness
Effect of Etch Patterns
(Ref’s 35,36)
Comparison of model results with actual bond.

Low Temperature
(Plasma) Activated
Direct Bonding

Plasma Activated Direct Bonding
• This is an important development in the last few years and has been
subject of extensive R&D
• Enables full strength Si:Si (SiO2:SiO2) at temperatures as low as 200oC
• The mechanism is not fully understood but linked to “dangling bonds”
• Very short plasma exposures needed (~30s) makes in-situ process
viable
• Opportunity for removing expensive, difficult to dispose wet chemicals
• Makes direct bonding more attractive process (temperature compatible)
• Enables otherwise non-compatible materials to be bonded (eg GaAs:Si,
quartz:Si etc.)

Plasma Activation / Low Temperature
Direct Bonding
Comparison of activated & Non-activated Bond Strength

vs Anneal temperature
Plasma Activation
Process Conditions
• Wafers are exposed to brief low power plasma
• Typical RIE plasma power of ~50W-200W,
• Exposure time ~20 sec to 200 sec
• Increased plasma exposure roughens surface
• Water dip post exposure - can improve quality but
compromises bond strength vs. anneal curve
• Oxygen is most common plasma, also N2 and Ar.#
• H2 plasma can be used to create hydrophobic surface

Plasma Bonding Notes
• Strong bonds can be achieved at anneal temepratures of 200C
• Bond interface will be porous –
• Therefore may not be suitable for hermetic sealing

Surface Activation Using
Radicals (RAD Activation)
• Exposing wafer surfaces to Plasma can
cause roughening of the surface = narrow
process window (ref 44)
• Exposing wafer surface only to the Radical
components of the plasma achieves bond
strength without roughening wafer surface.

Radical Activation
¾AFM results showing Surface Characteristics vs
Activation Time
Sa
Sa
Wafer Process Pressure Time Topographic
Phase (˚)
(nm)
1 0.51 0.17
2
2 1 0.18
3 0.84 0.75
Plasma 65mTorr 5
4 0.52 0.29
5 0.42 0.26
10
6 0.34 0.24 AML
7 0.58 0.14 data
2
8 - -
9 0.42 0.1
RAD (Air) 60mTorr 5
10 - -
11 0.16 0.13
10
12 - -
13 0.18 0.14
None - -
14 0.19 0.12
15 Plasma 200mTorr 2 - -

Radical-Co-axial Source
Gas supply
Only Earthed screen

radicals
in this
region
Source
Source
DC source
Wafers
for in-situ
activation
R. pump

Radical Activation Tool
Experimental set-up using glass vacuum chamber – showing

electrical discharge confined between the ring electrodes
Radical Activation
XPS spectra showing comparison of silicon wafer
before and after activation by Oxygen Radicals
Spectra of untreated and treated silicon Spectra of untreated and treated silicon
Untreated Centre
6000 6000
5000 5000
4000 4000
Counts per second
Counts per second

3000 3000
2000 2000
1000 1000
0 0
1000 800 600 400 200 0 1000 800 600 400 200 0
Binding energy /eV Binding energy /eV
Shows reduced carbon peak post exposure

Plasma Activation / Low Temperature
Direct Bonding
•A drawback with plasma activated bonding is the

long term stability of the interface.
•Electrical measurements have been made on plasma

activated wafers which have been stored for 5 years.
•These show the capacitance across the interface, and

the resistance of the interface changes with time.

Direct Bonding of
Substrates Other Than Si
• Low tempature activated bonding means dis-similar
substrates can be joined (CTE mismatch less important)
• Surafce roughness/ flatness requirements the same (or
better) than Si case, hydrophilic / hydrophobic
considerations apply
•Important substrates are Quartz – Quartz; Pyrex –
Pyrex (pharmasutical); Si – Pyrex (replaces anodic
bond) and Si – Sapphire (SOI)

Dissimilar substrates
• Important emerging technology – engineered substrates,
e.g. Si on sapphire, Si on Quartz – improved CMOS /
optoelectronic performance. (Ref 45,46)
• Different CTE materials need to be joined = requirement

for low temperature bonding / smart cut process in order to
minimise CTE induced strain.
• Need to effect the smart cut process without causing bulk

material fracture / bond delamination.
• After smart cut a high temperature anneal can be used to

remove / diffuse interface species (OH groups).

Dissimilar substrates
• Contacting wafers at intermediate elevated temperature can
increase the working range and allow smart cut temperature
to be achieved without fracture / delamination.
• May also need to contact at high temperatureif the bonded

pair is going to need further processing – eg if the TCE
mismatch allows a 200C temperature range after bonding
and the device needs to work at RT but will require further
processing at 400C, the best to contact the wafers at 200C
• Note that it is necessary to maintain some water on wafer

surfaces and so contacting at higher temperatures may not
result in bondfront propagation

Alignment of Si-Si Bonded Wafers
Can use IR optics, “front & back” camera
systems (eg EVG), or use wafer movement to
enable optical path to both bonding surface
(eg Suss)
Double side polished wafers, with back-side
alignment marks are necessary for the “front
& back” method

IR Alignment of Si-Si Bonded
Wafers
• Accuracy of IR alignment depends on the nature
of the Si wafers
• Double side polished wafers- resolution of
alignment features is dependent on imaging
system and wavelength of light, 2μ accuracy
possible
• Single side polished wafers- resolution limited by
the roughness of the back surface, typically 10-20
μ features can be resolved

Bond Inspection
Techniques
• 3 main techniques for inspecting bond quality
• Optical transmission, using visible and IR light
• SAM (Scanning Acoustic Microscopy)
• XRT (X Ray Topography)
• TEM (Transmission Electron Topography) limited use but
best resolution
ref 19,20

Optical Transmission
• Photon energy hν ≥ Bandgap Eg, photons can
break bonds in material and easily be absorbed
• If ν < Eg/h then photons can travel through the
material
• Standard exponential absorption relationship with
material type and material thickness , Iz = I0exp(-
αZ)
• Photons can be absorbed by free carriers (hence
metals are opaque). Heavily doped materials do
not transmit.

material bandgap (eV) min wavelength (um)
Material Bandgap vs. Minimum Transmissive Wavelength
Ge 0.67 1.85
Si at 600K 1.03 1.20
2
Si 1.12 1.10
m a te r ia l m in b a n d g a p (e V )
Ge at 600K 1.28 0.96
InP 1.35 0.91 1.5
AlGaAs 1.42 0.87
GaAs 1.43 0.86
1
AlAs 2.16 0.57
a SiC 2.2 0.56
b SiC 2.93 0.42 0.5
GaN 3.4 0.36
ZnS 3.6 0.34 0
C 5.48 0.22 0 1 2 3 4 5 6 7 8 9
AlN 6.2 0.20
min tramsmission wavelength (um)
SiO2 8 0.15
• As material temperature increases min transmission

wavelength increases
• CCD cameras only effective to ~1.1μm so Si at 300C not
easy to image through

Optical Transmission
• For 1.1μ light only voids with a depth of λ/4 can
be imaged.
• Depth of void can be estimated from number of
fringes (N) using D = N×(λ/4 )
• Typically a 1mm void can be seen. Smaller
features can be seen using an IR microscope
• Non destructive technique
• Cheap and quick to setup and get results
• Poor resolution relative to other techniques

Scanning Acoustic
Microscopy (SAM)
• Acoustic waves, typically 10-200MHz focused on bond
interface, reflected waves measured
• For 160MHz scan, resolution of 10μm
• Attenuation increases with increasing frequency = better
resolution but smaller signal
• Sample must be in liquid coupling medium, e.g. DI water.
Therefore no use for weakly bonded substrates
• Results can be confusing if voids are not homogeneous
• Better resolution than optical transmission but more
expensive and slower

X-Ray Topography
(XRT)
• Offers best resolution (2μ) but only of use for
crystalline solids
• X-ray beam diffracted according to- n λ=2dsinθ (θ
= Bragg angle, d = lattice spacing)
• Gives info on voids plus elastic and plastic lattice
distortion
• Very slow technique, difficult to set up.
• Very expensive systems

Transmission Electron
Microscopy (TEM)
• Need to thin samples to 1000~3000A

• Very high resolution (2A)

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Wafer Bonding

18th June 2009

AML – Wafer Bonding Machines & Services

09:00 Introduction of Tutor and Participants

AML – Wafer Bonding Machines & Services

• Glass frit bonding (ref 28)

AML – Wafer Bonding Machines & Services

Bond type Energy content (kJ/mol)

Ionic bonds 590 – 1050

Covalent bonds 563 – 710

Metallic 113 – 347

Van der Waals 4 – 42 (H2)

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

•Also known as Electrostatic Bonding, Field-Assisted

•Primarily used for bonding Silicon to Glass

•Other material combinations have been demonstrated (2, 3)

AML – Wafer Bonding Machines & Services

•Thermal expansion of the two materials needs to be well

•Materials must be polished to less than 5 nm and flat (4)

•Process temperatures typically in the range 300 –500oC

•Applied voltages between 100V and 2kV

•Glass needs to contain mobile ions

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

Depletion layer (high field) Bulk (low field)

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

depleted layer [µm]

The depth of the

Bonding at 1000 V and 400 degC Bonding at 400 degC

The electrostatic pressure

0 0.02 0.04 0.06 0.08 0.1 0

AML – Wafer Bonding Machines & Services

•Difficult to measure because when the bonded

•Values for pull tests are typically 30- 40Mpa (glass

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

Vd ~ V depleted layer glass silicon

• Electrostatic collapse silicon

AML – Wafer Bonding Machines & Services

Manufacturer Designation Comments

Corning 7070 Has high bonding temperature and low

Hoya SD1, SD2 Expensive. Suffers from severe staining and

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

• Too high a voltage across thin insulating layers and cavities

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

AML – Wafer Bonding Machines & Services

7740 0.5 0.68 0.33 0.46

AML – Wafer Bonding Machines & Services

• Silicon wafers are not necessarily flat. Standard SEMI

AML – Wafer Bonding Machines & Services

Two sources of bow – thermal; compositional