SOC

(System On a Chip Design - The future of

VLSI)

Abstract

This paper describes the SOC development, design through production,

using mixed-signal ASIC technology. The design process and its benefits are described. Topics
include mixed-signal design practices, the integration of multi-vendor IP, the step-by-step
integration of non-volatile memory, SRAM, microprocessor, I/O interface, and analog circuitry
onto a single low-cost chip. Some of the challenges encountered with the design such as the
voltage requirements for the RS-232 drivers and flash memory programming will be discussed.
Also included is a description of the circuit design techniques, including how immunity to
reverse engineering was achieved.
System-on-a-Chip

Highly competitive consumer product manufacturers can benefit from current

VLSI technology to employ a system-on-a-chip (SOC) device. The motivation to do so is the
prospect of reducing a circuit board full of components into a single low-cost integrated circuit.
The unique expertise to create such a device is available through third-party design companies or
through fabless semiconductor companies that can provide a complete design-through-
production solution.
This paper describes a representative consumer product that has all active
electronics implemented in a single integrated circuit. This includes the integration of non-
volatile memory, SRAM, Intel-compatible 8051 microprocessor, I/O interface, and analog
circuitry onto a single low-cost chip. In addition to providing a description of the design process
and benefits, this paper describes some of the challenges encountered with the design, in
particular the voltage requirements for the RS-232 drivers and flash memory programming.
These negative and higher voltages are more geared toward a bipolar or BiCMOS process than a
CMOS implementation. It also includes a description of the circuit design techniques employed
to implement this RS-232 driver in CMOS.

Leveraging mixed signal technology

The integration of the processor, non-volatile flash memory, SRAM, and analog
functions onto a single chip allows the creation of highly integrated SOC devices. Many products
can have their entire electronics workings implemented in a single VLSI circuit. Top-down
behavioral digital design in combination with modular analog building blocks allows the cost-
effective creation of SOC devices. This is particularly true when a working model for the design
is implemented using discreet components and field programmable gate arrays (FPGAs). This
bread-boarding approach allows the design to be developed and debugged before any expense or
risk associated with an application specific integrated circuit (ASIC) is incurred.
Discussed here is the creation of a SOC device for a PC peripheral that reads and
processes information contained on the magnetic strip from a credit card, with emphasis on the
input / output and processor requirements which are generic to a wide variety of SOC
applications. Particular attention is paid to some of the unique challenges encountered in
implementing an RS-232 bus driver / receiver on a CMOS process.

The technical requirements for this application include on-chip processing, program
code that is immune to reverse engineering, universal serial bus (USB) interface to a PC, and an
RS-232 interface to allow the connection of the peripheral to legacy point-of-sale systems. This
is a consumer product, so it must be built for an extremely low cost and be efficiently
manufacturable in high quantities. Additionally, periodic software upgrades require that program
code be stored in re-writable non-volatile memory versus mask ROM.
Protection from reverse engineering and security defeat is greatly enhanced by including
flash memory in this single chip device. Flash memory is particularly immune to contents
tampering because the physical state of the bit (i.e. 1 or 0) cannot be determined through
microscopic inspection or destructive physical analysis. It is relatively easy to protect and
obscure the read circuitry in the design so that it is impossible to download the flash memory
code contents. By design, no proprietary or security details can be determined from external pins
to the device. Therefore, the processing algorithm and security features are easily protected from
attempts to reverse engineer the device.

Design Overview
As illustrated in Figure 1, the board level design that is to be converted into an SOC
(System On Chip) ASIC device is a very typical, complete microcontroller-based system. The
design includes all of the building blocks associated with a small system application, including
microcontroller, serial I/O (USB 1.1 and RS-232), analog input, SRAM, and non-volatile
memory. All of these functions can be readily implemented in a single SOC device by employing
some cleaver analog design techniques to comply with the RS-232 voltage requirements, and to
select the required building blocks from commercially available IP (Intellectual Property) or
internally developed sources. This chip development pulled a combination of all of these
resources together in order to create the end product. The RS-232 driver development is
discussed in detail in this paper because it exploited the unique features of the selected mixed-
signal process capabilities more than any other requirement.
 The A/D was developed for this chip, and the specific architecture is described in some
detail. The USB 1.1 device controller core was a purchased IP that was procured from an outside
source and integrated into the design; likewise for the Intel™ compatible 8051 core. The 8051
and USB cores are available from a variety of IP suppliers, and each of these can be evaluated
for features and value for a given application. The USB 1.1 compatible I/O physical serial
interface was available internally. A block of digital logic was developed for the board level
implementation using an FPGA, and this was converted using the logic synthesis tools described
in this paper.
Functional features
A block diagram for the prototype board that was converted into a system-on-a-chip
(SOC) device is illustrated in Figure 1. The design includes the following components:
· 80C51 microcontroller
· Flash memory
· SRAM
· Monolithic USB device protocol driver with built-in USB bus drivers
· 12-bit A/D
· RS-232 bus driver / receiver
· Monolithic magnetic strip reader
· 20K gate FPGA (to implement some custom logic functions and to accommodate the “glue
logic” for all of the components)
· Precision monolithic crystal oscillator
The design problem solved in this endeavor process selected has is the integration all of
these functions onto a single SOC ASIC device. Some of the biggest intrinsic challenges are in
the area of non-compatible voltages. Specifically, replacing the board level de This SOC
application requires a substantial amount of program code (32K bytes). This amount of memory
is too great to affordably implement using embedded EEPROM, but is well within the density
capabilities of embedded flash memory. As mentioned previously, software upgrades and
protection from reverse engineering discourage the use of mask ROM and are best served with
flash memory.
The product interfaces to an IBM-compatible personal computer via the commonly used
USB 1.1 interface that allows hot swapping and plug-and-play capability. The peripheral product
can be connected directly to any IBM- compatible personal computer that is running Windows
98 or greater. The ASIC contains a macro function that implements a fully-compliant sign
requires an RS-232 driver capable of driving to –5V to +5V. This necessitates a 10V breakdown
voltage, while at the same time, digital logic requires 3.3V operation. The design requires some
specialized process features to accommodate bipolar supply voltages. Since everything has to
operate from a single 5V supply, it is necessary to implement on-chip voltage regulation to
convert the 5V supply voltage to 3.3V for the digital logic core and, via a charge pump, to create
the –5V to +5V bias levels for the RS-232 driver. An additional charge pump is required to
generate the 10V level necessary to perform on-chip programming of the embedded flash
memory. The mixed signal CMOS features that facilitate this integration of disparate voltage
levels.
Embedded processing
This system-on-a-chip application is based on the ubiquitous 8-bit Intel®-compatible
8051 microcontroller used in millions of embedded applications. Other microcontrollers, such as
the Motorola®-compatible 68HC11, are equally applicable and can be similarly supported in
SOC designs.
Program code
This SOC application
requires a substantial amount of
program code (32K bytes). This
amount of memory is too great
to affordably implement using
embedded EEPROM, but is well
within the density capabilities of
embedded flash memory. As
mentioned previously, software
upgrades and protection from
reverse engineering discourage the use of mask ROM
and are best served with flash memory.
USB Interface:
 The product interfaces to an IBM-compatible personal computer via the commonly used
USB 1.1 interface that allows hot swapping and plug-and-play capability. The peripheral product
can be connected directly to any IBM- compatible personal computer that is running Windows
98 or greater. The ASIC contains a macro function that implements a fully-compliant USB 1.1
protocol device controller. The ASIC also includes USB compatible I/O cells that allow the USB
cable to be driven directly by the ASIC.

Clock oscillator
The design requires a fairly high precision clock. There are three ways to accomplish
this, ranging from simple but relatively expensive, to more challenging but very inexpensive.
The board level prototype employs the simplest but most expensive solution, which is a
monolithic crystal-controlled oscillator. However, the very lowest cost solution is to implement
an oscillator that relies on an external resistor (only). This is lower cost than using either an
external monolithic oscillator or crystal. The ASIC requires the integration of this precision
oscillator into the PLL (Phased Lock Loop) function. A precision oscillator based on an external
resistor requires an on-chip precision capacitor. Since it is not possible to fabricate an on-chip
capacitor with great precision, the design employs what is referred to as active trimming.
Conceptually, active trimming employs non-volatile memory (flash memory in this case) to set
switches to invoke various trim values (i.e. different capacitors that are switched into the circuit
in parallel). The configuration for this trim value is accomplished during test, and the required
setting is loaded into the chip by the IC tester during final test of the product. The net result is a
precision clock that exhibits better than +/- 2% accuracy and stability. This offers the level of
accuracy normally associated with a crystal controlled oscillator, but at a cost that is only a few
pennies, versus the cost of a monolithic crystal controlled oscillator which is between 50 cents
and a dollar.
Sensor Interface
No mixed-signal design is complete without some analog functionality. This particular
SOC product must accept an analog input from a proprietary sensor and convert the information
into digital information. An analog to digital (A/D) converter is employed to accomplish this
function. The analog input signal has characteristics that include the following parameters:
· Voltage range from 0 to 5V
· Frequency components that can range from DC to 20K Hz
· A required precision of 1 part in 2048 (11-bits)
This requires a 12-bit A/D with an absolute accuracy of +/- 1 LSB. The Nyquist criteria
dictates that a signal must be sampled at a minimum of twice the frequency of the signal that
must be digitized. Thus the A/D required a sampling frequency of 40K Hz as a minimum. A
frequency of 50Hz was selected to eliminate any harmonic interference, and is also a simple
division of the basic 10 MHz system clock rate. The A/D required to sample this signal could be
readily implemented on-chip. As such, the mixed signal ASIC includes a 12-bit, 50 ksp (kilo
sample per second) A/D. The specific A/D architecture employed is referred to as a “Successive
Approximation” A/D. In its simplest description, a successive approximation A/D consists of a
comparitor and a Digital to Analog (DAC) converter. A DAC generates an output voltage that is
simply a conversion of the binary value placed in its input register. The analog input signal is
captured in a “hold” circuit which charges a capacitor to the value of the input signal. The
conversion process successively compares the sampled input signal to values that are placed in
the DAC. Figure 3 illustrates a block diagram for the A/D. The conversion process for a
successive approximation A/D can be described as follows:
• If the DAC output is greater than the analog input, the MSB in the DAC is reset,
otherwise it is left set
• The process is repeated with each bit in turn, until the test on the LSB is made (i.e. the
next comparison is 010000000000 or 110000000000 depending on result of
previous comparison, etc.
• Once all bits are compared, then the conversion process is complete, and the DAC input
register will contain the digital representation of the amplitude of the analog input signal
at the instant that the signal was sampled.

RS-232 interface
The RS-232 serial bus interface has been in use since the 1960s and remains a popular
serial bus present on most PCs and point-of-sale terminal equipment. It offers bus length
advantages versus USB, which is limited to 5 meters. It also represents one of the greatest
challenges for implementation on a SOC device. Specifically, the RS-232 bus requires that the
signal drive from a negative voltage level to a positive voltage level. While this is very easy to
do using bipolar processes, it represents a considerable challenge in CMOS. The ASIC described
here requires a drive level on the RS-232 bus of –5V to +5V.
The I/O driver necessary to drive to these –5V to +5V levels exploits the mixed signal
CMOS isolated P well feature, allowing a negative voltage bias for the P-doped well. The
complementary N-doped transistor is combined with this isolated P-doped transistor to create a
transistor pair capable of driving from –5V to +5V. The other process attribute necessary to
accomplish this is a high breakdown voltage. Specifically, a thick oxide isolation is used that is
capable of withstanding the 10V potential that exists between the isolated P well and deep N
well. The transistor pair structure is illustrated in Figure 4. The mixed signal CMOS process has
what is referred to as a dual-gate oxide option. This basically means that the device can contain
both “high voltage” (i.e. high breakdown voltage for gate oxide), and conventional 0.35 um
digital logic levels (i.e. thin gate oxide, which is designed for 3.3V operation). Exploitation of
these process features allows integration of functions requiring disparate voltages into a single
device.

Design interface
Product manufacturers develop expertise specific to their core competencies. It is often
desirable or necessary for them to rely on the ASIC supplier for detailed integrated circuit design
expertise. For this project, all analog design, memory design, circuit layout, mixed-signal design
integration, and test program development are performed by the ASIC supplier. The
manufacturer who developed the card reader product furnishes the ASIC supplier with a block
diagram and a prototype design that employs discreet microcontroller, memory, various I/O and
peripheral functions. All random digital glue logic is implemented in a field programmable gate
array (FPGA) device. The specific FPGA device used is not particularly important, since the
design files for most FPGAs can be readily translated into the ASIC supplier’s netlist
implementation using Synopsys™ or Mentor™ logic translation tools.

This design path allows the manufacturer of the card reader to develop and debug the
design in a highly efficient and low-cost manner. The FPGA can be changed many times during
the development process as the design progresses through qualification. Program code for the
8051 microcontroller is modified using In-Circuit Emulation, and, thus, can be changed and
updated real-time. No major expense or risk of ASIC implementation needs to occur until the
design is completely verified and debugged.

A division-of-labor table is illustrated in Table

1. In this case, the ASIC supplier addresses all
chip design expertise. This precludes the need
for the card reader manufacturer to possess or
gain expertise in the design aspects of creating
a mixed-signal ASIC. Instead, they provide the
breadboard design and FPGA description, and
the ASIC supplier is tasked with the chip
design.

Some of the biggest design challenges with a SOC design are the separate and unique
disciplines involved in the design. Specifically, this design requires five unique areas of
expertise, including:
• Analog design for the RS-232 transceiver, USB transceiver, and charge pumps;
• Digital behavioral level design expertise for the synthesis of the 8051 IP (Intellectual Property)
and the USB 1.1 protocol IP;
• Digital behavioral design also for the transfer of the customer supplied FPGA which needs to
be retarget for incorporation into the ASIC;
• Memory design for both the SRAM and the particularly challenging embedded flash memory;
• Physical layout design (i.e. creating the actual physical implementation of the “artwork” for the
ASIC).
• Creation of the mixed signal test program.
The creation of the test program is made more unique by the combination of skills
necessary to test a circuit that contains both analog and digital attributes. One interesting
technique employed in the test program is to program the flash memory with the program code
supplied by the card reader manufacturer during test. This step allows the card reader
manufacturer to insert the ASIC directly into the assembly of the product without a time-
consuming and expensive step of programming the devices.
 Although the physical layout process for the digital standard cell library is quite
automated, the analog circuitry is laid out using CAE tools that require a good deal of human
interaction and physical placement of the structures. A memory compiler is employed that
generates a physical layout for the specific width and depth required for the desired memory
structures. Memory compilers are employed for both the flash and SRAM structures.

Conclusions
State-of-the-art system-on-a-chip technology can be successfully employed to create a single
chip product. The design created via this process is, for all practical purposes, immune to reverse
engineering. Since the silicon real estate and package complexity is modest, the recurring cost
for such an ASIC device is very low and represents a considerable savings versus the multiple
chip board level equivalent circuit. Combining all of this functionality into a single ASIC
reduces device count, board space, component cost, manufacturing cost, and improves reliability
and manufacturability.
References

1. www.google.com
2. www.esda.org
3. www.esd-toolkit.org
4. www.esd-electronics.org
5. IEEE MAGAZINES