Chapter 2

Introduction to computer organization

2.1 Functional Units
CPU Central Processing Unit, which includes:
o ALU Arithmetic and Logic Unit
o Set of registers (including program counter keeping the address of the next
instruction to e performed!
o Control Unit decoding instructions and controlling internal data
mo"ement among different CPU parts
o #nterface Unit mo"es data etween CPU and other hardware components
Memory
o $he %ain %emor& Primar& Storage or 'A% 'andom Access %emor&
(olds data or a piece of a program code (instructions!
Consists of a large numer of cells, each indi"iduall& addressale)
Cell is called *&te+ and consists of , its (inar& elements holding
- or .!
Usuall& a word consists of / &tes)
#n most cases "olatile memor&
o $he %ultile"el Cache 0 An intermediate stage etween ultra0fast registers
(inside CPU! and much slower main memor&)
%ost acti"el& used information in the main memor& is duplicated
in the cache, which is faster, ut of much lesser capacit&)
2.2.System Buses
2.2.1 Memory Bus
$he memor& us is the set of wires that is used to carr& memor& addresses and data to and from
the s&stem 'A%) $he memor& us in most PCs is also shared with the processor us, connecting
the s&stem memor& to the processor and the s&stem chipset) $he memor& us is part of the PC1s
hierarch& of uses, which are high0speed communications channels used within the computer to
transfer information etween its components)
$he memor& us is made up of two parts:
2ata us: carries actual memor& data within the PC
Address us: selects the memor& address that the data will come from or go to on a read or
write
2.2.2 I/ Bus
$he #34 us facilitates communication etween CPU and all the interface units)
#34 us is of two t&pes:
#solated #34
o Separate #34 read3write control lines in addition to memor& read3write control
lines
o Separate (isolated! memor& and #34 address spaces
o 2istinct input and output instructions
%emor&0mapped #34
o A single set of read3write control lines (no distinction etween memor& and #34
transfer!
o %emor& and #34 addresses share the common address space which reduces
memor& address range a"ailale
o 5o specific input or output instruction, as a result the same memor& reference
instructions can e used for #34 transfers
o Considerale flexiilit& in handling #34 operations
2.3 Memory Su!system rganization
2.".1. Memory #ierarchy
%emor& (ierarch& is to otain the highest possile access speed while minimi6ing the total cost
of the memor& s&stem)
2.".2) Memory $ocation% &ddress Map
Address space assignment to each memor& chip) 7xample: 8.9 &tes 'A% and 8.9 &tes '4%)
2.".".'ypes o( Memory
Main Memory
o Consists of 'A% and '4% chips
o (olds instructions and data for the programs in execution
o :olatile
o ;ast access
o Small storage capacit&
$&pical 'A% chip
RAM 1
RAM 2
RAM 3
RAM 4
ROM
0000 - 007F
0080 - 00FF
0100 - 017F
0180 - 01FF
0200 - 03FF
Component
Hexa
address
0 0 0 x x x x x x x
0 0 1 x x x x x x x
0 1 0 x x x x x x x
0 1 1 x x x x x x x
1 x x x x x x x x x
10 9 8 7 6 5 4 3 2 1
Address bs
C!"p se#e$t 1
C!"p se#e$t 2
Read
%r"te
7-b"t address
C&1
C&2
R'
%R
A' 7
128 x 8
RAM
8-b"t data bs
C!"p se#e$t 1
C!"p se#e$t 2
9-b"t address
C&1
C&2
A' 9
512 x 8
ROM
8-b"t data bs
$&pical '4% chip
&u)iliary Memory
o #nformation organi6ed on magnetic tapes
o Auxiliar& memor& holds programs and data for future use
o 5on0"olatile data remains e"en when the memor& de"ice is taken off0power
o Slower access rates
o <reater storage capacit&
&ssociati*e Memory
o Accessed & the content of the data rather than & an address
o Also called Content Addressale %emor& (CA%!
o Used in "er& high speed searching applications
o %uch faster than 'A% in "irtuall& all search applications
o (igher costs
CA% (ardware 4rgani6ation
Cache Memory
o Cache is a fast small capacit& memor& that should hold those information which
are most likel& to e accessed
Ar(ment re("ster)A*
+e, re("ster )+*
Asso$"at"-e memor,
arra, and #o("$
m .ords
n b"ts per .ord
/npt
Read
%r"te
M
Mat$! Re("ster
o $he propert& of Localit& of 'eference makes the Cache memor& s&stems work
o Localit& of 'eference 0 $he references to memor& at an& gi"en time inter"al tend
to e confined within a locali6ed areas) $his area contains a set of information and
the memership changes graduall& as time goes &)
$emporal Localit& 0 $he information which will e used in near future is
likel& to e in use alread&
Spatial Localit& 0 #f a word is accessed, ad=acent(near! words are likel&
accessed soon
2.4 I/O Subsystem Organization and Interfacing
2.+.1. & Model o( I/ Su!system rganization
Local peripheral
device
Communications
port
File
System
Hardware
Hardware
User Processes
User Processes
Logical
I/O
Communication
Architecture
irectory
!anagement
File System
Physical
Organi"ation
Scheduling # Control
Scheduling # Control
evice I/O
evice I/O
2.+.2. I/ Inter(ace
Pro"ides a method for transferring information etween internal storage (such as memor&
and CPU registers! and external #34 de"ices
'esol"es the differences etween the computer and peripheral de"ices
Peripherals 0 7lectromechanical 2e"ices
CPU or %emor& 0 7lectronic 2e"ice
2ata $ransfer 'ate
o Peripherals 0 Usuall& slower
o CPU or %emor& 0 Usuall& faster than peripherals> Some S&nchroni6ation
mechanism ma& e needed
unit of #nformation
o Peripherals ?&te, ?lock, etc)
o CPU or %emor& @ord
C!"p se#e$t
Re("ster se#e$t
Re("ster se#e$t
/0O read
/0O .r"te
C&
R&1
R&0
R'
%R
1"m"n(
and
Contro#
2s
b33ers
2"d"re$t"ona#
data bs
4ort A
re("ster
4ort 2
re("ster
Contro#
re("ster
&tats
re("ster
/0O data
Contro#
&tats
/
n
t
e
r
n
a
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C45
/0O
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