KANAAD_2007

8051 OPERATIONAL CODE MNEMONICS

DATA TRANSFER INSTRUCTIONS
1 MOV A, #N
Copy immediate data byte 'N' to the register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

2 MOV A, RN
Copy immediate data of register RN to the register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

3 MOV RN, A
Copy immediate data of A register to register RN.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

4 MOV RN, #N
Copy immediate data byte 'N' to register RN.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

5 MOV DPTR, #NN
Copy immediate 16-bit data 'NN' to the DPTR register.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

6 MOV A, ADDRESS
Copy data from direct address ADDRESS to A register.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

7 MOV ADDRESS, A
Copy data from register A to direct address ADDRESS.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

8 MOV RN, ADDRESS
Copy data from direct address ADDRESS to register RN.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

9 MOV ADDRESS, RN
Copy data from register RN to direct address ADDRESS.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.
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10 MOV ADDRESS, #N
Copy immediate byte 'N' to direct address ADDRESS.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

11 MOV ADDRESS1, ADDRESS2
Copy data from direct address ADDRESS2 to direct address ADDRESS1.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

12 MOV @RP, #N
Copy immediate byte 'N' to the address in RP.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

13 MOV @RP, ADDRESS
Copy the contents of ADDRESS to the address in RP.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

14 MOV @RP, A
Copy the data of register A to the address in RP.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

15 MOV ADDRESS, @RP
Copy the contents of address in RP to ADDRESS.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

16 MOV A, @RP
Copy the contents of address in RP to register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

17 MOVX A, @RP
Copy the contents of external address in RP to register A.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

18 MOVX A, @DPTR
Copy the contents of external address specified in DPTR to register A.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.



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19 MOVX @RP, A
Copy the data of register A to the external address in RP.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

20 MOVX @DPTR, A
Copy the data of register A to the external address specified in DPTR.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

21 MOVC A, @A+DPTR
Copy the code byte, found at the ROM address formed by addition of register A &
DPTR to register A.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

22 MOVC A, @A+PC
Copy the code byte, found at the ROM address formed by addition of register A &
PC to register A.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

23 PUSH ADDRESS
Increment SP; copy the data in ADDRESS to the internal RAM address contained in
Stack Pointer.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

24 POP ADDRESS
copy the data from the internal RAM address contained in SP to ADDRESS;
decrement Stack Pointer.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.


25 XCH A, RN
Exchange data bytes between register RN & register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

26 XCH A, ADDRESS
Exchange data bytes between ADDRESS & register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.




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27 XCH A @RP
Exchange data bytes between address in RP & register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

28 XCHD A, @RP
Exchange lower nibble between address in RP & register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

LOGICAL INSTRUCTIONS
29 RL A
Rotate register A to the left; the MSB becomes LSB.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

30 RLC A
Rotate register A & carry bit to the left; the MSB becomes the carry & the carry
becomes LSB.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

31 RR A
Rotate register A to the right; the LSB becomes MSB.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

32 RRC A
Rotate register A & carry bit to the left; the LSB becomes the carry & the carry
becomes MSB.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

33 SWAP A
Exchange the low & high nibbles of register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

34 ANL A, #N
AND each bit of register A with the same bit of immediate number 'N'; put result in
register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Immediate Addressing.





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35 ANL A, ADDRESS
AND each bit of register A with the same bit of direct RAM ADDRESS; put result in
register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

36 ANL A, RN
AND each bit of register A with the same bit of register RN; put result in A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

37 ANL A, @RP
AND each bit of register A with the same bit of the contents of the RAM address
contained in register RP; put result in register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

38 ANL ADDRESS, A
AND each bit of register A with the same bit of direct RAM ADDRESS; put result in
direct RAM ADDRESS.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

39 ANL ADDRESS, #N
AND each bit of direct RAM ADDRESS with the same bit of immediate number 'N';
put result in direct RAM ADDRESS.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

40 ORL A, #N
OR each bit of register A with the same bit of immediate number 'N'; put result in
register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

41 ORL A, ADDRESS
OR each bit of register A with the same bit of direct RAM ADDRESS; put result in
register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

42 ORL A, RN
OR each bit of register A with the same bit of register RN; put result in register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.


43 ORL A, @RP
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OR each bit of register A with the same bit of the contents of the RAM address
contained in register RP; put result in register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

44 ORL ADDRESS, A
OR each bit of register A with the same bit of direct RAM ADDRESS; put result in
direct RAM ADDRESS.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

45 ORL ADDRESS, #N
OR each bit of direct RAM ADDRESS with the same bit of immediate number 'N';
put result in direct RAM ADDRESS.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

46 XRL A, #N
XOR each bit of register A with the same bit of immediate number 'N'; put result in
register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

47 XRL A, ADDRESS
XOR each bit of register A with the same bit of direct RAM ADDRESS; put result in
register A.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

48 XRL A, RN
XOR each bit of register A with the same bit of register RN; put result in A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

49 XRL A, @RP
XOR each bit of register A with the same bit of the contents of the RAM address
contained in register RP; put result in register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

50 XRL ADDRESS, A
XOR each bit of register A with the same bit of direct RAM ADDRESS; put result in
direct RAM ADDRESS.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

51 XRL ADDRESS, #N
XOR each bit of direct RAM ADDRESS with the same bit of immediate number 'N';
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put result in direct RAM ADDRESS.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

52 CLR A
Clear register A; set each bit of register to 0.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

53 CPL A
Compliment each bit of register A; every 1-state bit becomes a 0 state & each 0-
state bit becomes a 1 state.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

54 ANL C, BIT
AND carry & the addressed bit; put result in carry.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

55 ANL C, /BIT
AND carry & the complement of addressed BIT; put result in carry; addressed BIT is
not altered.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

56 ORL C, BIT
OR carry & the addressed BIT; put result in carry.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

57 ORL C, /BIT
OR carry & the complement of addressed BIT; put result in carry; addressed BIT is
not altered.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

58 CPL C
Compliment the carry.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.




59 CPL BIT
Compliment the addressed BIT.
This is a 1-byte instruction requiring 1 machine cycle.
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No flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

60 CLR C
Clear the carry.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

61 CLR BIT
Clear the addressed BIT.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

62 MOV C, BIT
Copy the addressed BIT to carry.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

63 MOV BIT, C
Copy the carry to the addressed BIT.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

64 SETB C
Set the carry flag to 1.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

65 SETB BIT
Set the addressed BIT to 1.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Bit Addressing.

66 INC A
Add a 1 to register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

67 INC RN
Add a 1 to register RN.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.


68 INC ADDRESS
Add a 1 to contents of the direct memory address ADDRESS.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
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Addressing Mode: - Direct Addressing.

69 INC @RP
Add a 1 to contents of the direct memory address in RP.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

70 INC DPTR
Add a 1 to DPTR.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

71 DEC A
Subtract a 1 from register A.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

72 DEC RN
Subtract a 1 from register RN.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Implicit Addressing.

73 DEC ADDRESS
Subtract a 1 from contents of the direct memory address ADDRESS.
This is a 2-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

74 DEC @RP
Subtract a 1 from contents of the direct memory address in RP.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

76 ADD A, #N
Add register A with the immediate number 'N'; put sum in register A.
This is a 2-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

77 ADD A, RN
Add register A with the register RN; put sum in register A.
This is a 1-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Register Addressing.


78 ADD A, ADDRESS
Add register A with the contents of ADDRESS; put sum in register A.
This is a 2-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Direct Addressing.
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79 ADD A, @RP
Add register A with the contents of address in register RP; put sum in register A.
This is a 2-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

80 ADDC A, #N
Add register A with the immediate number 'N' & the carry; put sum in register A.
This is a 2 byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Immediate Addressing.

81 ADDC A, RN
Add register A with the register RN & the carry; put sum in register A.
This is a 1-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Register Addressing.

82 ADDC A, ADDRESS
Add register A with the contents of ADDRESS & the carry; put sum in register A.
This is a 2-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Direct Addressing.

83 ADDC A, @RP
Add register A with the contents of address in register RP & the carry; put sum in
register A.
This is a 1-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

84 SUBB A, #N
Subtract the immediate number 'N' & the carry from register A; put result in A.
This is a 2-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Register Addressing.

85 SUBB A, ADDRESS
Subtract the contents of ADDRESS & the carry from register A; put result in A.
This is a 2-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Direct Addressing.

86 SUBB A, RN
Subtract the register RN & the carry from register A; put result in register A.
This is a 1-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Register Addressing.

87 SUBB A, @RP
Subtract the contents of address in register RP & the carry from register A; put
result in register A.
This is a 1-byte instruction requiring 1 machine cycle.
Carry, Overflow & Auxiliary carry flags are affected while executing this instruction.
Addressing Mode: - Indirect Addressing.
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88 MUL AB
Multiply A by B; put the low-order byte of the product in register A; put the higher-
order byte of the product in register B.
This is a 1-byte instruction requiring 4-machine cycle.
Overflow & Zero flags are affected while executing this instruction.
Addressing Mode: - Register Addressing.

89 DA A
Adjust the sum of two packed BCD numbers found in register A; leave the adjusted
number in register A.
This is a 1-byte instruction requiring 1 machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Register Addressing.

90 DIV AB
Divide A by B; put the integer part of the quotient in register A; put the integer part
of the reminder in register B.
This is a 1-byte instruction requiring 4-machine cycle.
Overflow & Zero flags are affected while executing this instruction.
Addressing Mode: - Register Addressing.

91 JC REL
J ump to the relative address if the carry flag is set to 1.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

92 JNC REL
J ump to the relative address if the carry flag is reset to 0.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

93 JB BIT, REL
J ump to the relative address if the addressable bit is set to 1.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

94 JNB BIT, REL
J ump to the relative address if the addressable bit is reset to 0.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.




95 JBC BIT, REL
J ump to the relative address if the addressable bit is set & clear the addressable bit.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

96 CJNE A, ADDRESS, REL
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Compare the contents of register A with the contents of direct address; if they are
not equal, then jump to the relative address else continue with next command.
This is a 3-byte instruction requiring 2-machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

97 CJNE A, #N, REL
Compare the contents of register A with the immediate number; if they are not
equal, then jump to the relative address else continue with next command.
This is a 3-byte instruction requiring 2-machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

98 CJNE RN, #N, REL
Compare the contents of register RN with the immediate number; if they are not
equal, then jump to the relative address else continue with next command.
This is a 3-byte instruction requiring 2-machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

99 CJNE @RP, #N, REL
Compare the contents of address in register RP with the immediate number; if they
are not equal, then jump to the relative address else continue with next command.
This is a 3-byte instruction requiring 2-machine cycle.
Carry flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

100 DJNZ RN, REL
Decrement the register RN by 1 & jump to the relative address if the result is not 0.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

101 DJNZ ADDRESS, REL
Decrement the direct address by 1 & jump to the relative address if the result is not
zero.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

102 JZ REL
J ump to the relative address if register A is 0.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.



103 JNZ REL
J ump to the relative address if register A is not 0.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

104 JMP @A+DPTR
J ump to the address formed by addition of register A & DPTR. The address can be
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anywhere in the program memory.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

105 AJMP SADDRESS
J ump to the absolute short-range address SADDRESS.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

106 LJMP LADDRESS
J ump to the absolute long-range address LADDRESS.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

107 SJMP REL
J ump to the relative address REL.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

108 NOP
Do nothing & go to next instruction.
This is a 1-byte instruction requiring 1 machine cycle.
No flag is affected while executing this instruction.

109 ACALL SADDRESS
Call the subroutine located on the same page as the address of the opcode
immediately following the ACALL instruction; push the address of the instruction
immediately after the call on the stack.
This is a 2-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.

110 LCALL LADDRESS
Call the subroutine located anywhere in the program; push the address of the
instruction immediately after the call on the stack.
This is a 3-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Direct Addressing.





111 RET
Pop 2 bytes from stack into program counter.
This is a 1-byte instruction requiring 2-machine cycle.
No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.

112 RETI
Pop 2 bytes from stack into program counter & reset the interrupt enable flip flop.
This is a 1-byte instruction requiring 2-machine cycle.
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No flag is affected while executing this instruction.
Addressing Mode: - Indirect Addressing.







MNEMONIC ACRONYMS

ADDRESS
Address of the internal RAM from 00h to FFh.

LADDRESS
Long address of 16bits from 0000h to FFFFh.

SADDRESS
Short address of 11bits

REL
Relative address, a signed number from 128d to 127d.

BIT
Addressable bit of the internal RAM or SFR.

RN
Any of the eight registers R0 to R7 in the selected bank.

RP
Either of the pointing registers R0 or R1 in selected bank.

Note
Flags affected by each instruction are shown where appropriate; any operation that
affects PSW may also affect the flags.

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