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APPENDIX A: REFERENCES

[1] K. Roy & S.C. Prasad, Low-power CMOS VLSI circuit design, New York: John Wiley &
Sons, Inc., 2012, pp. 12222.
[2] G.E. Moore, "Cramming More Components onto Integrated Circuits," Proc. IEEE, vol.
86, no. 1, pp. 8285, Jan. 1998.
[3] G.E. Moore, "Progress in digital integrated electronics," Electron Device Meeting, vol.
21, pp. 1113, 1975.
[4] C. Disco & B. Van Der Meulen, Getting new technologies together., New York: Walter
de Gruyter, 1998, pp. 206207.
[5] F.N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans.
Very Large Scale Integration (VLSI) Syst., vol. 2, no. 4, pp. 446455, Dec. 1994.
[6] A. Mukherjee, Introduction to NMOS and CMOS VLSI Systems Design., Englewood
Cliffs: Prentice-Hall, 1986, pp. 27.
[7] S.M. Kang & Y. Leblebic, CMOS digital integrated circuits: Analysis and design. 3rd ed.,
Boston: McGraw-Hill, 2003, pp. 2046.
[8] J. Watling. (2009, Sept.). The impact of interface roughness and self-heating on the
performance of nano-scale MOSFETs [Online]. Available:
http://userweb.eng.gla.ac.uk/
[9] N.H. Weste & D.M. Harris, CMOS VLSI design: A circuits and systems perspective. 4th
ed., Boston: Addison-Wesley, 2011, pp. 2933.
[10] W.W. Lattin, J.A. Bayliss, J.R. Rattner & D.L. Budde, "A methodology for VLSI chip
design," Lambda, vol. 2, pp. 3444, 1981.
[11] C. Kopp. (2010, Dec 31). Assessing the impact of exponential growth laws on future
combat aircraft design. [Online}. Available: http://www.ausairpower.net/
[12] A. Krishnamoorthy. (2004, July 15). Minimize IC power without sacrificing
performance [Online]. Available: http://www.eetimes.com/
[13] D.J. Mlynek & Y. Leblebici. Design of VLSI systems.[Online]. Available:
http://book.huihoo.com/
[14] M. Favalli, L. Benini, Analysis of glitch power dissipation in CMOS ICs, Proc. of the
1995 International symposium on low power design, p. 123-128, April 23-26, 1995,
Dana Point, California, USA
[15] F. DAgostino, D. Quercia, Short-channel effects in MOSFETs. Retrieved June, 2014
Available: www.cs.ucl.as.uk
[16] A. Abdollahi, et al, Leakage current reduction in CMOS VLSI circuits by input vector
control, IEEE Transactions on VLSI Systems, vol. 12, no. 2, pp. 140-154, Feb. 2004
[17] F. Poppen. Low power design guide [Online]. Available: http://www.informatik.uni-
oldenburg.de/
[18] D. Conflitti, Low power VLSI design, M.S. thesis, Dept. of Elect and Comp Engr.,
Univ. of Windsor, Windsor, Ontario, Canada, 2001.
[19] J. M. Rabaey, Low power design essentials. New York, NY. Springer 2009
[20] S. Wilton, S. Ang, W. Luk, The impact of pipelining on energy per operation in field-
programmable gate arrays, Lecture Notes in Computer Science. Vol. 3203, pp 719-
728, 2004
[21] R. Uma, et al., Area, delay and power comparison of adder topologies, Int. Journal
of VLSI Design & Comm. Systems (VLSICS) Vol.3, No.1, February 2012
[22] G. K. Yeap, Half-swing clocking scheme for 75% power saving in clocking circuitry
IEEE Journal of Solid State Circuits. Vol. 30, No. 4, April 1995

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