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LCD TV

SERVICE MANUAL
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
CHASSIS : LJ91L
MODEL : 42SL90QD
42SL90QD-SA
North/Latin America http://aic.lgservice.com
Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
Internal Use Only
Printed in Korea P/NO : MFL61862416 (0911-REV01)
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 2 -
CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ..................................................................................3
SPECIFICATION........................................................................................6
ADJUSTMENT INSTRUCTION ...............................................................10
EXPLODED VIEW .................................................................................. 17
SVC. SHEET ...............................................................................................
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 3 -
SAFETY PRECAUTIONS
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by acci dental shorts of the ci rcui try that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1W), keep the resistor 10mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1M and 5.2M.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
1.5 Kohm/10W
To Instruments
exposed
METALLIC PARTS
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
AC Volt-meter
When 25A is impressed between Earth and 2nd Ground
for 1 second, Resistance must be less than 0.1
*Base on Adjustment standard
IMPORTANT SAFETY NOTICE
0.15uF

LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 4 -
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions on
page 3 of this publication, always follow the safety precautions.
Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board
module or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug or
other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an
explosion hazard.
2. Test high voltage only by measuring it with an appropriate high
voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10% (by volume) Acetone and 90% (by
volume) isopropyl alcohol (90%-99% strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test fixtures specified in this
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily
by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors and
semiconductor "chip" components. The following techniques
should be used to help reduce the incidence of component
damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground.
Al ternati vel y, obtai n and wear a commerci al l y avai l abl e
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the
unit under test.
2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or
exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.
4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
electrical charges sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads
electrically shorted together by conductive foam, aluminum foil
or comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.
8. Mi ni mi ze bodi l y mot i ons when handl i ng unpackaged
replacement ES devices. (Otherwise harmless motion such as
the brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity
sufficient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500F to 600F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
bristle (0.5 inch, or 1.25cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500F to 600F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-
type solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500F to 600F)
b. First, hold the soldering iron tip and solder the strand against
the component lead until the solder melts.
c. Quickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
onl y unti l the sol der fl ows onto and around both the
component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.
SERVICING PRECAUTIONS
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 5 -
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the
circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by gently
prying up on the lead with the soldering iron tip as the solder
melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the
IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close as
possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
si de of t he ci rcui t board. (Use t hi s t echni que onl y on I C
connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly
connected to the affected copper pattern.
3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 6 -
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
4. Electrical specification
4.1 General Specification
1. Application range
This specification is applied to the LCD TV used LJ91L
chassis.
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature : 255C (779F), CST : 405C
2) Relative Humidity : 6510%
3) Power Voltage : Standard input voltage(100~240V@50/60Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawi ng and speci f i cat i on by part number i n
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety: CE, IEC specification
- EMC: CE, IEC specification
No Item Specification Remark
1. Receiving System 1) SBTVD / NTSC / PAL-M / PAL-N
2. Available Channel 1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135




3. Input Voltage 1) AC 100 ~ 240V 50/60Hz Mark : 110V, 60Hz
4. Market Cent
42 inch Wide(1920x1080)
47 inch Wide(1920x1080)
LC420WUL-SBT1
LC470WUL-SBT1
42SL90QD-SA
47SL90QD-SA
42SL90QD-SA
47SL90QD-SA
ral and South AMERICA
5. Screen Size
6. Aspect Ratio 16:9
7. Tuning System FS
8. Module

9. Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %

10. Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %


- 7 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
5. Chromiance & Luminance spec.
No Item Min Typ Max Unit Remark
Module cd/m
2
White brightness 294 368
2.
1.
3.
Luminance uniformity 77 % Full white
0.640
0.331 4.
5.
RED

0.282
0.634

6.
7.
GREEN

0.151
8.
9.
BLUE

0.279
10.
Color
coordinate
WHITE
Y
X
Y
X
Y
X
Y
X
Typ.
-0.03
0.292
Typ.
+0.03



11.
12.
Color coordinate uniformity N/A
900 1300 Contrast ratio
Cool
-0.015
Typ. 0.269
0.273
Typ.
+0.015

Standard
-0.015
Typ.
Typ.
0.285
0.293
Typ.
+0.015

13. Color
Temperature
Warm
-0.015
0.313
0.329
Typ.
+0.015

<Test Condition>
85% Full white pattern
** The W/B Tolerance is
0.015 for Adjustment
Dynamic contrast : off
Dynamic color : off
OPC : off
14. Color Distortion, DG 10.0 %
15. Color Distortion, DP 10.0 deg
16. Color S/N, AM/FM 43.0 dB
17. Color Killer Sensitivity -80 dBm
6. Component Input (Y, CB/PB, CR/PR)
No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed
1. 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2. 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3. 720*480 31.47 60 27.027 SDTV 480P
4. 720*480 31.47 59.94 27.0 SDTV 480P
5. 1280*720 45.00 60.00 74.25 HDTV 720P
6. 1280*720 44.96 59.94 74.176 HDTV 720P
7. 1920*1080 33.75 60.00 74.25 HDTV 1080I
8. 1920*1080 33.72 59.94 74.176 HDTV 1080I
9. 1920*1080 67.500 60 148.50 HDTV 1080P
10. 1920*1080 67.432 59.939 148.352 HDTV 1080P
11. 1920*1080 27.000 24.000 74.25 HDTV 1080P
12. 1920*1080 26.97 23.94 74.176 HDTV 1080P
13. 1920*1080 33.75 30.000 74.25 HDTV 1080P
14. 1920*1080 33.71 29.97 74.176 HDTV 1080P
15. 1920*1080 56.25 50.000 148.5 HDTV 1080P
16. 1920*1080 28.125 25.000 74.25 HDTV 1080P
- 8 -
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Only for training and service purposes
7. RGB Input (PC)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
PC DDC
1. 640*350 31.468 70.09 25.17 EGA X
O
O
O
O
O
O
O
O
O
O
2. 720*400 31.469 70.08 28.32 DOS
3. 640*480 31.469 59.94 25.17 VESA(VGA)
4. 800*600 35.156 56.25 36.00 VESA(SVGA)
5. 800*600 37.879 60.31 40.00 VESA(SVGA)
6. 1024*768 48.363 60.00 65.00 VESA(XGA)
7. 1280*768 47.776 59.870 79.5 CVT(WXGA)
8. 1360*768 47.712 60.015 85.50 VESA (WXGA)
9. 1280*1024 63.981 60.020 108.00 VESA
10. 1600*1200 75.00 60.00 162 VESA (UXGA)
11 1920*1080 67.5 60 148.5 HDTV 1080P
** RGB PC Monitor Range Limits
- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz
8. HDMI Input (PC/DTV)
No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed
PC DDC
1 640*350 31.468 70.09 25.17 EGA X
O
O
O
O
O
O
O
O
O
O
2 720*400 31.469 70.08 28.32 DOS
3 640*480 31.469 59.94 25.17 VESA(VGA)
4 800*600 35.156 56.25 36.00 VESA(SVGA)
5 800*600 37.879 60.31 40.00 VESA(SVGA)
6 1024*768 48.363 60.00 65.00 VESA(XGA)
7 1280*768 47.776 59.870 79.5 CVT(WXGA)
8 1360*768 47.712 60.015 85.50 VESA (WXGA)
9 1280*1024 63.981 60.020 108.00 VESA (SXGA)
10 1600*1200 75.00 60.00 162 VESA (UXGA)
11 1920*1080 66.587 59.934 138.5 HDTV 1080P
DTV
1 720*480 31.47 60 27.027 SDTV 480P
2 720*480 31.47 59.94 27.00 SDTV 480P
3 1280*720 45.00 60.00 74.25 HDTV 720P
4 1280*720 44.96 59.94 74.176 HDTV 720P
5 1920*1080 33.75 60.00 74.25 HDTV 1080I
6 1920*1080 33.72 59.94 74.176 HDTV 1080I
7 1920*1080 67.500 60 148.50 HDTV 1080P
8 1920*1080 67.432 59.939 148.352 HDTV 1080P
9 1920*1080 27.000 24.000 74.25 HDTV 1080P
10 1920*1080 26.97 23.94 74.176 HDTV 1080P
11 1920*1080 33.75 30.000 74.25 HDTV 1080P
12 1920*1080 33.71 29.97 74.176 HDTV 1080P
17. 1920*1080 56.25 50.000 148.5 HDTV 1080P
18. 1920*1080 28.125 25.000 74.25 HDTV 1080P
** HDMI Monitor Range Limits
- Min Vertical Freq - 56 Hz
- Max Vertical Freq - 62 Hz
- Min Horiz. Freq - 30 kHz
- Max Horiz. Freq - 80 kHz
- Pixel Clock - 170 MHz
- 9 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
9. Consignment Setting (OUTGOING CONDITION)
No Item Condition
1. Input Mode TV02CH
2. Volume Level 10
3. Mute Off
4. Aspect Ratio 16:9
5. System Color PAL-M
6 Booster On
Picture Mode Vivid
Backlight
Contrast
Brightness
Sharpness
Color 70
70
0
0
100
100
50

Tint
Color Temperature Cool
7. Picture
Picture Reset
Sound Mode Standard
Auto Volume Off
Clear Voice Off
SRS TruSurround XT Off
Balance
8. Audio
TV Speaker On
On
Clock Auto 9. Time
Off Timer / On Timer
Sleep Timer / Auto Sleep
Off
Language (Menu/Audio) Portugues
SimpLink
Key Lock Off
Off
Caption
10. Option
Set ID 1
11. Channel Memory RF : 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 30, 51, 63
CATV : 15, 16, 17
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 10 -
ADJUSTMENT INSTRUCTION
1. Application Range
This specification sheet is applied all of the LJ91T LCD TV
models, which produced in manufacture department or similar
LG TV factory.
2. Notice
1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
2) Adjustment must be done in the correct order. But it is
flexible when its factory local problem occurs. .
3) The adjustment must be performed in the circumstance of
25 5C of temperature and 6510% of relative humidity if
there is no specific designation.
4) The input voltage of the receiver must keep 100~220V,
50/60Hz.
5) Before adjustment, execute Heat-Run for 5 minutes.
After Receive 100% Full white pattern (06CH) then process
Heat-run
(or 8. Test pattern condition of Ez-Adjust status)
How to make set white pattern
1) Press Power ON button of Service Remocon
2) Press ADJ button of Service remocon. Select 8. Test
pattern and, after select White using navigation button,
and then you can see 100% Full White pattern.
* In this status you can maintain Heat-Run useless any
pattern generator
* Noti ce: i f you mai ntai n one pi cture over 20 mi nutes
(Especially sharp distinction black with white pattern
13Ch, or Cross hatch pattern 09Ch) then it can appear
image stick near black level.
3. Adjustment Items
3.1 PCB Assembly adjustment
CPLD DOWNLOAD
Adjust 480i Comp1
Adjust 1080p Comp1/RGB
- If it is necessary, it can adjustment at Manufacture Line
- You can see set adj ustment status at 1. ADJUST
CHECK of the In-start menu
3.2 Set Assembly Adjustment
EDID (The Extended Display Identification Data ) / DDC
(Display Data Channel) download
Color Temperature (White Balance) Adjustment
Make sure RS-232C control
Selection Factory output option
4. PCB Assembly Adjustment
4.1. CPLD DOWNLOAD : JTAG MODE
4.2. << PRINT PORT >> PIN MAP
Pin JTAG Mode Signal Name
2 TCK
3 TMS
8 TDI
11 TDO
13 -
15 VCC
18 TO 25 GND
- 11 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
4.3. << 10P WAFER >> PIN MAP
- 12 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
4.4. Using RS-232C
Adjust 3 items at 3.1 PCB assembly adjustments 4.1.3
sequence one after the order.
O Adjustment protocol
See ADC Adjustment RS232C Protocol_Ver1.0
O Adjustment protocol
- Pattern Generator : (MSPG-925FA)
- Adjust 480i Comp1 (MSPG-925FA : model :209 , pattern
: 65)
- Adjust 1080p Comp1/RGB(MSPG-925FA:model : 225 ,
pattern : 65)
- Adjust RGB (MSPG-925FA:model :225 , Pattern :65)
RGB-PC Mode
* If you want more information then see the below Adjustment
method (Factory Adjustment)
O Adjustment sequence
- ad 00 00 : Enter the ADC Adjustment mode.
- xb 00 40: Change the mode to Component1 (No actions)
- ad 00 10: Adjust 480i Comp
- ad 00 10: Adjust 1080p Comp
- xb 00 60: Change to RGB-PC mode(No action)
- ad 00 10: Adjust 1080p RGB
- ad 00 90: End of the adjustment
Order Command Set response
1. Inter the ad 00 00 d 00 OK00x
Adjustment mode
2. Change the kb 00 40 b 00 OK40x (Adjust 480i Comp1/1080p Comp1)
Source kb 00 60 b 00 OK60x (Adjust 1080p RGB)
3.Start Adjustment ad 00 10
4.Return the OKx ( Success condition )
Response NGx ( Failed condition )
5.Read (main) (main : component1 480i, RGB 1080p)
Adjustment data ad 00 20 000000000000000000000000007c007b006dx
(main) (main : component1 1080p)
ad 00 30 000000070000000000000000007c00830077x
6.Confirm ad 00 99 NG 03 00x (Failed condition)
Adjustment NG 03 01x (Failed condition)
NG 03 02x (Failed condition)
OK 03 03x (Success condition)
7. End of Adjustment ad 00 90 d 00 OK90x
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
- 13 -
5. Factory Adjustment
5.1 Manual Adjust Component 480i/1080p
RGB 1080p
O Summary : Adjustment component 480i/1080i and RGB
1080p is Gain and Black levelsetting at Analog
to Digital converter, and compensate the RGB
deviation
O Using instrument
- Adjustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator (It can output 480i/1080i
horizontal 100% color bar pattern signal, and its output
level must setting 0.7V0.1V p-p correctly)
<Pic.4 Adjustment pattern : 480i / 1080p 60Hz Pattern >
* You must make it sure its resolution and pattern cause every
instrument can have different setting
O Adj ust ment met hod 480i Comp1, Adj ust 1080p
Comp1/RGB (Factory adjustment)
ADC 480i Component1 adjustment
- Check connection of Component1
- MSPG-925FA Model: 209, Pattern 65
Set Component 480i mode and 100% Horizontal Color
Bar Pat t ern(HozTV31Bar), t hen set TV set t o
Component1 mode and its screen to NORMAL
ADC 1080p Component1 / RGB adjustment
- Check connection both of Component1 and RGB
- MSPG-925FA Model: 225, Pattern 65
Set Component 1080p mode and 100% Horizontal Color
Bar Pat t ern(HozTV31Bar), t hen set TV set t o
Component1 mode and its screen to NORMAL
After get each the signal, wait more a second and enter
the IN-START with press IN-START key of Service
remocon. After then select 7. External ADC with
navigator button and press Enter.
After Then Press key of Servi ce remocon Ri ght
Arrow(VOL+)
You can see ADC Component1 Success
Component 1 1080p, RGB 1080p Adj ust i s same
method.
Component 1080p Adjustment in Component1 input
mode
RGB 1080p adjustment in RGB input mode
If you success RGB 1080p Adjust. You can see ADC
RGB-DTV Success
5.2 EDID (The Extended Display
Identification Data) / DDC (Display Data
Channel) Download.
O Summary
It is established in VESA, for communication between
PC and Monitor without order from user for building user
condition. It helps to make easily use realize Plug and
Play function.
For EDID data write, we use DDC2B protocol.
O Auto Download
After enter Service Mode by pushing ADJ key,
Enter EDID D/L mode.
Enter START by pushing OK key.
Caution: - Never connect HDMI & D-sub Cable when the user
downloading .
- Use the proper cables below for EDID Writing.







- 14 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
O Manual Download
Write HDMI EDID data
- Using instruments
=> Jig. (PC Serial to D-Sub connection) for PC, DDC
adjustment.
=> S/W for DDC recording (EDID data write and
read)
=> D-sub jack
=> Additional HDMI cable connection Jig.
- Preparing and setting.
=> Set instruments and Jig. Like pic.5), then turn on
PC and Jig.
=> Operate DDC write S/W (EDID write & read)
=> It will operate in the DOS mode.
Pic.3) For write EDID data, setting Jig and another instruments.
EDID data for LJ91D Chassis (Model name = LG TV)
- HDMI-1 EDID table (0x3D, 0x2C)
- HDM2 EDID table (0x3D, 0x1C)
- HDMI-3 EDID table (0x3D, 0x0C)
- Analog (RGB) EDID table (0x9B, 0x25)
See Workig Guide of you want more information about EDID
communication.
PC
VSC
B/D
Edid data and Model option download (RS232)
NO Item CMD 1 CMD 2 Data 0
Enter
download MODE
Download
Mode In
A E 0 0
When transfer the Mode In ,
Carry the command.
Edid data and
Model option
download
Download
A E *Note1 *Note2
Automatically download
(The use of a internal Data)
Adjust Mode Out
A E 9 0

Adjustment
Confirmation
A E 9 9
To check Download
on Assembly line.
5.3 Adjustment Color Temperature
(White balance)
O Using Instruments
Color Analyzer: CA-210 (CH 9)
- Using LCD color temperature, Color Analyzer (CA-210)
must use CH 9, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.
Aut o-adj ust ment Equi pment (I t needs when Aut o-
adjustment It is availed communicate with RS-232C :
Baud rate: 115200)
Vi deo Si gnal Generator MSPG-925F 720p, 216Gray
(Model: 217, Pattern 78)
O Connection Diagram (Auto Adjustment)
Using Inner Pattern
Using HDMI input
<Pic.5 Connection Diagram for Adjustment White balance> .
O White Balance Adjustment
If you cant adjust with inner pattern, then you can adjust
it using HDMI pattern. You can select option at "Ez-Adjust
Menu 7. White Balance" there items "NONE, INNER,
HDMI". It is normally setting at inner basically. If you cant
adjust using inner pattern you can select HDMI item, and
you can adjust.
In manual Adjust case, if you press ADJ button of service
remocon, and ent er "Ez-Adj ust Menu 7. Whi t e
Balance", then automatically inner pattern operates. (In
case of "Inner" originally "Inner" will be selected.
Connect all cables and equipments like Pic.5)
Set Baud Rate of RS-232C to 115200. It may set
115200 orignally.
Connect RS-232C cable to set
Connect HDMI cable to set
RS-232C Command (Commonly apply)
wb 00 00 White Balance adjustment start.
wb 00 10 Start of adjust gain (Inner white
pattern)
wb 00 1f End of gain adjust
wb 00 20 Start of offset adjust(Inner white
pattern)
wb 00 2f End of offset adjust
wb 00 ff End of White Balance adjust(Inner
pattern disappeared)
"wb 00 00": Start Auto-adjustment of white balance.
"wb 00 10": Start Gain Adjustment (Inner pattern)
"jb 00 c0" :

"wb 00 1f": End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00
2f-end)
"wb 00 ff": End of white balance adjustment (inner
pattern disappear)
- 15 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
CA -100+
COL OR
A NA L Y Z ER
T Y PE; CA -100+
Ful l W hi t e Pat t er n
RS-232C


- 16 -
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
O White Balance Adjustment (Manual adjustment)
Test Equipment: CA-210
- Using LCD color temperature, Color Analyzer (CA-
210) must use CH 9, which Matrix compensated
(White, Red, Green, Blue compensation) with CS-
2100. See the Coordination bellowed one.
Manual adjustment sequence is like bellowed one.
- Turn to "Ez-Adjust" mode with press ADJ button of
service remocon.
- Select "10.Test Pattern" with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more
10cm from center of LCD module when adjustment.
- Press "ADJ" button of service remocon and select
"7.White-Balance" in "Ez-Adjust" then press " "
button of navigation key.
(When press " " button then set will go to full white
mode)
- Adjust at three mode (Cool, Medium, Warm)
- If "cool" mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then
control R, G gain adjustment High Light adjustment.
- If "Medium" and "Warm" mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.
- All of the three mode
Let R-Gain to 192 and R, G, B-Cut to 64 and then
control G, B gain adjustment High Light adjustment.
- With volume button (+/-) you can adjust.
- After all adjustment finished, with Enter ( key) turn
to Ez-Adjust mode. Then with ADJ button, exit from
adjustment mode
Attachment: White Balance adjustment coordination and color
temperature.
O Using CS-1000 Equipment.
- COOL : T=11000K, uv=0.000, x=0.276 y=0.283
- MEDIUM : T=9300K, uv=0.000, x=0.285 y=0.293
- WARM : T=6500K, uv=0.000, x=0.313 y=0.329
5.4 EYE-Q Function check.
1) Turn on TV
2) Press EYE Key of Adj R/C
3) Cover the Eye Q II sensor on the front of the using your
hand and wait for 6 seconds
4) Confirm that R/G/B va;ie os ;pwer tjam 10 of the Raw
Data (Sensor data, Back light). If after 6 seconds, R/G/B
value is not lower than 10, re[;ace EYE Q II sensor.
5) Remove your hand from the EYE Q II sensor and wait for
6 sencond
6) Confirm that OK pop up.
If change is not seen, replace EYE Q II sensor
5.5 Test of RS-232C control
Press IN-Start button of service remocon then set the 4.Baud
rate to 15200, Then check RS-232C control and
5.6 Selection of Country option.
Selection of country option is allowed only North American model
(Not allowed Korean model). It is selection of Country about
Rating and Time Zone.
Models: All models which use LA75A Chassis (See the first
page.)
Press In-Start button of Service Remocon, then enter the
Option Menu with PIP CH- Button
Select one of these three (USA, CANADA, MEXICO)
defends on its market using Vol. +/-button.
* Caution : Dont push The Instop Key ater completing the
function inspection.
5.7 Check the Ginga(Data Broadcasting)
1) Turn on TV
2) Press the OK Button on the ADJ R/C
3) Check the Ginga icon
LGE Internal Use Only Copyright LG Electronics. Inc. All right reserved.
Only for training and service purposes
-17 -
3
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EXPLODED VIEW
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
IMPORTANT SAFETY NOTICE
A
2
L
V
1
A
1
0
L
V
2
F
i
b
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O
p
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THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009. 03. 23
IN - OUT
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2
3
4
5
6
7
8
9
10
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8
6
7
5
4
P1101
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2
3
4
5
6
7
8
9
R1150
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9
10
8
7
6
5
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11
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10
8
7
6
5
4
11
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R1172
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R1173
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3 E_SPRING
1 15
LEE GI YOUNG
RS-232C
BCM RECOMMAND
R,G,B PC&DDC
BCM Reference
PC AUDIO
SPDIF OPTIC JACK
COMPONENT1
COMPONENT2
AV1
SIDE AV
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
HDMI
BCM (BRAZIL VENUS)
5V_HDMI_2
+1.8V_HDMI
R674
OPT
4.7K
+1.8V_AMP
D2-_HDMI2
5V_HDMI_2
HPD1
R676
12K
CK+_HDMI1
D2+_HDMI2
CK+_HDMI1
Y12
C624
0.1uF
R657
47K
+3.3V_HDMI
H
D
M
I
0
_
R
X
1
+
_
B
C
M
1
1
:
W
1
6
D2+_HDMI4
AE19
HPD4
AH19
C625
0.1uF
5V_HDMI_1
R
6
7
0
0
H
D
M
I
0
_
R
X
2
+
_
B
C
M
1
1
:
W
1
6
GND
R641
0
CK+_HDMI2
CEC_REMOTE
C605
0.1uF
C612
0.1uF
DDC_SDA_2
HPD2
C
6
1
1
0
.
1
u
F
5V_HDMI_2
P19;AJ15
C604
0.1uF
H
D
M
I
0
_
R
X
C
-
_
B
C
M
1
1
:
W
1
7
DDC_SCL_4
R13;AG19
R672
OPT 4.7K
CK-_HDMI1
Y12
R666
68K
H
D
M
I
0
_
R
X
2
-
_
B
C
M
1
1
:
W
1
6
R607 0
C621
0.1uF
D
D
C
_
S
C
L
_
4
D0+_HDMI1
DDC_SCL_2
R17;AL12
DDC_SDA_2
R18;AL12
C
6
1
0
0
.
1
u
F
+1.8V_HDMI
DDC_SCL_1
C606
0.1uF
R627
0
C
K
-
_
H
D
M
I
4
D1-_HDMI2
AL13
C616
0.1uF
D1-_HDMI2
D
2
+
_
H
D
M
I
4
D0-_HDMI2
C628
0.1uF
5V_HDMI_1
L19;Z14
C623
0.1uF
+3.3V_HDMI
C626
0.1uF
D1+_HDMI4
AF19
R661
1.8K
R653
47K
D0+_HDMI4
AF19
R618 0
L601
BLM18PG121SN1D
HPD1
Y13
V
R
6
0
7
A
V
R
L
1
6
1
A
1
R
1
N
T
DDC_SCL_2
R616 0
GND
D
2
-
_
H
D
M
I
4
+1.8V_HDMI
CK-_HDMI1
D
0
-
_
H
D
M
I
4
CK+_HDMI2
AL12
DDC_SDA_1
C
6
1
5
0
.
1
u
F
CK+_HDMI4
AG19
IC601
TDA9996HL
1 VSS_1
2 OUT_C+
3 OUT_C-
4 VDDO[3V3]
5 OUT_DDC_CLK
6 OUT_DDC_DAT
7 VSS_2
8 VDDC[1V8]_1
9 RXA_HPD
10 RXA_5V
11 RXA_DDC_DAT
12 RXA_DDC_CLK
13 RXA_C-
14 RXA_C+
15 VDDH[3V3]_1
16 RXA_D0-
17 RXA_D0+
18 VSS_3
19 RXA_D1-
20 RXA_D1+
21 VDDH[3V3]_2
22 RXA_D2-
23 RXA_D2+
24 VDDH[1V8]_1
25 NC
2
6
V
S
S
_
4
2
7
T
E
S
T
2
8
R
X
B
_
H
P
D
2
9
R
X
B
_
5
V
3
0
R
X
B
_
D
D
C
_
D
A
T
3
1
R
X
B
_
D
D
C
_
C
L
K
3
2
R
X
B
_
C
-
3
3
R
X
B
_
C
+
3
4
V
D
D
H
[
3
V
3
]
_
3
3
5
R
X
B
_
D
0
-
3
6
R
X
B
_
D
0
+
3
7
V
S
S
_
5
3
8
R
X
B
_
D
1
-
3
9
R
X
B
_
D
1
+
4
0
V
D
D
H
[
3
V
3
]
_
4
4
1
R
X
B
_
D
2
-
4
2
R
X
B
_
D
2
+
4
3
V
S
S
_
6
4
4
C
D
E
C
_
D
D
C
4
5
V
D
D
C
[
1
V
8
]
_
2
4
6
V
D
D
C
[
3
V
3
]
4
7
M
O
D
E
4
8
P
D
4
9
S
D
A
/
S
E
L
1
5
0
S
C
L
/
S
E
L
0
51 XTAL_IN
52 XTAL_OUT
53 INT/HP_CTRL
54 CDEC_STBY
55 VDDS[3V3]
56 VSS_7
57 CEC
58 RXC_HPD
59 RXC_5V
60 RXC_DDCC_DAT
61 RXC_DDC_CLK
62 RXC_C-
63 RXC_C+
64 VDDH[3V3]_5
65 RXC_D0-
66 RXC_D0+
67 VSS_8
68 RXC_D1-
69 RXC_D1+
70 VDDH[3V3]_6
71 RXC_D2-
72 RXC_D2+
73 VSS_9
74 R12K
75 VDDH[1V8]_2
7
6
R
X
D
_
H
P
D
7
7
R
X
D
_
5
V
7
8
R
X
D
_
D
D
C
_
D
A
T
7
9
R
X
D
_
D
D
C
_
C
L
K
8
0
R
X
D
_
D
C
-
8
1
R
X
D
_
D
C
+
8
2
V
D
D
H
[
3
V
3
]
_
7
8
3
R
X
D
_
D
0
-
8
4
R
X
D
_
D
0
+
8
5
V
S
S
_
1
0
8
6
R
X
D
_
D
1
-
8
7
R
X
D
_
D
1
+
8
8
V
D
D
H
[
3
V
3
]
_
8
8
9
R
X
D
_
D
2
-
9
0
R
X
D
_
D
2
+
9
1
V
D
D
C
[
1
V
8
]
_
3
9
2
V
S
S
_
1
1
9
3
O
U
T
_
D
2
+
9
4
O
U
T
_
D
2
-
9
5
V
D
D
O
[
1
V
8
]
9
6
O
U
T
_
D
1
+
9
7
O
U
T
_
D
1
-
9
8
V
S
S
_
1
2
9
9
O
U
T
_
D
0
+
1
0
0
O
U
T
_
D
0
-
S
C
L
1
_
3
.
3
V
5
:
G
5
;
1
6
:
G
1
4
R655
47K
D
1
-
_
H
D
M
I
4
C
6
1
4
0
.
1
u
F
5V_HDMI_4
D
D
C
_
S
D
A
_
4
DDC_SDA_1
M18;X13
R662
1.8K
H
D
M
I
0
_
R
X
C
+
_
B
C
M
1
1
:
W
1
7
C607
0.1uF
R639 0
GND
D2-_HDMI2
AL14
R673
OPT
4.7K
D0+_HDMI2
CK-_HDMI4
AG19
D1+_HDMI1
Y11
D0+_HDMI2
AL13
D1+_HDMI2
AL13
D1+_HDMI1
D1-_HDMI1
5V_HDMI_4
5V_HDMI_1
DDC_SDA_1
D0+_HDMI1
Y11
R663
0
C
6
1
9
0
.
1
u
F
C622
0.1uF
DDC_SCL_2
D0-_HDMI4
AF19
D2+_HDMI1
+3.3V_ST
R617 0
+5.0V
R642 0
R678 0
OPT
D2+_HDMI1
Y10
H
D
M
I
0
_
R
X
0
+
_
B
C
M
1
1
:
W
1
7
C
6
1
3
0
.
1
u
F
R665
0
R669
0
C617
0.1uF
D3.3V
H
D
M
I
_
S
C
L
R628
0
R606 0
DDC_SDA_2
D
1
+
_
H
D
M
I
4
D1-_HDMI1
Y11
D
0
+
_
H
D
M
I
4
5V_HDMI_4
Q16;AH18
DDC_SDA_4
R14;AG19
R
6
6
7
9
.
1
K
R605 0
L602
BLM18PG121SN1D
CEC_REMOTE
H8;H17;R26;AL11
R656
47K
D2-_HDMI1
Y10
CEC_REMOTE
H17;R26;W27;AL11
CK-_HDMI2
AL12
S
D
A
1
_
3
.
3
V
5
:
G
5
;
1
6
:
G
1
4
C629
0.1uF
R677
0
HDMI_CEC
12:F6
+5.0V
CEC_REMOTE
H8;R26;W27;AL11
D
6
0
1
M
M
B
D
3
0
1
L
T
1
G
DDC_SCL_4
DDC_SDA_4
C
6
0
9
0
.
1
u
F
R634
47K
R658
0
R643 0
D2-_HDMI1
GND
C620
0.1uF
C608
0.1uF
C627
0.1uF
H
D
M
I
0
_
R
X
0
-
_
B
C
M
1
1
:
W
1
7
H
D
M
I
0
_
R
X
1
-
_
B
C
M
1
1
:
W
1
6
D0-_HDMI2
AL13
R
6
6
8
0
D0-_HDMI1
D1-_HDMI4
AF19
DDC_SCL_1
M17;X12
D2+_HDMI2
AL14
R675
OPT
0
CK-_HDMI2
CEC_REMOTE
H8;H17;W27;AL11
GND
H
D
M
I
_
S
D
A
HPD2
AL11
D1+_HDMI2
R635
47K
+3.3V_HDMI
R664
0
OPT
H
P
D
4
R
6
7
1
0
Q601
SSM6N15FU
3
DRAIN2
2
GATE1
1
SOURCE1
4
SOURCE2
5
GATE2
6
DRAIN1
C
K
+
_
H
D
M
I
4
DDC_SCL_1
D0-_HDMI1
Y12
D2-_HDMI4
AE19
JK501
YKF45-7058V
14
13
5
20
20
12
11
2
19
18
10
4
1
17
9
8
3
16
7
6
15
JK503
KJA-ET-0-0032
14
NC
13
CEC
5
DATA1_SHIELD
20
JACK_GND
12
CLK-
11
CLK_SHIELD
2
DATA2_SHIELD
19
HPD
18
+5V_POWER
10
CLK+
4
DATA1+
1
DATA2+
17
DDC/CEC_GND
9
DATA0-
8
DATA0_SHIELD
3
DATA2-
16
SDA
7
DATA0+
6
DATA1-
15
SCL
C618
5.6nF
JK500
YKF45-7058V
14
13
5
20
20
12
11
2
19
18
10
4
1
17
9
8
3
16
7
6
15
2 15
LEE GI YOUNG
Net Labels changed for HDMI2
SIDE_HDMI_PORT4
UI_HW_PORT1
in case HDMI Switch doesnt support ESD protection
UI_HW_PORT2
HDMI S/W For MSTAR Platform
* HDMI CEC
VARISTORS(VR500/501/502/503/504/505/506/507) on lines-HPD1/2/3/4 are all options
EDID Pull-up
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
AUDIO
BCM (BRAZIL VENUS)
C533
1000pF
50V
R505 100
R513
100
L507
120-ohm
L501
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
R525
4.7K R529
3.3
R523
4.7K
C509
33pF
50V
0.1uF
C513
16V
SPK_R- H4
C534
1000pF
50V
0.1uF
C542
50V
AMP_RST 9:G7;9:I3;12:I4
0.01uF
C545
50V
C519
22000pF
50V
R519
5.6
0.1uF
C505
16V
L509
120-ohm
R524
4.7K
C532
1000pF
50V
0.1uF
C528
50V
C517
33pF
50V
OPT
C521
1uF
16V
C501
10uF
10V
SPK_R+ H4
C530
0.1uF
50V
C531
1000pF
50V
+1.8V_AMP
R518
5.6
SPK_L+ H3
AUDIO_M_CLK
9:G6
C503
10uF
6.3V
R526
4.7K
0.1uF
C508
R
5
0
1
0
AMP_MUTE 12:F3
+1.8V_AMP
SCL1_3.3V 9:I4;2:AH5
SDA1_3.3V 9:I4;2:AH5
R511
3.3
SPK_L- H3
R507 100
L510
120-ohm
0.1uF
C541
50V
R508 100
C511
1uF 10V
L508
120-ohm
BCM_I2S_DATA_OUT 11:F7
C507
1000pF
50V
R522
3.3
SPK_R- H3
C523
1uF 16V
BCM_I2S_BIT_CLK 11:F7
R530
3.3
R521
5.6
L502
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
0.01uF
C546
50V
C524
22000pF
50V
C506
1000pF
50V
R503
3.3K
C512
33pF
50V
0.01uF
C547
50V
SPK_L+ H5
R520
5.6
+1.8V_AMP
+24V_AMP
D3.3V
R502
100
BCM_I2S_WORD_CLK 11:F6
C518
1uF
10V
C504
100pF
50V
C525
22000pF
50V
C502
0.1uF
16V
R527
3.3
C514
22000pF
50V
R506 100
0.1uF
C543
50V
C535
0.01uF
50V
R509 100
L503
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
SPK_L- H5
R504
0
+24V_AMP
0.1uF
C522
50V
0.01uF
C526
50V
0.1uF
C540
50V
SPK_R+ H3
R528
3.3
0.1uF
C520
50V
C510
10uF
10V
0.01uF
C544
50V
0.01uF
C515
50V
+24V
L511
MLB-201209-0120P-N2
+24V_AMP
+1.8V_AMP
GND
D3.3V
C551
0.1uF
16V
C549
0.1uF
16V
IC503
AZ1117H-1.8TRE1(EH13A)
2
OUTPUT
3
INPUT
1
ADJ/GND
0.01uF
C527
50V
IC501
NTP-3100L
EAN60664001
1 BST1A
2 VDR1A
3 RESET
4 AD
5 DVSS_1
6 VSS_IO
7 CLK_I
8 VDD_IO
9 DGND_PLL
10 AGND_PLL
11 LFM
12 AVDD_PLL
13 DVDD_PLL
14 TEST0
1
5
D
V
S
S
_
2
1
6
D
V
D
D
1
7
S
D
A
T
A
1
8
W
C
K
1
9
B
C
K
2
0
S
D
A
2
1
S
C
L
2
2
M
O
N
I
T
O
R
_
0
2
3
M
O
N
I
T
O
R
_
1
2
4
M
O
N
I
T
O
R
_
2
2
5
F
A
U
L
T
2
6
V
D
R
2
B
2
7
B
S
T
2
B
2
8
P
G
N
D
2
B
_
1
29 PGND2B_2
30 OUT2B_1
31 OUT2B_2
32 PVDD2B_1
33 PVDD2B_2
34 PVDD2A_1
35 PVDD2A_2
36 OUT2A_1
37 OUT2A_2
38 PGND2A_1
39 PGND2A_2
40 BST2A
41 VDR2A
42 NC
4
3
V
D
R
1
B
4
4
B
S
T
1
B
4
5
P
G
N
D
1
B
_
1
4
6
P
G
N
D
1
B
_
2
4
7
O
U
T
1
B
_
1
4
8
O
U
T
1
B
_
2
4
9
P
V
D
D
1
B
_
1
5
0
P
V
D
D
1
B
_
2
5
1
P
V
D
D
1
A
_
1
5
2
P
V
D
D
1
A
_
2
5
3
O
U
T
1
A
_
1
5
4
O
U
T
1
A
_
2
5
5
P
G
N
D
1
A
_
1
5
6
P
G
N
D
1
A
_
2
P501
WAFER-ANGLE
1
2
3
4
5
C553
330uF
35V
C529
330uF
C552
10uF
10V
C548
10uF
10V
D501
100V
1N4148W
OPT
D502
100V
1N4148W
OPT
D503
100V
1N4148W
OPT
D504
100V
1N4148W
OPT
L504
DA-8580
EAP38319001
22uH
2S
1S 1F
2F
L505
DA-8580
EAP38319001
22uH
2S
1S 1F
2F
C538
0.47uF
50V
C539
0.47uF
50V
3 15
SPEAKER_R
SPEAKER_L
Change 22uH(L504,L505) TO 15uH/6.3mm After DV1
2A => 5A
T_330uF_Capacitor
T_330uF_Capacitor
MCLK SDATA WCK BCK TP is necessory
Monitor0_1_2 TP is necessory
KIM JONG HYUN
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER
BCM (BRAZIL VENUS) 2009.03.23
R823
1K O
P
T
IC805
AOZ1073AIL
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
L815
3.6uH
RL_ON
12:I5;14:E5
+3.3V_ST
C846
330pF
50V
INV_ON/OFF
12:I5
D803
1N4148W
100V
3.3K
R832
C815
2200pF
IC802
AZ1085S-ADJTR/E1
1
ADJ/GND
2 OUTPUT 3 INPUT
R
8
4
3
1
0
K
C801
10uF
16V
R810
22K
R813
47K
L807
CB4532UK121E
+5.0V
12:A3;2:Y20;2:Z10;B3;C6;H5;7:A3;14:I7;14:J1
R853
300
C838
1uF
25V
3.3K
R873
A_DIM
9:G6;9:I3
C895
0.1uF
50V
TruMotion_240Hz
C868
10uF
10V
C
8
8
2
1
0
u
F
6
.
3
V
D1.8V
R864
620
R854
10K
C821
0.068uF
R812
47K
R824
10K
22uF
C819
16V
C876
100uF
16V
0.1uF
C808
16V
OPT
C
1
8
1
0
1
0
u
F
6
.
3
V
R870
10K
OPT
L817
2.2uH
C896
22uF
16V
C840
1000pF
50V
L826
BG2012B080TF
Q812
SI4804BDY
3
S2
2
G1
4
G2
1
S1
5
D2_1
6
D2_2
7
D1_1
8
D1_2
C
1
8
0
7
0
.
1
u
F
R
8
5
5
1
2
.
4
K
1
%
C870
0.1uF
16V
PWM_DIM
9:G7;9:I3;7:I5
Q806
2SC3052
E
B
C
R
8
4
0
3
9
K
C824
0.1uF
50V
OPT
C851
470pF
IC803
SC4215ISTRT
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
22uF
C842
16V
+12V
R835
0
+1.8V_MEMC
R
8
7
2
1
.
2
K
C
8
8
3
1
0
0
u
F
1
6
V
+3.3V_MEMC
D1.2V
R
8
1
1
2
2
K
R805
10K
R849
10K
R
8
7
5
0
C803
0.1uF
16V
C817
4.7uF
25V
OPT
R833
390K
1/8W
C
8
8
5
3
3
u
F
C
1
8
0
2
10uF
25V
D805
SAM2333
A
2
[
G
N
]
C
A
1
[
R
D
]
C826
47uF
25V
C
8
4
5
0
.
1
u
F
5
0
V
R827
10K
OPT
C
8
7
8
0
.
1
u
F
+12V
12:A3;A6;B5;F7;G7;I2;14:B2
IC807
SC4215ISTRT
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
R869
0
OPT
R828
10K
OPT
C820
15pF
50V
C836
0.1uF
C832
1uF
25V
+5.0V
C829
1uF
25V
OPT
R845
15K
C856
6800pF
L804
BG2012B080TF
R
8
4
1
1
8
K
A2.5V
+5.0V
C811
0.1uF
C
8
3
0
2
2
0
0
p
F
Q813
2SC3875S(ALY)
OPT
E
B
C
Q
8
0
2
2SC3052 E
B
C
C
8
4
4
0
.
1
u
F
R
8
1
6
6
.
8
K
O
P
T
C
1
8
0
4
4
7
0
p
F
R807
0
OPT
Q807
2SC3875S(ALY)
OPT E
B
C
C
8
8
1
1
0
u
F
6
.
3
V
R826
10K
OPT
R
8
4
4
1
1
K
R821
1.8K
C859
0.1uF
D2.5V
L812
MLB-201209-0120P-N2
L
8
0
1
C
B
3
2
1
6
P
A
5
0
1
E
C1805
1uF
25V
L828
2.2uH
R829
0
+3.3V_ST
C899
100uF
16V
C
8
1
4
0
.
1
u
F
1
6
V
C1806
1uF
25V
R
8
4
2
2
K
P801
FM20020-24
19
N.C
14
12V
9
5.2V
4
GND
18
24V
13
12V
8
5.2V
3
GND
17
24V
12
GND
7
5.2V
2
POWER_ON
16
GND
11
GND
6
GND
1
N.C
20
Inverter_On
15
GND
10
5.2V
5
GND
21
A.Dim
22
Error_Out
23
N.C
24
PWM_Dim
25
G
N
D
+3.3V_ST
IC801
AZ1117D-3.3TRE1
1
ADJ/GND
2 OUTPUT 3 INPUT
+5V_ST
C
1
8
0
9
10uF
25V
C807
68uF
35V
C
8
5
2
1
0
u
F
6
.
3
V
R806
10K
OPT
D3.3V
R825
66.5
1%
C
1
8
0
0
1
u
F
2
5
V
C806
0.1uF
16V
OPT
C
8
7
7
0
.
1
u
F
1
6
V
C812
0.1uF
50V
D3.3V
C
8
8
7
0
.
1
u
F
C
8
8
6
0
.
1
u
F
D3.3V
R
8
7
4
1
.
1
K
C835
1uF
25V
C
8
6
1
0
.
0
1
u
F
C
1
8
1
2
1
0
u
F
6
.
3
V
Q804
SI4925BDY
3 S2
2 G1
4 G2
1 S1
5 D2_1
6 D2_2
7 D1_1
8 D1_2
Q809
SI4804BDY
3
S2
2
G1
4
G2
1
S1
5
D2_1
6
D2_2
7
D1_1
8
D1_2
C
8
8
4
0
.
0
1
u
F
D802
1N4148W
100V
L819
2.2uH
+12V
C860
10uF
16V
+5V_ST
C1801
0.01uF
Q803
2SC3052
E
B
C
D801
1N4148W
100V
C872
1uF
25V
C804
1uF
50V
IC806
SC2621ASTRT
3
COMP
2
OCS
4
FB
1
BST
6
LDFB
5
LDOG
7
GND_1
8
VCC
9
NC
10
DRV
11
DL
12
GND_2
13
PN
14
DH
PANEL_CTL
12:I5
C
1
8
1
3
1
0
u
F
6
.
3
V
R
8
4
6
1
K
+5V_ST
ERROR_OUT
12:F6
R852
10K
R857
56
1%
OPC_OUT1
7:I5
C805
1uF
25V
C822
0.1uF
C
1
8
0
3
3
3
u
F
1
0
V
A3.3V
C880
470pF
C
8
7
5
1
0
u
F
6
.
3
V
C
8
2
5
2
2
0
p
F
C828
0.1uF
50V
R830
0
A1.2V
+12V
C1811
1uF
25V
IC809
SC2621ASTRT
3
COMP
2
OCS
4
FB
1
BST
6
LDFB
5
LDOG
7
GND_1
8
VCC
9
NC
10
DRV
11
DL
12
GND_2
13
PN
14
DH
R822
0
OPT
C
8
3
9
22uF
16V
+1.8V_MEMC
+12V
12:A3;A6;C4;F7;G7;I2;14:B2
C818
330uF
4V
R871
20K
C
8
6
2
4
7
0
p
F
C
8
8
8
3
3
u
F
1
0
V
C873
1uF
25V
C833
22uF
25V
+12V
6.8K
R831
C841
10uF
+24V
+1.26V_MEMC
+5.0V
C827
100uF
R
8
4
8
1
.
5
K
R818
3.3K R801
4.7K
C
8
1
0
2
2
u
F
1
6
V
+5V_ST
C853
10uF
16V
R819
56
1%
C837
1uF
25V
R862
5.6K
C863
10uF
16V
R856
22K
L808
MLB-201209-0120P-N2
IC804
SC2621ASTRT
3
COMP
2
OCS
4
FB
1
BST
6
LDFB
5
LDOG
7
GND_1
8
VCC
9
NC
10
DRV
11
DL
12
GND_2
13
PN
14
DH
Q810
SI4804BDY
3
S2
2
G1
4
G2
1
S1
5
D2_1
6
D2_2
7
D1_1
8
D1_2
R815
100
12V_TCON
7:I5;7:I7
C
8
9
8
1uF
25V
R859
330K
1/10W
R814
15K
1%
C802
68uF
35V
R
8
4
7
2
0
0
R863
1K
C
1
8
1
4
1
0
u
F
6
.
3
V
C858
33uF
10V
C1815
10uF
6.3V
R
8
7
6
1
K
L
D
1
SAM2333
A
2
[
G
N
]
C
A
1
[
R
D
]
0
R802
R
8
7
7
0
R
8
7
8
0
R834
150K
1/10W
Q805
RT1P141C-T112
E
B
C
R817
33K
O
P
T
R820
33K
C1816
10uF
6.3V
C1808
1
0
0
u
F
1
6
V
C
8
6
5
1
0
u
F
6
.
3
V
C
8
5
4
3
3
0
u
F
4
V
J
P
8
1
0
C1817
10uF
C855
10uF
6.3V
C1818
0.1uF
50V
OPT
C1819
0.1uF
50V
OPT
L805
CB4532UK121E
R861
3.3
R837
3.3
R
8
3
6
3
.
3
C879
470pF
C848
470pF
C
8
4
7
4
7
0
p
F
L
8
2
4
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
L829
MLB-201209-0120P-N2
L822
MLB-201209-0120P-N2
L830
MLB-201209-0120P-N2
L827
MLB-201209-0120P-N2
L
8
1
3
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
L806
MLB-201209-0120P-N2
L821
MLB-201209-0120P-N2
L
8
1
1
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
15 4
AN SO YOUNG
* FROM LIPS & POWER B/D -->Apply changed Pin Map
220uF ==> 100uF*2 + 22uF for Depth
600 mA
must be placed with pin#8,#10 as close as possible.
VOUT : 2.533V
400 mA + 600 mA
FLASH, A1.2, +1.8_DDR_BCM3556, VTT
R1
750 mA
* +5v_ST to +3.3V_ST
Well change SI4804 to KECs Product
415 mA @85% efficiency
R2
* +1.26V Core for FRC
* +1.8V_MEMC for FRC DDR
1.8V_BCM3556
* +5.0V to 1.2V
must be placed with pin#8,#10 as close as possible.
* +12v -> PANEL_POWER
* +12V to +5.0V
* D1.8V
Vout = (1+R2/R1)*1.25
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR Memory
BCM (BRAZIL VENUS) 2009.03.23
DDR01_A[0]
DDR01_A[1]
DDR01_A[2]
DDR01_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR01_A[7]
DDR01_A[8]
DDR01_A[9]
DDR01_A[10]
DDR01_A[12]
DDR01_A[13]
DDR01_A[11]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[12]
DDR0_DQ[15]
DDR0_DQ[8]
DDR0_DQ[13]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[14]
DDR1_DQ[4]
DDR1_DQ[12]
DDR1_DQ[7]
DDR1_DQ[0]
DDR1_DQ[5]
DDR1_DQ[8]
DDR1_DQ[1]
DDR1_DQ[13]
DDR1_DQ[15]
DDR1_DQ[9]
DDR1_DQ[10]
DDR1_DQ[11]
DDR1_DQ[14]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_DQ[6]
DDR01_A[0]
DDR01_A[1]
DDR01_A[2]
DDR01_A[3]
DDR01_A[7]
DDR01_A[8]
DDR01_A[9]
DDR01_A[12]
DDR01_A[13]
DDR01_A[10]
DDR01_A[11]
DDR0_A[4]
DDR0_A[6]
DDR0_A[5]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR01_A[2]
DDR1_DQ[0]
DDR1_DQ[4]
DDR1_DQ[11]
DDR1_DQ[6]
DDR1_DQ[12]
DDR01_A[7]
DDR1_DQ[2]
DDR1_DQ[14]
DDR1_DQ[8]
DDR1_A[5]
DDR1_DQ[3]
DDR1_DQ[1]
DDR01_A[3]
DDR01_A[0]
DDR01_A[8]
DDR1_DQ[7]
DDR01_A[1]
DDR01_A[12]
DDR01_A[9]
DDR1_DQ[9]
DDR01_A[11]
DDR1_DQ[13]
DDR1_A[4]
DDR01_A[10]
DDR1_DQ[10]
DDR1_A[6]
DDR1_DQ[15]
DDR1_DQ[5]
DDR01_A[2]
DDR0_DQ[0]
DDR0_DQ[4]
DDR0_DQ[11]
DDR0_DQ[6]
DDR0_DQ[12]
DDR01_A[7]
DDR0_DQ[2]
DDR0_DQ[14]
DDR0_DQ[8]
DDR0_A[5]
DDR0_DQ[3]
DDR0_DQ[1]
DDR01_A[3]
DDR01_A[0]
DDR01_A[8]
DDR0_DQ[7]
DDR01_A[1]
DDR01_A[12]
DDR01_A[9]
DDR0_DQ[9]
DDR01_A[11]
DDR0_DQ[13]
DDR0_A[4]
DDR01_A[10]
DDR0_DQ[10]
DDR0_A[6]
DDR0_DQ[15]
DDR0_DQ[5]
A1.2V
C345 0.1uF
C346 0.1uF
DDR01_CKE E5;H5;I2
DDR01_ODT E5;H5;I1
DDR0_CLK E5
DDR0_CLKb E5
DDR1_CLK H5
DDR1_CLKb H5
DDR01_A[0-3] E6;H6;H2
DDR0_A[4-6] D6;H2
DDR01_A[7-13] E6;H6;H2
DDR1_A[4-6] H6;H1
DDR01_BA0
DDR01_BA1
DDR01_BA2
DDR01_CASb
DDR0_DQ[0-15] G6
DDR1_DQ[0-15] J6
DDR0_DM0 E4
DDR0_DM1 E4
DDR1_DM1 H4
DDR1_DM0 H4
DDR0_DQS0b E4
DDR0_DQS0 E4
DDR0_DQS1 E4
DDR0_DQS1b E4
DDR1_DQS0 H4
DDR1_DQS1 H4
DDR1_DQS1b H4
DDR1_DQS0b H4
DDR01_RASb
E5;H5;I1
DDR0_VREF0
DDR1_VREF0
DDR01_WEb
R304
75
R305
75
R306
75
R307
75
R310 75 OPT
R308
75
R309
75
R311 75
C336
0.01uF
C337
0.01uF
C338
0.01uF
C339
0.01uF
C340
0.01uF
C341
0.01uF
DDR01_CKE B6;E5;H5
DDR01_BA0 B5;E5;H5
DDR01_BA1 B5;E5;H5
DDR01_BA2 B5;E5;H5
DDR01_ODT B6;E5;H5
DDR01_RASb B2;E5;H5
DDR01_CASb B5;E5;H5
DDR01_WEb B2;E5;H5
DDR01_A[0-3,7-13]
DDR0_A[4-6]
DDR1_A[4-6]
DDR1_DQ[0-15]
B4
DDR1_CLKb B6
R303
100
DDR1_VREF0
DDR1_DM0 B3
DDR1_DQS0 B3
DDR01_WEb B2;E5;I1
DDR1_A[4-6] B5;H1
DDR01_CASb B5;E5;I1
DDR1_DM1 B3
DDR01_BA2 B5;E5;I1
D1.8V
C321
470pF
DDR01_CKE B6;E5;I2
DDR1_CLK B6
DDR01_A[0-3,7-13] B6;E6;H2;B5
DDR1_DQS1 B3
DDR01_BA1 B5;E5;I1
DDR1_DQS1b B3
DDR01_BA0 B5;E5;I1
C322
0.1uF
DDR01_ODT B6;E5;I1
DDR1_DQS0b B3
DDR01_RASb B2;E5;I1
DDR0_DQ[0-15] B4
DDR0_CLKb B6
R300
100
DDR0_VREF0
DDR0_DM0 B3
DDR0_DQS0 B3
DDR0_A[4-6] B6;H2
DDR01_WEb B2;H5;I1
DDR01_CASb B5;H5;I1
DDR01_BA2 B5;H5;I1
DDR0_DM1 B3
C300
470pF
D1.8V
DDR01_CKE B6;H5;I2
DDR0_CLK B6
DDR01_A[0-3,7-13] B6;H6;H2;B5
DDR0_DQS1 B3
DDR01_BA1 B5;H5;I1
DDR0_DQS1b B3
DDR01_BA0 B5;H5;I1
C301
0.1uF
DDR01_ODT B6;H5;I1
DDR0_DQS0b B3
DDR01_RASb B2;H5;I1
D1.8V
R312 0
OPT
R313
240
C355
0.1uF
C
3
5
8
1uF
C
3
5
9
470pF
C
3
6
0
470pF
C
3
6
1
1uF
C362
0.1uF
DDR_VTT
C
3
4
3
1uF
C
3
4
2
470pF
C
3
4
7
1uF
C
3
4
4
470pF
R301
22
C
3
0
7
0
.
1
u
F
C
3
1
6
2
7
0
0
p
F
C
3
1
3
0
.
1
u
F
C
3
2
9
4
7
0
p
F
C
3
3
1
0
.
1
u
F
C
3
1
4
0
.
0
1
u
F
C
3
3
4
2
7
0
0
p
F
C
3
2
4
1
0
u
F
C
3
1
1
4
7
0
p
F
D1.8V
C
3
3
5
4
7
0
p
F
C
3
1
0
2
7
0
0
p
F
D1.8V
C
3
5
1
0
.
1
u
F
C
3
1
7
4
7
0
p
F
C
3
1
2
1
0
u
F
C
3
5
0
0
.
1
u
F
C
3
2
3
1
0
0
u
F
C
3
2
6
0
.
0
1
u
F
C
3
0
5
1
0
0
u
F
C
3
3
3
0
.
0
4
7
u
F
C
3
2
7
0
.
0
4
7
u
F
C
3
2
5
0
.
1
u
F
C
3
5
4
0
.
1
u
F
C
3
0
8
0
.
0
1
u
F
C
3
5
2
0
.
1
u
F
C
3
3
0
1
0
u
F
C
3
3
2
0
.
0
1
u
F
C
3
2
8
2
7
0
0
p
F
C
3
0
6
1
0
u
F
C
3
5
3
0
.
1
u
F
C
3
0
9
0
.
0
4
7
u
F
C
3
1
5
0
.
0
4
7
u
F
C
3
4
9
0
.
1
u
F
D3.3V
C869
100uF
16V
DDR1_VREF0
R851 0
C834
0.1uF
16V
DDR_VTT
DDR0_VREF0
C874
10uF
10V
R858
1M
D1.8V
C897
0.1uF
16V
C864
0.1uF
16V
IC808
BD35331F-E2
3
VTTS
2
EN
4
VREF
1
GND
5
VDDQ
6
VCC
7
VTT_IN
8
VTT
R850 0
C
8
6
6
0
.
1
u
F
1
6
V
C831
0.1uF
16V
C871
1uF
6.3V
C867
100uF
16V
IC100
BCM3556
DDR_BVDD0
A6
DDR_BVDD1
A24
DDR_BVSS0
B7
DDR_BVSS1
B24
DDR_PLL_TEST
F20
DDR_PLL_LDO
B23
DDR01_CKE
B17
DDR_COMP
C22
DDR01_ODT
E16
DDR_EXT_CLK
C23
DDR0_CLK
B12
DDR0_CLKB
C12
DDR1_CLK
A13
DDR1_CLKB
A12
DDR01_A00
B15
DDR01_A01
E14
DDR01_A02
A15
DDR01_A03
D15
DDR0_A04
E13
DDR0_A05
E12
DDR0_A06
F13
DDR01_A07
C14
DDR01_A08
F14
DDR01_A09
B14
DDR01_A10
D14
DDR01_A11
C13
DDR01_A12
D13
DDR01_A13
B13
DDR1_A04
F15
DDR1_A05
C15
DDR1_A06
D16
DDR01_BA0
F16
DDR01_BA1
B16
DDR01_BA2
E15
DDR01_CASB
A17
DDR0_DQ00
A8
DDR0_DQ01
B11
DDR0_DQ02
B8
DDR0_DQ03
D11
DDR0_DQ04
E11
DDR0_DQ05
C8
DDR0_DQ06
C11
DDR0_DQ07
C9
DDR0_DQ08
D8
DDR0_DQ09
E10
DDR0_DQ10
E9
DDR0_DQ11
F11
DDR0_DQ12
F12
DDR0_DQ13
E8
DDR0_DQ14
D10
DDR0_DQ15
F8
DDR1_DQ00
C18
DDR1_DQ01
C20
DDR1_DQ02
A18
DDR1_DQ03
B21
DDR1_DQ04
C21
DDR1_DQ05
B18
DDR1_DQ06
B20
DDR1_DQ07
D18
DDR1_DQ08
E18
DDR1_DQ09
D21
DDR1_DQ10
F18
DDR1_DQ11
E20
DDR1_DQ12
A22
DDR1_DQ13
F17
DDR1_DQ14
B22
DDR1_DQ15
E17
DDR0_DM0
A10
DDR0_DM1
C10
DDR1_DM0
A20
DDR1_DM1
F19
DDR0_DQS0
B10
DDR0_DQS0B
B9
DDR0_DQS1
F10
DDR0_DQS1B
F9
DDR1_DQS0
B19
DDR1_DQS0B
C19
DDR1_DQS1
E19
DDR1_DQS1B
D19
DDR01_RASB
C16
DDR_VREF0
A7
DDR_VREF1
A23
DDR01_WEB
C17
DDR_VDDP1P8_1
C7
DDR_VDDP1P8_2
D22
IC301
HYB18TC1G160C2F-1.9
Qimonda
J2 VREF
J8 CK
H2 VSSQ2
B7 UDQS
N8 A4
P8 A8
L1 BA2
L2 BA0
R8 NC3
K7 RAS
F8 VSSQ3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC4
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC5
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC1
N2 A3
P2 A7
H8 VSSQ1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC2
E7 VSSQ5
D8 VSSQ6
D2 VSSQ7
A7 VSSQ8
B8 VSSQ9
B2 VSSQ10
P9 VSS1
N1 VSS2
J3 VSS3
E3 VSS4
A3 VSS5
G9 VDDQ1
G7 VDDQ2
G3 VDDQ3
G1 VDDQ4
E9 VDDQ5
C9 VDDQ6
C7 VDDQ7
C3 VDDQ8
C1 VDDQ9
A9 VDDQ10
R1 VDD1
M9 VDD2
J9 VDD3
E1 VDD4
A1 VDD5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
IC300
HYB18TC1G160C2F-1.9
Qimonda
J2 VREF
J8 CK
H2 VSSQ2
B7 UDQS
N8 A4
P8 A8
L1 BA2
L2 BA0
R8 NC3
K7 RAS
F8 VSSQ3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC4
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC5
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC1
N2 A3
P2 A7
H8 VSSQ1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC2
E7 VSSQ5
D8 VSSQ6
D2 VSSQ7
A7 VSSQ8
B8 VSSQ9
B2 VSSQ10
P9 VSS1
N1 VSS2
J3 VSS3
E3 VSS4
A3 VSS5
G9 VDDQ1
G7 VDDQ2
G3 VDDQ3
G1 VDDQ4
E9 VDDQ5
C9 VDDQ6
C7 VDDQ7
C3 VDDQ8
C1 VDDQ9
A9 VDDQ10
R1 VDD1
M9 VDD2
J9 VDD3
E1 VDD4
A1 VDD5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
IC300-*1
EDE1116ACBG-1J-E
ELPIDA
J2 VREF
J8 CK
H2 VSSQ_2
B7 UDQS
N8 A4
P8 A8
L1 BA2
L2 BA0
R8 NC_3
K7 RAS
F8 VSSQ_3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC_5
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ_4
B3 UDM
M2 A10
K2 CKE
R7 NC_6
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC_1
N2 A3
P2 A7
H8 VSSQ_1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC_2
E7 VSSQ_5
D8 VSSQ_6
D2 VSSQ_7
A7 VSSQ_8
B8 VSSQ_9
B2 VSSQ_10
P9 VSS_1
N1 VSS_2
J3 VSS_3
E3 VSS_4
A3 VSS_5
G9 VDDQ_1
G7 VDDQ_2
G3 VDDQ_3
G1 VDDQ_4
E9 VDDQ_5
C9 VDDQ_6
C7 VDDQ_7
C3 VDDQ_8
C1 VDDQ_9
A9 VDDQ_10
R1 VDD_1
M9 VDD_2
J9 VDD_3
E1 VDD_4
A1 VDD_5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
IC301-*1
EDE1116ACBG-1J-E
ELPIDA
J2 VREF
J8 CK
H2 VSSQ_2
B7 UDQS
N8 A4
P8 A8
L1 BA2
L2 BA0
R8 NC_3
K7 RAS
F8 VSSQ_3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC_5
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ_4
B3 UDM
M2 A10
K2 CKE
R7 NC_6
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC_1
N2 A3
P2 A7
H8 VSSQ_1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC_2
E7 VSSQ_5
D8 VSSQ_6
D2 VSSQ_7
A7 VSSQ_8
B8 VSSQ_9
B2 VSSQ_10
P9 VSS_1
N1 VSS_2
J3 VSS_3
E3 VSS_4
A3 VSS_5
G9 VDDQ_1
G7 VDDQ_2
G3 VDDQ_3
G1 VDDQ_4
E9 VDDQ_5
C9 VDDQ_6
C7 VDDQ_7
C3 VDDQ_8
C1 VDDQ_9
A9 VDDQ_10
R1 VDD_1
M9 VDD_2
J9 VDD_3
E1 VDD_4
A1 VDD_5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
IC301-*2
H5PS1G63EFR-20L
HYNIX
J2 VREF
J8 CK
H2 VSSQ_2
B7 UDQS
N8 A4
P8 A8
L1 NC_4/BA2
L2 BA0
R8 NC_3/A13
K7 RAS
F8 VSSQ_3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC_5/A14
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ_4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC_6/A15
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC_1
N2 A3
P2 A7
H8 VSSQ_1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC_2
E7 VSSQ_5
D8 VSSQ_6
D2 VSSQ_7
A7 VSSQ_8
B8 VSSQ_9
B2 VSSQ_10
P9 VSS_1
N1 VSS_2
J3 VSS_3
E3 VSS_4
A3 VSS_5
G9 VDDQ_1
G7 VDDQ_2
G3 VDDQ_3
G1 VDDQ_4
E9 VDDQ_5
C9 VDDQ_6
C7 VDDQ_7
C3 VDDQ_8
C1 VDDQ_9
A9 VDDQ_10
R1 VDD_1
M9 VDD_2
J9 VDD_3
E1 VDD_4
A1 VDD_5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
IC300-*2
H5PS1G63EFR-20L
HYNIX
J2 VREF
J8 CK
H2 VSSQ_2
B7 UDQS
N8 A4
P8 A8
L1 NC_4/BA2
L2 BA0
R8 NC_3/A13
K7 RAS
F8 VSSQ_3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC_5/A14
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ_4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC_6/A15
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC_1
N2 A3
P2 A7
H8 VSSQ_1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC_2
E7 VSSQ_5
D8 VSSQ_6
D2 VSSQ_7
A7 VSSQ_8
B8 VSSQ_9
B2 VSSQ_10
P9 VSS_1
N1 VSS_2
J3 VSS_3
E3 VSS_4
A3 VSS_5
G9 VDDQ_1
G7 VDDQ_2
G3 VDDQ_3
G1 VDDQ_4
E9 VDDQ_5
C9 VDDQ_6
C7 VDDQ_7
C3 VDDQ_8
C1 VDDQ_9
A9 VDDQ_10
R1 VDD_1
M9 VDD_2
J9 VDD_3
E1 VDD_4
A1 VDD_5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
BCM recommends to remove this R
6 15
HONG YEON HYUK
* DDR_VTT
A B C D E F G H I J
1
2
3
4
5
6
7
[E1]
[D1]
[L9]
[N5]
[N4]
[N12]
[N13]
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
LVDS / Mstar FRC
BCM (BRAZIL VENUS)
URSA_DQ[28]
URSA_C4P
U
R
S
A
_
A
[
1
0
]
URSA_C4M
U
R
S
A
_
D
Q
[
1
4
]
URSA_D1P U
R
S
A
_
D
Q
[
0
-
3
1
]
U
R
S
A
_
D
Q
[
4
]
URSA_BCKM
U
R
S
A
_
A
[
1
]
URSA_DQ[25]
URSA_DQ[18]
URSA_DQ[21]
U
R
S
A
_
A
4
M
URSA_BCKP
U
R
S
A
_
D
Q
[
9
]
URSA_B2P
U
R
S
A
_
D
Q
[
6
]
U
R
S
A
_
A
[
8
]
U
R
S
A
_
B
1
M
U
R
S
A
_
B
0
M
U
R
S
A
_
B
1
P
U
R
S
A
_
B
0
P
U
R
S
A
_
A
[
3
]
U
R
S
A
_
A
4
P
U
R
S
A
_
A
3
P
URSA_D3M
URSA_DCKM
U
R
S
A
_
D
Q
[
5
]
U
R
S
A
_
D
Q
[
1
2
]
URSA_DCKP
URSA_B2M
URSA_D2P
U
R
S
A
_
A
[
5
]
URSA_D2M
U
R
S
A
_
D
Q
[
3
]
URSA_DQ[20]
URSA_DQ[26]
U
R
S
A
_
A
3
M
U
R
S
A
_
A
C
K
M
URSA_DQ[31]
U
R
S
A
_
A
2
P
URSA_B4M
URSA_DQ[30]
U
R
S
A
_
D
Q
[
0
]
U
R
S
A
_
A
[
2
]
U
R
S
A
_
D
Q
[
7
]
U
R
S
A
_
D
Q
[
2
]
U
R
S
A
_
A
[
1
1
]
U
R
S
A
_
A
[
6
]
URSA_C2P
URSA_C0P
U
R
S
A
_
A
[
7
]
URSA_DQ[16]
URSA_DQ[27]
URSA_DQ[29]
U
R
S
A
_
D
Q
[
1
0
]
URSA_DQ[17]
URSA_DQ[19]
U
R
S
A
_
A
C
K
P
U
R
S
A
_
A
1
M
U
R
S
A
_
A
2
M
U
R
S
A
_
A
1
P
U
R
S
A
_
A
0
P
U
R
S
A
_
A
0
M
URSA_C0M
URSA_C1P
URSA_C1M
U
R
S
A
_
D
Q
[
1
1
]
U
R
S
A
_
A
[
4
]
URSA_DQ[22]
U
R
S
A
_
A
[
0
]
U
R
S
A
_
D
Q
[
1
5
]
URSA_D4M
URSA_D4P
URSA_DQ[24]
URSA_D3P
URSA_D0M
URSA_D0P
U
R
S
A
_
D
Q
[
8
]
URSA_C2M
URSA_D1M
U
R
S
A
_
A
[
1
2
]
URSA_B4P
URSA_DQ[23]
URSA_B3P
URSA_B3M
U
R
S
A
_
A
[
9
]
U
R
S
A
_
D
Q
[
1
3
]
URSA_CCKP
URSA_C3P
URSA_CCKM
URSA_C3M
U
R
S
A
_
D
Q
[
1
]
URSA_C3P
URSA_A3P
URSA_C3M
URSA_A4P
URSA_B4M
URSA_D1P
URSA_B1P
URSA_A2M
URSA_BCKP
URSA_ACKM
URSA_B3P
URSA_A3M
URSA_B4P
URSA_A4M
URSA_D2M
URSA_A1M
URSA_D3P
URSA_A0M
URSA_DCKM
URSA_C2M
URSA_B0P
URSA_B0M
URSA_B2P
URSA_D4M
URSA_C0P
URSA_D0M
URSA_C4M
URSA_D1M
URSA_C4P
URSA_B1M
URSA_D0P
URSA_D2P
URSA_B2M
URSA_DCKP
URSA_C0M
URSA_C2P
URSA_C1P
URSA_A0P
URSA_C1M
URSA_A1P
URSA_BCKM
URSA_CCKP
URSA_A2P
URSA_D4P
URSA_CCKM
URSA_ACKP
URSA_B3M
URSA_D3M
R922
100
L
V
D
S
_
T
X
_
1
_
D
A
T
A
0
_
N
L
V
D
S
_
T
X
_
1
_
D
A
T
A
1
_
P
+3.3V_MEMC
R
9
0
8
2
.
2
K
O
P
T
L
V
D
S
_
T
X
_
1
_
D
A
T
A
3
_
P
C
9
0
8
0
.
1
u
F
C
9
3
3
1
0
u
F
U
R
S
A
_
B
A
0
L
V
D
S
_
T
X
_
0
_
D
A
T
A
1
_
P
C
9
2
3
0
.
1
u
F
L
9
0
4
B
L
M
1
8
P
G
1
2
1
S
N
1
D
C
9
1
6
1
0
u
F
L
V
D
S
_
T
X
_
0
_
D
A
T
A
3
_
P
R946 56
L
V
D
S
_
T
X
_
1
_
D
A
T
A
4
_
P
C953
0.1uF
C
9
0
4
0
.
1
u
F
C
9
2
4
1
u
F
URSA_DQM3
U
R
S
A
_
M
C
L
K
E
R909 0
C
9
1
4
0
.
1
u
F
R
9
3
9
1
K
O
P
T
M_SPI_DO
+1.26V_MEMC
L
V
D
S
_
T
X
_
0
_
D
A
T
A
3
_
N
R926
100
U
R
S
A
_
A
[
0
-
1
2
]
R920
100
U
R
S
A
_
D
Q
S
B
0
ISP_TXD_TR A3
C
9
3
8
0.1uF
C
9
4
3
0
.
1
u
F
ISP_TXD_TR
B6
M
_
X
T
A
L
O
C920
0.1uF
R924
100
C919
0.1uF
URSA_DQSB3
L
V
D
S
_
T
X
_
1
_
C
L
K
_
N
URSA_DQS2
C930
0.1uF
R918
100
+3.3V_MEMC
C921 0.1uF
C
9
3
1
1
0
u
F1
0
V
+3.3V_MEMC
+3.3V_MEMC
C956
0.1uF
L
V
D
S
_
T
X
_
1
_
D
A
T
A
3
_
N
C
9
5
1
0
.
1
u
F
R
9
4
2
1
K
L
9
0
5
BLM18PG121SN1D
C
9
4
1
0
.
1
u
F
R931
820
U
R
S
A
_
D
Q
M
1
M_SPI_DO
C929
0
.
1
u
F
IC902
W25X20AVSNIG
3 WP
2 DO
4 GND
1 CS
5 DIO
6 CLK
7 HOLD
8 VCC
URSA_MCLKZ
C
9
4
8
0
.
1
u
F
URSA_DQM2
U
R
S
A
_
D
Q
S
1
M_SPI_CK H3
L
V
D
S
_
T
X
_
0
_
D
A
T
A
4
_
P
R925
100
L
V
D
S
_
T
X
_
1
_
D
A
T
A
2
_
N
M
_
X
T
A
L
I
L
9
0
8
B
L
M
1
8
P
G
1
2
1
S
N
1
D
C957
0.1uF
ISP_RXD_TR
B6
R923
100
X901
12MHz
SCL3_3.3V 9:I4
U
R
S
A
_
W
E
Z
C
9
3
4
0.1uF
C
9
0
9
1
0
u
F
+5.0V
C
9
3
2
0.1uF
URSA_MCLK
L
V
D
S
_
T
X
_
0
_
D
A
T
A
4
_
N
L
9
0
7
B
L
M
1
8
P
G
1
2
1
S
N
1
D
L
9
0
2
B
L
M
1
8
P
G
1
2
1
S
N
1
D
R915 1K
L
V
D
S
_
T
X
_
1
_
D
A
T
A
1
_
N
R
9
0
7
2
.
2
K
O
P
T
L
V
D
S
_
T
X
_
1
_
D
A
T
A
4
_
N
U
R
S
A
_
C
A
S
Z
ISP_RXD_TR A3
M_XTALI
R
9
3
8
1
K
R917
100
R
9
1
4
1
0
K
R951 56
+3.3V_MEMC
C913
0.1uF
16V
+3.3V_MEMC
R952 56
U
R
S
A
_
B
A
1
L
V
D
S
_
T
X
_
0
_
D
A
T
A
1
_
N
+3.3V_MEMC
C925 0.1uF
FRC_RESET
M_SPI_CZ
C
9
1
0
1
0
u
F
C
9
0
6
1
0
u
F
C
9
4
0
0
.
1
u
F L
9
0
6
B
L
M
1
8
P
G
1
2
1
S
N
1
D
C912
0.1uF
16V
L
V
D
S
_
T
X
_
1
_
D
A
T
A
2
_
P
C927
0.1uF
+1.8V_MEMC
+3.3V_MEMC
C
9
3
9
0.1uF
R
9
1
3
1
0
K
L
V
D
S
_
T
X
_
0
_
D
A
T
A
2
_
N
U
R
S
A
_
M
C
L
K
1
M_XTALO
L
V
D
S
_
T
X
_
0
_
D
A
T
A
0
_
N
R916 1K
OPT
C
9
5
2
1
0
u
F
C
9
1
7
0
.
1
u
F
L
V
D
S
_
T
X
_
1
_
C
L
K
_
P
C
9
4
9
0
.
1
u
F
M_SPI_DI
SDA3_3.3V 9:I4
C
9
3
7
0
.
1
u
F
URSA_ODT
R928
100
C922
0.1uF
+3.3V_MEMC
L
V
D
S
_
T
X
_
0
_
C
L
K
_
N
R912 100
L
V
D
S
_
T
X
_
0
_
D
A
T
A
2
_
P
L
V
D
S
_
T
X
_
0
_
C
L
K
_
P
R927
100
R910 0
C
9
4
2
0
.
1
u
F
L
9
0
3
B
L
M
1
8
P
G
1
2
1
S
N
1
D
C
9
1
1
1
0
u
F
U
R
S
A
_
R
A
S
Z
L
V
D
S
_
T
X
_
1
_
D
A
T
A
0
_
P
M_SPI_DI H3
C
9
4
4
1
u
F
URSA_DQSB2
U
R
S
A
_
D
Q
S
B
1
C
9
4
5
0
.
1
u
F
C
9
0
1
0
.
1
u
F
R
9
4
3
1
K
O
P
T
C
9
3
6
0.1uF
R911 100
C928
0.1uF
R929
1M
C
9
3
5
0
.
1
u
F
R947 10K
R
9
3
0
0
M_SPI_CK
R945 56
C
9
2
6
0
.
1
u
F
L
V
D
S
_
T
X
_
0
_
D
A
T
A
0
_
P
URSA_DQ[0-31]
U
R
S
A
_
M
C
L
K
Z
1
C
9
5
0
0
.
1
u
F
U
R
S
A
_
D
Q
M
0
C
9
5
8
0
.
1
u
F
M_SPI_CZ
R921
100
C918 0.1uF
R919
100
C955
0.1uF
URSA_DQS3
U
R
S
A
_
D
Q
S
0
C
9
5
4
1
0
u
F
LVDS_SEL
R936 0
OPT
OPC_OUT1
OPC_EN
R937 0
OPC_EN
R941 0 OPC_EN
R953
0
OPT
12V_TCON
R940 0
C
9
6
0
1
0
0
0
p
F
5
0
V
L
9
0
9
C
B
3
2
1
6
P
A
5
0
1
E
PWM_DIM
C
9
6
1
0
.
1
u
F
5
0
V
BIT_SEL
R
9
4
9
3
.
3
K
O
P
T
R
9
5
5
3
.
3
K
P902
TJC2508-4A
1
2
3
4
P903
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
P904
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
IC901
LGE7329A
E1
SDAS
D1
SCLS
F1 GPIO[8]
G1 GPIO[9]
K8 GND_14
E5 VDDC_1
E2 GPIO[10]
F2 GPIO[11]
F3 GPIO[12]
G2 GPIO[13]
M4 GPIO[22]
M5 GPIO[23]
G3 GPIO[14]
E4 GPIO[15]
F4 GPIO[16]
G4 GPIO[17]
H4 GPIO[18]
J4 GPIO[19]
K4 GPIO[20]
L4 GPIO[21]
J6 VDDP_2
H9 GND_7
F6 VDDC_2
H1 MDATA[20]
H2 MDATA[19]
H3 MDATA[17]
J1 MDATA[22]
J2 MDATA[27]
J3 MDATA[28]
K1 MDATA[25]
K2 MDATA[30]
K6 AVDD_DDR_2
K3 DQM[3]
L1 DQM[2]
J8 GND_10
L2 DQS[2]
L3 DQSB[2]
L6 AVDD_DDR_4
L8 VDDP_3
H10 GND_8
M1 DQS[3]
M2 DQSB[3]
L7 AVDD_DDR_5
M3 MDATA[31]
N1 MDATA[24]
J9 GND_11
N2 MDATA[26]
N3 MDATA[29]
L10 AVDD_DDR_6
P1 MDATA[23]
R1 MDATA[16]
T1 MDATA[18]
T2 MDATA[21]
R2 MCLK[0]
P2 MCLKZ[0]
G7 GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T
3
R
A
S
Z
R
3
C
A
S
Z
P
3
M
A
D
R
[
0
]
T
4
M
A
D
R
[
2
]
R
4
M
A
D
R
[
4
]
J
1
0
G
N
D
_
1
2
P
4
M
A
D
R
[
6
]
T
5
M
A
D
R
[
8
]
R
5
M
A
D
R
[
1
1
]
P
5
W
E
Z
T
6
B
A
D
R
[
1
]
R
6
B
A
D
R
[
0
]
P
6
M
A
D
R
[
1
]
T
7
M
A
D
R
[
1
0
]
L
1
1
A
V
D
D
_
D
D
R
_
7
R
7
M
A
D
R
[
5
]
P
7
M
A
D
R
[
9
]
T
8
M
A
D
R
[
1
2
]
R
8
M
A
D
R
[
7
]
P
8
M
A
D
R
[
3
]
N
8
M
C
L
K
E
K
1
0
G
N
D
_
1
6
F
7
V
D
D
C
_
3
T
9
M
D
A
T
A
[
4
]
R
9
M
D
A
T
A
[
3
]
K
7
G
N
D
_
1
3
P
9
M
D
A
T
A
[
1
]
T
1
0
M
D
A
T
A
[
6
]
K
1
1
A
V
D
D
_
D
D
R
_
3
R
1
0
M
D
A
T
A
[
1
1
]
P
1
0
M
D
A
T
A
[
1
2
]
T
1
1
M
D
A
T
A
[
9
]
R
1
1
M
D
A
T
A
[
1
4
]
J
1
1
A
V
D
D
_
D
D
R
_
1
P
1
1
D
Q
M
[
1
]
T
1
2
D
Q
M
[
0
]
R
1
2
D
Q
S
[
0
]
P
1
2
D
Q
S
B
[
0
]
H
1
1
V
D
D
P
_
1
T
1
3
D
Q
S
[
1
]
R
1
3
D
Q
S
B
[
1
]
P
1
3
M
D
A
T
A
[
1
5
]
T
1
4
M
D
A
T
A
[
8
]
R
1
4
M
D
A
T
A
[
1
0
]
P
1
4
M
D
A
T
A
[
1
3
]
T
1
5
M
D
A
T
A
[
7
]
R
1
5
M
D
A
T
A
[
0
]
P
1
5
M
D
A
T
A
[
2
]
T
1
6
M
D
A
T
A
[
5
]
R
1
6
M
C
L
K
[
1
]
P
1
6
M
C
L
K
Z
[
1
]
N
9
G
P
I
O
[
2
6
]
N
1
0
G
P
I
O
[
2
7
]
N
1
1
G
N
D
_
1
7
M
1
1
R
E
S
E
T
G
6
V
D
D
C
_
4
N12
GPIO[28]
N13
GPIO[29]
N14 GPIO[30]
L13 SCK
M13 SDI
M12 SDO
K13 CSZ
L12 PWM1
K12 PWM0
J13 GPIO[0]
H13 GPIO[1]
G13 GPIO[2]
F13 GPIO[3]
E13 GPIO[4]
F12 GPIO[5]
D14 GPIO[6]
E12 GPIO[7]
N6 GPIO[24]
H6 VDDC_5
N15 LVD4M
N16 LVD4P
M14 LVD3M
M15 LVD3P
F8 AVDD_33_1
M16 LVDCKM
L16 LVDCKP
L15 LVD2M
L14 LVD2P
G9 GND_3
K14 LVD1M
J14 LVD1P
J16 LVD0M
J15 LVD0P
H15 LVC4M
H16 LVC4P
H14 LVC3M
G14 LVC3P
G16 LVCCKM
G15 LVCCKP
F15 LVC2M
F16 LVC2P
F14 LVC1M
E14 LVC1P
E16 LVC0M
E15 LVC0P
G10 GND_4
F9 AVDD_33_2
D16 LVB4M
D15 LVB4P
C16 LVB3M
B16 LVB3P
A16 LVBCKM
A15 LVBCKP
B15 LVB2M
C15 LVB2P
D2 GPIO_3
E3 GPIO_10
E10 GPIO_11
D10 GPIO_7
D8 GPIO_5 D
1
2
R
E
X
T
C
1
4
L
V
B
1
M
C
1
3
L
V
B
1
P
A
1
3
L
V
B
0
M
B
1
3
L
V
B
0
P
D
7
G
P
I
O
_
4
D
9
G
P
I
O
_
6
B
1
2
L
V
A
4
M
A
1
2
L
V
A
4
P
C
1
2
L
V
A
3
M
C
1
1
L
V
A
3
P
A
1
1
L
V
A
C
K
M
B
1
1
L
V
A
C
K
P
B
1
0
L
V
A
2
M
A
1
0
L
V
A
2
P
C
1
0
L
V
A
1
M
C
9
L
V
A
1
P
A
9
L
V
A
0
M
B
9
L
V
A
0
P
F
1
0
A
V
D
D
_
P
L
L
G
8
G
N
D
_
2
D
1
1
G
P
I
O
_
8
D
1
3
G
P
I
O
_
9
E
1
1
G
P
I
O
_
1
2
N
7
G
P
I
O
[
2
5
]
D
6
S
C
L
M
D
5
S
D
A
M
A
1
4
G
P
I
O
_
1
B
1
4
G
P
I
O
_
2
D
3
X
I
N
D
4
X
O
U
T
K
1
6
G
P
I
O
_
1
4
K
1
5
G
P
I
O
_
1
3
H
7
G
N
D
_
5
G
1
1
A
V
D
D
_
L
V
D
S
_
2
B
8
R
O
0
N
A
8
R
O
0
P
C
8
R
O
1
N
C
7
R
O
1
P
A
7
R
O
2
N
B
7
R
O
2
P
B
6
R
O
C
K
N
A
6
R
O
C
K
P
C
6
R
O
3
N
C
5
R
O
3
P
A
5
R
O
4
N
B
5
R
O
4
P
H
8
G
N
D
_
6
F
1
1
A
V
D
D
_
L
V
D
S
_
1
B
4
R
E
0
N
A
4
R
E
0
P
C
4
R
E
1
N
C
3
R
E
1
P
A
3
R
E
2
N
B
3
R
E
2
P
B
2
R
E
C
K
N
A
2
R
E
C
K
P
C
2
R
E
3
N
C
1
R
E
3
P
A
1
R
E
4
N
B
1
R
E
4
P
G
N
D
_
9
J
7
GND_15K9
12V_TCON
R
9
5
4
3
.
3
K
O
P
T
+3.3V_MEMC
R
9
4
8
4
9
9
O
P
C
_
E
N
R3029
0
1/16W
5%
OPT
LVDS_SEL
9:G6;I5
R
9
3
3
4
.
7
K
C
9
1
5
1
0
u
F
6
.
3
V
C
3
0
1
9
1
0
u
F
6
.
3
V
C
9
0
7
1
0
u
F
C
3
0
2
0
1
0
u
F
C947
22pF
C946
22pF
7 15
HIGH
PI Result
EEPROM
HIGH
* XTAL
I2C
HIGH
* ISP Port for MEMC
LOW
PWM1
PI Result
HIGH
HIGH
HIGH
* SPI FLASH
SPI
PWM0 GPIO8
LOW
HIGH
PARK.S.W
22uF/16 CST PROBLEM
22uF/16 CST PROBLEM
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
M-STAR FRC DDR
BCM (BRAZIL VENUS)
DDR_DQ[22]
DDR_DQ[13]
URSA_DQ[26]
URSA_DQ[10]
DDR_DQ[15]
DDRA_A[1]
DDRB_A[9]
DDRA_A[2]
DDR_DQ[0]
DDRA_A[7]
URSA_DQ[11]
DDR_DQ[23]
DDR_DQ[18]
DDRA_A[3]
DDR_DQ[8]
DDR_DQ[17]
URSA_DQ[16]
DDR_DQ[14]
URSA_A[3]
DDRB_A[10]
DDR_DQ[3]
DDRB_A[1]
URSA_A[8]
URSA_A[7]
DDRB_A[5]
DDR_DQ[30]
DDR_DQ[24]
DDR_DQ[10]
DDR_DQ[28]
DDRA_A[6]
DDR_DQ[7]
DDRB_A[2]
DDRB_A[3]
URSA_DQ[21]
URSA_DQ[5]
DDR_DQ[20]
URSA_A[5]
DDRA_A[0]
DDRB_A[4]
DDR_DQ[4]
DDRA_A[9]
DDRB_A[0]
URSA_DQ[1]
URSA_DQ[19]
URSA_A[2]
DDRB_A[6]
URSA_DQ[15]
DDRB_A[7]
DDR_DQ[21]
DDR_DQ[11]
DDRA_A[4]
DDRB_A[4]
URSA_A[0]
DDRB_A[1]
URSA_DQ[14]
DDRA_A[12]
DDRB_A[7]
DDRB_A[11]
URSA_DQ[7]
URSA_DQ[22]
URSA_DQ[8]
DDRA_A[10]
DDR_DQ[3]
URSA_DQ[31]
URSA_A[6]
D
D
R
_
D
Q
[
0
-
1
5
]
DDR_DQ[1]
DDRA_A[11]
DDRB_A[5]
DDR_DQ[12]
DDRB_A[2]
URSA_DQ[29]
URSA_DQ[6]
URSA_A[11]
URSA_A[8]
D
D
R
A
_
A
[
0
-
1
2
]
URSA_A[4]
DDR_DQ[8]
D
D
R
B
_
A
[
0
-
1
2
]
DDR_DQ[5]
DDR_DQ[29]
URSA_DQ[2]
DDRB_A[12]
URSA_DQ[18]
DDR_DQ[27]
DDRA_A[3]
URSA_A[1]
DDRA_A[12]
URSA_A[11]
URSA_DQ[20]
DDRA_A[8]
DDRB_A[3]
DDR_DQ[16] DDR_DQ[10]
URSA_DQ[23]
DDRA_A[0]
DDR_DQ[6]
DDR_DQ[9]
DDRA_A[1]
URSA_DQ[13]
DDRA_A[8]
DDR_DQ[4]
URSA_DQ[24]
DDRA_A[2]
DDRB_A[6]
DDRB_A[8]
DDRA_A[9]
DDR_DQ[9]
DDRA_A[6]
URSA_DQ[17]
DDRB_A[9]
DDRB_A[10]
DDR_DQ[1]
DDR_DQ[31]
URSA_DQ[9]
DDRA_A[5]
URSA_DQ[30]
DDRB_A[11]
DDR_DQ[19]
DDR_DQ[2]
DDRB_A[0]
URSA_A[3]
DDR_DQ[14]
DDR_DQ[25]
URSA_DQ[3]
DDR_DQ[5]
DDRB_A[8]
DDR_DQ[2]
DDR_DQ[0]
DDR_DQ[15]
DDR_DQ[7]
DDR_DQ[26]
DDRB_A[12]
URSA_A[1]
DDRA_A[11]
URSA_DQ[4] DDRA_A[7]
DDRA_A[5]
DDR_DQ[11]
D
D
R
_
D
Q
[
1
6
-
3
1
]
DDR_DQ[13]
URSA_DQ[0]
DDRA_A[10]
URSA_DQ[12]
DDR_DQ[6] DDRA_A[4]
URSA_A[10]
DDR_DQ[12]
URSA_A[10]
URSA_DQ[27]
URSA_DQ[25]
URSA_DQ[28]
URSA_A[7]
URSA_A[5]
URSA_A[0]
URSA_A[2]
URSA_A[4]
URSA_A[6]
DDR_DQ[31]
DDR_DQ[16]
DDR_DQ[17]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
DDR_DQ[24]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[29]
DDR_DQ[30]
URSA_A[9]
URSA_A[12]
URSA_A[9]
URSA_A[12]
C
1
0
0
8
0
.
1
u
F
URSA_RASZ
URSA_WEZ 7:D1;T10
A_URSA_RASZ
C
1
0
2
0
0
.
1
u
F
+1.8V_FRC_DDR
C
1
0
2
1
0
.
1
u
F
URSA_BA0 7:D1;U12
C
1
0
2
8
0
.
1
u
F
R1015 22
R
1
0
0
3
1
K
1
%
URSA_DQM1 7:F1
R1012 56
URSA_DQS2 7:B4
R
1
0
2
3
1
K
C
1
0
4
1
0
.
1
u
F
AR1015
56
C
1
0
1
4
0
.
1
u
F
URSA_MCLK 7:B3
A_URSA_BA0 AA17
URSA_WEZ 7:D1;U11
AR1003
56
R1005 22
+1.8V_FRC_DDR
R1013 22
URSA_MCLK1 7:G1
AR1010
22
URSA_DQS1 7:F1
R1011 56
C
1
0
1
8
0
.
1
u
F
B_URSA_MCLKE Q16
URSA_BA1 7:D1;T10
R1019 56
A_URSA_CASZ
R1021 56
C
1
0
3
3
0
.
1
u
F
URSA_ODT 7:B3;X15
R
1
0
0
1
1
5
0
O
P
T
R1009 56
AR1006
22
C
1
0
0
6
0
.
1
u
F
R
1
0
2
4
1
5
0
O
P
T
A_URSA_MCLKE U10
AR1008
22
URSA_DQSB2 7:B4
C
1
0
1
6
0
.
1
u
F
C
1
0
3
8
0
.
1
u
F
C
1
0
0
7
0
.
1
u
F
C
1
0
1
5
0
.
1
u
F
C
1
0
0
1
1
0
0
0
p
F
URSA_RASZ
C
1
0
2
4
1
0
u
F
+1.8V_FRC_DDR
URSA_ODT 7:B3;Q15
C
1
0
1
0
1
0
u
F
C
1
0
3
5
0
.
1
u
F
URSA_DQSB0 7:F1
AR1007
22
C
1
0
4
5
0
.
1
u
F
B_URSA_BA1
URSA_DQM2 7:B4
C
1
0
3
2
0
.
1
u
F
C
1
0
0
9
0
.
1
u
F
B_URSA_CASZ R17
AR1005
22
A_URSA_WEZ X14
C
1
0
1
3
0
.
1
u
F
+1.8V_FRC_DDR
URSA_MCLKE 7:E1;U11
A_URSA_RASZ X17
URSA_DQ[0-31]
7:G1;AM22
R1006 22
URSA_DQSB3 7:B4
+1.8V_FRC_DDR
B_URSA_BA1
B_URSA_WEZ Q14
C
1
0
0
4
1
0
u
F
1
0
V
L1002
BLM18PG121SN1D
A_URSA_CASZ X17
C
1
0
4
4
0
.
1
u
F
R
1
0
2
2
1
K
+1.8V_MEMC
B_URSA_RASZ R17
URSA_MCLKE 7:E1;T10
URSA_DQ[0-31]
7:G1;C22
URSA_CASZ
C
1
0
4
0
0
.
1
u
F
C
1
0
3
6
0
.
1
u
F
C
1
0
4
2
0
.
1
u
F
C
1
0
3
7
0
.
1
u
F
A_URSA_BA0
C
1
0
3
4
0
.
1
u
F
URSA_DQSB1 7:F1
C
1
0
1
1
0
.
1
u
F
AR1009
22
AR1001
56
R1016 56
URSA_BA1 7:D1;U12
URSA_DQS3 7:B4
AR1004
56
R
1
0
0
2
1
K
1
%
+1.8V_FRC_DDR
C
1
0
0
2
0
.
1
u
F
C
1
0
2
5
1
0
u
F
1
0
V
R1004 22
AR1016
56
B_URSA_CASZ
B_URSA_RASZ
C
1
0
3
9
0
.
1
u
F
URSA_DQM0 7:F1
URSA_DQS0 7:F1
R1008 56
A_URSA_BA1 AA17
B_URSA_BA0
C
1
0
2
9
0
.
1
u
F
AR1011
22
C
1
0
2
6
1
0
u
F
C
1
0
3
0
0
.
1
u
F
AR1012
22
C
1
0
0
5
1
0
u
F
A_URSA_BA1
C
1
0
1
2
0
.
1
u
F
AR1018
56
URSA_BA0 7:D1;T11
R1010 56
AR1013
22
AR1017
56
C
1
0
4
3
0
.
1
u
F
URSA_CASZ
U
R
S
A
_
A
[
0
-
1
2
]
R1017 56
URSA_MCLKZ 7:B3
R1018 56
+1.8V_FRC_DDR
R1007 56
B_URSA_BA0
URSA_MCLKZ1 7:G1
C
1
0
3
1
0
.
1
u
F
C
1
0
0
3
0
.
1
u
F
C
1
0
1
7
0
.
1
u
F
C
1
0
1
9
0
.
1
u
F
B_URSA_WEZ T11
R1014 22
URSA_DQM3 7:B4
A_URSA_MCLKE Z16
AR1014
22
A_URSA_WEZ U10
B_URSA_MCLKE T11
R1020 56
C
1
0
2
7
0
.
1
u
F
C
1
0
2
2
0
.
1
u
F
C
1
0
2
3
1
0
0
0
p
F
AR1002
56
C
1
0
4
8
0
.
1
u
F
C
1
0
5
0
0
.
1
u
F
C
1
0
4
7
0
.
1
u
F
C
1
0
5
3
0
.
1
u
F
C
1
0
5
2
0
.
1
u
F
C
1
0
5
1
0
.
1
u
F
C
1
0
4
9
0
.
1
u
F
C
1
0
4
6
0
.
1
u
F
+1.8V_MEMC
+1.8V_FRC_DDR
+1.8V_FRC_DDR +1.8V_FRC_DDR
IC1001
H5PS5162FFR-S6C
J2 VREF
J8 CK
H2 VSSQ2
B7 UDQS
N8 A4
P8 A8
L1 NC4
L2 BA0
R8 NC3
K7 RAS
F8 VSSQ3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC5
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC6
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC1
N2 A3
P2 A7
H8 VSSQ1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC2
E7 VSSQ5
D8 VSSQ6
D2 VSSQ7
A7 VSSQ8
B8 VSSQ9
B2 VSSQ10
P9 VSS1
N1 VSS2
J3 VSS3
E3 VSS4
A3 VSS5
G9 VDDQ1
G7 VDDQ2
G3 VDDQ3
G1 VDDQ4
E9 VDDQ5
C9 VDDQ6
C7 VDDQ7
C3 VDDQ8
C1 VDDQ9
A9 VDDQ10
R1 VDD1
M9 VDD2
J9 VDD3
E1 VDD4
A1 VDD5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
IC1002
H5PS5162FFR-S6C
J2 VREF
J8 CK
H2 VSSQ2
B7 UDQS
N8 A4
P8 A8
L1 NC4
L2 BA0
R8 NC3
K7 RAS
F8 VSSQ3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC5
L3 BA1
J7 VSSDL
L7 CAS
F2 VSSQ4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC6
M7 A2
N7 A6
M8 A0
J1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC1
N2 A3
P2 A7
H8 VSSQ1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC2
E7 VSSQ5
D8 VSSQ6
D2 VSSQ7
A7 VSSQ8
B8 VSSQ9
B2 VSSQ10
P9 VSS1
N1 VSS2
J3 VSS3
E3 VSS4
A3 VSS5
G9 VDDQ1
G7 VDDQ2
G3 VDDQ3
G1 VDDQ4
E9 VDDQ5
C9 VDDQ6
C7 VDDQ7
C3 VDDQ8
C1 VDDQ9
A9 VDDQ10
R1 VDD1
M9 VDD2
J9 VDD3
E1 VDD4
A1 VDD5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
8 15
DDR2 1.8V By CAP - Place these Caps near Memory
PI Result
HONG.Y.H
resonance Compensation
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
BCM3556 & NAND FLASH
BCM (BRAZIL VENUS)
N
A
N
D
_
I
O
[
0
-
7
]
NAND_IO[7]
NAND_IO[6]
NAND_IO[5]
NAND_IO[4]
NAND_IO[3]
NAND_IO[2]
NAND_IO[1]
NAND_IO[0]
NAND_IO[0]
NAND_IO[1]
NAND_IO[3]
NAND_IO[2]
NAND_IO[5]
NAND_IO[4]
NAND_IO[7]
NAND_IO[6]
R
1
8
0
4
.
7
K
R
1
9
4
4
.
7
K
COMP2_DET 14:A5
SDA3_3.3V 7:B6
A_DIM I3;4:A6
BCM_AVC_DEBUG_TX2 G5
R
1
9
3
4
.
7
K
NAND_IO[0-7]
R
1
7
6
4
.
7
K
OPT
R
1
7
0
4
.
7
K
NAND_REb C3
R182 22
NAND_WEb E5
NAND_REb
E6
VREG_CTRL
R196 0 OPT
NAND_ALE E6
BCM_AVC_DEBUG_RX1 G6
FLASH_WP_1
D3.3V
BCM_AVC_DEBUG_TX1 G6
R198 0 OPT
SDA0_3.3V 14:A6
R
1
1
6
4
.
7
K
SDA2_3.3V B5;12:F3
C115
0.1uF
BLUETOOTH_RESET I3;14:I3
R
1
8
4
4
.
7
K
BCM_AVC_DEBUG_TX2 C7
R174 22
RF_SWITCH 14:A6
BCM_AVC_DEBUG_RX2 C6
BCM_RX
BCM_TX
NAND_ALE C2
BCM_AVC_DEBUG_RX2 G5
D3.3V
R175 22
R
1
3
6
4
.
7
K
PWM_DIM I3;4:A5;7:I5
C114
0.1uF
SDA1_3.3V 3:D3;2:AH5
R186 22
R109 0 OPT
GAIN_SWITCH 14:A6
D3.3V
R179 22
SIDE_CVBS_DET
D3.3V
NAND_WEb C2
SCL3_3.3V 7:B6
R181 22
SCL0_3.3V 14:A6
R105
22
BCM_AVC_DEBUG_RX1 C7
R185 22
C136 10uF
6.3V
NAND_CEb
E6
NAND_CLE E5
R
1
7
7
4
.
7
K
OPT
NAND_CEb C3
R
1
8
3
4
.
7
K
D3.3V
R
1
7
1
4
.
7
K
SCL1_3.3V 3:D3;2:AH5
NAND_CLE C2
R
1
8
7
4
.
7
K
NAND_IO[0-7]
NAND_RBb E5
P100
GIL-G-06-S3T2
OPT
1
2
3
4
5
6
TUNER_RESETb I3;14:A6
R
1
9
2
4
.
7
K
D3.3V
R178 22
SCL2_3.3V B5;12:F3
FRC_RESET 7:H2
AV1_CVBS_DET 14:A5
R197 0 OPT
R161 0
NAND_RBb C3
COMP1_DET 14:A6
AUDIO_M_CLK 3:C4
Q101
KRC103S
E
B
C
BCM_AVC_DEBUG_TX1 C7
DSUB_DET
R189 0
OPT
R195 0
OPT
R103 100
AMP_RST
R2005 100 OPT
R2004 100
R2008 100
R2009 100
PWM_DIM G7;4:A5;7:I5
R
2
0
1
1
2
.
7
K
R
2
0
1
4
2
.
7
K
HDMI_HPD_IN
A_DIM G6;4:A6
VREG_CTRL
BLUETOOTH_RESET
AMP_RST G7;12:I4;3:C5
R
2
0
1
5
2
.
7
K
R
2
0
1
3
2
.
7
K
R
2
0
1
6
2
.
7
K
R
2
0
1
0
2
.
7
K
D3.3V
HDMI_HPD_IN
D3.3V
C416
0.1uF
SDA2_3.3V I4;12:F3
D3.3V
IC400
KIA7029AF
2
G
3 O 1 I
R
4
1
9
4
.
7
K
SCL2_3.3V I4;12:F3
R
4
2
2
4
.
7
K
R2003
0
OPT
IC403
AT24C512BW-SH-T
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
RESET
10:I2;12:I5
R412
22
R411
22
D3.3V
SYS_RESETb
10:E4
NAND_IO[5]
E3;E6
NAND_IO[6]
E3;E6
NAND_IO[2]
E3;E6
D3.3V D3.3V
NAND_IO[0]
E3;E6
NAND_IO[3]
E3;E6
D3.3V
BIT_SEL
R2018 100 OPT
POWER_DET
12:B3;12:I4
R117
33
D3.3V
D3.3V
NAND_IO[4]
E3;E6
R
1
9
1
2
.
7
K
R
2
0
4
0
2
.
7
K
R
1
3
1
2
.
7
K
D3.3V
TUNER_RESETb G7;14:A6
R3016
4.7K
R
4
0
9
9
1
0
C400
10uF
R
4
1
0
1
0
K
IC101
NAND01GW3A2CN6E
26
NC_17
27
NC_18
28
NC_19
29
I/O0
30
I/O1
31
I/O2
32
I/O3
33
NC_20
34
NC_21
35
NC_22
36
VSS_2
37
VDD_2
38
NC_23
39
NC_24
40
NC_25
41
I/O4
42
I/O5
43
I/O6
44
I/O7
45
NC_26
46
NC_27
47
NC_28
48
NC_29
17
AL
3
NC_3
6
NC_6
16
CL
15
NC_10
14
NC_9
13
VSS_1
12
VDD_1
11
NC_8
10
NC_7
9
E
8
R
7
RB
4
NC_4
5
NC_5
25
NC_16
24
NC_15
23
NC_14
2
NC_2
22
NC_13
21
NC_12
1
NC_1
20
NC_11
19
WP
18
W
LVDS_SEL
R3030 100
OPT
R199 22
OPT
R2002 22
OPT
R2001 22
OPT
DDC_SCL I3;14:A6
DDC_SDA I3;14:A6
R2024 22
R160 22
R102 22
R
2
0
3
2
2
.
7
K
O
P
T
R
3
1
7
2
.
7
K
R
2
0
3
3
2
.
7
K
R
3
1
6
2
.
7
K
R
3
1
5
2
.
7
K
O
P
T
R
3
2
1
2
.
7
K
O
P
T
R
2
0
2
9
2
.
7
K
O
P
T
R
3
1
4
2
.
7
K
R
2
0
3
0
2
.
7
K
R
2
0
3
1
2
.
7
K
IC100
BCM3556
GPIO_00
N26
GPIO_01
L26
GPIO_02
N25
GPIO_03
L25
GPIO_04
K27
GPIO_05
K28
GPIO_06
K24
GPIO_07
K26
GPIO_08
K25
GPIO_09
AA27
GPIO_10
AA28
GPIO_11
AA26
GPIO_12
L1
GPIO_13
L3
GPIO_14
L2
GPIO_15
Y25
GPIO_16
Y26
GPIO_17
M27
GPIO_18
AA25
GPIO_19
R25
GPIO_20
N28
GPIO_21
N27
GPIO_22
AH18
GPIO_23
P23
GPIO_24
M23
GPIO_25
AD19
GPIO_26
AE19
GPIO_27
M4
GPIO_28
M5
GPIO_29
L23
GPIO_30
Y28
GPIO_31
Y27
GPIO_32
G2
GPIO_33
G3
GPIO_34
G5
GPIO_35
G6
GPIO_36
G4
GPIO_37
L24
GPIO_38
P25
GPIO_39
L5
GPIO_40
K4
GPIO_41
K1
GPIO_42
L27
GPIO_43
M26
GPIO_44
N23
GPIO_45
R28
GPIO_46
R27
GPIO_47
R26
GPIO_48
P28
GPIO_49
P27
GPIO_50
K6
GPIO_51
K5
GPIO_52
P26
GPIO_53
M3
GPIO_54
M2
GPIO_55
M1
GPIO_56
L4
GPIO_57
L6
SGPIO_00
W27
SGPIO_01
W28
SGPIO_02
W26
SGPIO_03
W25
SGPIO_04
J2
SGPIO_05
J1
SGPIO_06
K3
SGPIO_07
K2
EBI_ADDR3
J23
EBI_ADDR4
J24
EBI_ADDR2
H25
EBI_ADDR1
H24
EBI_ADDR0
H23
EBI_ADDR5
J25
EBI_ADDR6
F26
EBI_ADDR8
H28
EBI_ADDR9
J26
EBI_ADDR13
H27
EBI_ADDR12
G26
EBI_ADDR11
J27
EBI_ADDR10
J28
EBI_ADDR7
F27
EBI_TAB
G24
EBI_WE1B
H26
EBI_CLK_IN
G27
EBI_CLK_OUT
G28
EBI_RWB
K23
EBI_CS0B
G25
NAND_DATA0
U24
NAND_DATA1
T26
NAND_DATA2
T27
NAND_DATA3
U26
NAND_DATA4
U27
NAND_DATA5
V26
NAND_DATA6
V27
NAND_DATA7
V28
NAND_CS0B
T24
NAND_ALE
R23
NAND_REB
T23
NAND_CLE
T25
NAND_WEB
R24
NAND_RBB
U25
SF_MISO
W24
SF_MOSI
U23
SF_SCK
V23
SF_CSB
V24
C3024
4700pF
R408
330
R2025
0
M
D
S
6
1
8
8
7
7
0
2
GAS1
G
A
S
1
_
6
T
M
D
S
6
1
8
8
7
7
0
2
GAS5
G
A
S
5
_
6
T
M
D
S
6
1
8
8
7
7
0
2
GAS4
G
A
S
4
_
6
T
M
D
S
6
1
8
8
7
7
0
2
GAS3
G
A
S
3
_
6
T
M
D
S
6
1
8
8
7
7
0
2
GAS2
G
A
S
2
_
6
T
M
D
S
6
1
8
8
7
7
0
3
GAS2-*1
G
A
S
2
_
7
T
M
D
S
6
1
8
8
7
7
0
3
GAS1-*1
G
A
S
1
_
7
T
M
D
S
6
1
8
8
7
7
0
3
GAS5-*1
G
A
S
5
_
7
T
M
D
S
6
1
8
8
7
7
0
3
GAS3-*1
G
A
S
3
_
7
T
M
D
S
6
1
8
8
7
7
0
3
GAS4-*1
G
A
S
4
_
7
T
15
Open Drain
9
SF_MISO
SF_MOSI
SF_SCK
SF_CSB
* I2C MAP
* I2C_0 : TUNER
* I2C_1 : Audio amp, HDMI S/W
* I2C_2 : NVRAM,Micom
* I2C_3 : FRC
Hot Plug input pin should be feeded over 5mA.
BCM Recommend
NVRAM
RESET
NAND_IO[0] : Flash Select (1)
0 : Boot From Serial Flash
1 : Boot From NAND Flash
NAND_IO[1] : NAND Block 0 Write (DNS)
0 : Enable Block 0 Write
1 : Disable Block 0 Write
NAND_IO[3:2] : NAND ECC (10)
00 : No ECC
01 : 1 ECC Bit
10 : 4 ECC Bit
11 : 8 ECC Bit
NAND_IO[4] : CPU Endian (0)
0 : Little Endian
1 : Big Endian
NAND_IO[6:5] : Xtal Bias Control (1, DNS)
00 : 1.2mA
01 : 1.8mA
10 : 2.4mA (Recommand)
11 : 3.0mA
Boot Strap
* NAND FLASH MEMORY 1Gbit (128M)
JANG.J.H
IF FUNDMENTAL IS USED => LOW
IF DIP IS USED => HIGH
SMD Gasket Option
32/42/55 - 6T SMD Gasket
47 - 7T SMD Gasket
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
BCM3556 AUD_IN/LVDS
2009.03.23 BCM (BRAZIL VENUS)
54MHz_XTAL_N
54MHz_XTAL_P
C
2
1
2
4
.
7
u
F
L202
BLM18PG121SN1D
C213
0.01uF
A3.3V A2.5V
C
2
1
9
0
.
1
u
F
C
2
1
4
0
.
1
u
F
R220 560
A1.2V
C215
0.1uF
C
2
2
3
0
.
1
u
F
JP201
D3.3V
C
2
0
0
4
.
7
u
F
R
2
0
1
1
.
5
K
JP202
JP200
R
2
0
0
1
.
5
K
JP203
USB_DM2
L200
BLM18PG121SN1D
A2.5V
C
2
0
9
0
.
1
u
F
R209
3.9K
C
2
0
8
4
.
7
u
F
C201
100pF
R210
120
USB_DM1
A1.2V
C
2
0
7
0
.
1
u
F
C
2
0
3
0
.
1
u
F
C
2
0
2
0
.
1
u
F
USB_DP1
A3.3V
USB_DP2
A1.2V
R218
240
A2.5V
R219 1K
C222
0.1uF
A2.5V
C217
10uF
C
3
0
0
5
4
.
7
u
F
C228
10uF
OPT
C
2
9
5
0
.
1
u
F
A2.5V
C
2
4
2
4
.
7
u
F
A1.2V
C
2
3
6
0
.
1
u
F
C
2
3
9
0
.
1
u
F
A1.2V
C
2
1
8
0
.
1
u
F
54MHz_XTAL_P I2
C
3
0
0
8
0
.
1
u
F
54MHz_XTAL_N I2
A2.5V
A1.2V
L203
BLM18PG121SN1D
C235
4.7uF
C233
0.1uF
D3.3V
A2.5V
D3.3V
C234
0.1uF
SYS_RESETb
9:B7
C231
10uF
L204
BLM18PG121SN1D
A1.2V
C
2
4
1
4
.
7
u
F
C
2
4
0
4
.
7
u
F
A1.2V
L207
BLM18PG121SN1D
C
2
3
7
0
.
1
u
F
R222 1K
R223 1K
R221
4.7K
L201
BLM18PG121SN1D
LVDS_TX_0_DATA3_P 7:E7
LVDS_TX_0_DATA0_P 7:E7
LVDS_TX_1_DATA3_N 7:D7
LVDS_TX_1_DATA1_P 7:D7
LVDS_TX_0_DATA1_N 7:E7
LVDS_TX_0_DATA1_P 7:E7
LVDS_TX_1_CLK_P 7:D7
LVDS_TX_0_DATA2_N 7:E7
LVDS_TX_1_CLK_N 7:D7
LVDS_TX_0_DATA4_P 7:E7
LVDS_TX_1_DATA4_P 7:D7
LVDS_TX_0_DATA2_P 7:E7
LVDS_TX_1_DATA3_P 7:D7
LVDS_TX_0_CLK_N 7:E7
LVDS_TX_0_DATA4_N 7:E7
LVDS_TX_0_CLK_P 7:E7
LVDS_TX_1_DATA4_N 7:D7
LVDS_TX_1_DATA1_N 7:D7
LVDS_TX_0_DATA3_N 7:E7
LVDS_TX_1_DATA0_N 7:D7
LVDS_TX_1_DATA0_P 7:D7
LVDS_TX_1_DATA2_P 7:D7
LVDS_TX_1_DATA2_N 7:D7
LVDS_TX_0_DATA0_N 7:E7
R204 51
COMP2_INCM 14:A5
AV1_INCM 14:A5
COMP1_L_IN 14:A6
R233 51
R231 51
AV1_L_IN 14:A5
R230 51
R234 51
R229 51
R232 51
R214 51
COMP1_R_IN 14:A6
COMP1_INCM 14:A6
AV1_R_IN 14:A5
SIDE_L_IN 14:A4
COMP2_L_IN 14:A5
R228 51
PC_INCM 14:A3
SIDE_R_IN 14:A4
PC_R_IN 14:A3
SIDE_INCM 14:A4
COMP2_R_IN 14:A5
PC_L_IN 14:A3
R215 51
C
2
3
8
0
.
1
u
F
USB_CTL1
USB_OCD1
D3.3V
R235
2.7K
TU_SCLK
TU_SYNC
TU_SDATA
P200
TJC2508-4A
1
2
3
4
R
2
3
70
R
2
3
60
A1.2V
R240
390
OPT
R241 0
OPT
R242 0
OPT
R226
4.7K
R225
4.7K
OPT
R227
4.7K
R224
4.7K
OPT
R
3
0
2
7
6
0
4
L
8
0
1
4
1
0
0
8
L
S
-
2
7
2
X
J
L
C
C
3
0
1
2
3
3
p
F
IC100
BCM3556
PKT0_CLK
D23
PKT0_DATA
C24
PKT0_SYNC
B26
RMX0_CLK
A25
RMX0_DATA
B25
RMX0_SYNC
A26
POD2CHIP_MCLKI
G23
POD2CHIP_MDI0
D25
POD2CHIP_MDI1
D24
POD2CHIP_MDI2
C25
POD2CHIP_MDI3
E27
POD2CHIP_MDI4
E26
POD2CHIP_MDI5
D28
POD2CHIP_MDI6
D27
POD2CHIP_MDI7
D26
POD2CHIP_MISTRT
E23
POD2CHIP_MIVAL
E24
CHIP2POD_MCLKO
F25
CHIP2POD_MDO0
C27
CHIP2POD_MDO1
C26
CHIP2POD_MDO2
B28
CHIP2POD_MDO3
B27
CHIP2POD_MDO4
A27
CHIP2POD_MDO5
F24
CHIP2POD_MDO6
F23
CHIP2POD_MDO7
E25
CHIP2POD_MOSTRT
C28
CHIP2POD_MOVAL
A28
VDAC_AVDD2P5
AC18
VDAC_AVDD1P2
AF20
VDAC_AVDD3P3_1
AG20
VDAC_AVDD3P3_2
AG21
VDAC_AVSS_1
AF19
VDAC_AVSS_2
AD20
VDAC_AVSS_3
AE20
VDAC_RBIAS
AH22
VDAC_1
AH20
VDAC_2
AG19
VDAC_VREG
AH21
BSC_S_SCL
M25
BSC_S_SDA
M24
USB_AVSS_1
R6
USB_AVSS_2
T6
USB_AVSS_3
R7
USB_AVSS_4
T7
USB_AVSS_5
T8
USB_AVDD1P2
R3
USB_AVDD1P2PLL
U3
USB_AVDD2P5
T4
USB_AVDD2P5REF
T3
USB_AVDD3P3
R4
USB_RREF
U4
USB_DM1
V1
USB_DP1
V2
USB_DM2
U1
USB_DP2
U2
USB_MONCDR
T5
USB_MONPLL
R5
USB_PWRFLT_1
R1
USB_PWRFLT_2
R2
USB_PWRON_1
T2
USB_PWRON_2
T1
EPHY_VREF
P6
EPHY_RDAC
P5
EPHY_RDN
P3
EPHY_RDP
P2
EPHY_TDN
N3
EPHY_TDP
N2
EPHY_AVDD1P2
P1
EPHY_AVDD2P5
P4
EPHY_PLL_VDD1P2
N4
EPHY_AGND_1
N1
EPHY_AGND_2
N5
EPHY_AGND_3
P7
AUDMX_LEFT1
AE6
AUDMX_RIGHT1
AD7
AUDMX_INCM1
AF6
AUDMX_LEFT2
AH4
AUDMX_RIGHT2
AG5
AUDMX_INCM2
AG4
AUDMX_LEFT3
AG6
AUDMX_RIGHT3
AF7
AUDMX_INCM3
AE7
AUDMX_LEFT4
AH5
AUDMX_RIGHT4
AG7
AUDMX_INCM4
AH6
AUDMX_LEFT5
AD8
AUDMX_RIGHT5
AF8
AUDMX_INCM5
AE8
AUDMX_LEFT6
AH7
AUDMX_RIGHT6
AH8
AUDMX_INCM6
AG8
AUDMX_AVSS_1
AF5
AUDMX_AVSS_2
AB9
AUDMX_AVSS_3
AA10
AUDMX_AVSS_4
AB10
AUDMX_AVSS_5
AA11
AUDMX_AVSS_6
AB11
AUDMX_LDO_CAP
AC8
AUDMX_AVDD2P5
AE5
LVDS_TX_0_DATA0_P
B4
LVDS_TX_0_DATA0_N
A4
LVDS_TX_0_DATA1_P
C6
LVDS_TX_0_DATA1_N
B6
LVDS_TX_0_DATA2_P
B3
LVDS_TX_0_DATA2_N
A3
LVDS_TX_0_DATA3_P
A1
LVDS_TX_0_DATA3_N
A2
LVDS_TX_0_DATA4_P
D5
LVDS_TX_0_DATA4_N
D6
LVDS_TX_0_CLK_P
C5
LVDS_TX_0_CLK_N
B5
LVDS_TX_1_DATA0_P
B1
LVDS_TX_1_DATA0_N
B2
LVDS_TX_1_DATA1_P
C2
LVDS_TX_1_DATA1_N
C3
LVDS_TX_1_DATA2_P
D1
LVDS_TX_1_DATA2_N
D2
LVDS_TX_1_DATA3_P
E1
LVDS_TX_1_DATA3_N
E2
LVDS_TX_1_DATA4_P
E3
LVDS_TX_1_DATA4_N
E4
LVDS_TX_1_CLK_P
D3
LVDS_TX_1_CLK_N
D4
LVDS_PLL_VREG
F5
LVDS_TX_AVDDC1P2
F1
LVDS_TX_AVDD2P5_1
F4
LVDS_TX_AVDD2P5_2
F2
LVDS_TX_AVSS_1
C1
LVDS_TX_AVSS_2
F3
LVDS_TX_AVSS_3
C4
LVDS_TX_AVSS_4
A5
LVDS_TX_AVSS_5
E5
LVDS_TX_AVSS_6
E6
LVDS_TX_AVSS_7
D7
LVDS_TX_AVSS_8
E7
LVDS_TX_AVSS_9
F7
LVDS_TX_AVSS_10
G7
LVDS_TX_AVSS_11
H7
CLK54_AVDD1P2
AD27
CLK54_AVDD2P5
AD28
CLK54_AVSS
AD26
CLK54_XTAL_N
AC26
CLK54_XTAL_P
AC27
CLK54_MONITOR
AE25
PM_OVERRIDE
Y23
VCXO_AGND_1
AA23
VCXO_AGND_2
AB24
VCXO_AGND_3
AC24
VCXO_AVDD1P2
AF25
VCXO_PLL_AUDIO_TESTOUT
AF24
RESET_OUTB
P24
RESETB
F6
NMIB
N24
TMODE_0
J5
TMODE_1
J4
TMODE_2
J6
TMODE_3
J3
SPI_S_MISO
V25
POR_OTP_VDD2P5
AH3
POR_VDD1P2
AB8
EJTAG_TCK
H4
EJTAG_TDI
H3
EJTAG_TDO
H2
EJTAG_TMS
H1
EJTAG_TRSTB
G1
EJTAG_CE0
H6
EJTAG_CE1
H5
PLL_MAIN_AVDD1P2
AB26
PLL_MAIN_AGND
AC25
PLL_MAIN_MIPS_EREF_TESTOUT
AB27
PLL_RAP_AVD_TESTOUT
M6
PLL_RAP_AVD_AVDD1P2
N6
PLL_RAP_AVD_AGND
N7
BYP_CPU_CLK
AA24
BYP_DS_CLK
Y24
BYP_SYS216_CLK
AE24
BYP_SYS175_CLK
AD25
R212
22
R211
22
C229
12pF
C230
12pF
X
9
0
3
5
4
M
H
z
2
1
3
C4014
0.47uF
R
4
0
0
1
3
4
R
4
0
0
7
3
4
COMP1_VID_INCM 3:T23
TU_CVBS_INCM
3:T25
COMP2_INCM
3:T22 R4010
5.1
R4009
5.1
C4015
0.47uF
B_VID_INCM
3:T15
R4011
5.1
R4012
5.1
R4008
5.1
C4006 0.1uF
COMP2_VID_INCM
3:T21
C4000 0.1uF
C4001 0.1uF
R
4
0
0
6
3
4
SIDE_CVBS_INCM
3:T19
R
4
0
0
5
3
4
C4004 0.1uF
R_VID_INCM
3:T15
C4013
0.47uF
R
4
0
0
4
3
4
R
4
0
0
0
3
4
AV1_INCM 3:T20
C4005 0.1uF
C4007 0.1uF
R
4
0
0
2
3
4
R
4
0
0
3
3
4
C4003 0.1uF
C4016
0.47uF
SIDE_INCM
3:T18
C4002 0.1uF
COMP1_INCM
3:T24
G_VID_INCM
3:T15
PC_INCM
3:T14
C4017
0.47uF
AV1_CVBS_INCM
3:T19
C4010
0.15uF
C4011
0.15uF
C4008
0.15uF
C4009
0.15uF
C4012
0.15uF
C224 15nF
C211 15nF
C226 15nF
C221 15nF
C206 15nF
C225 15nF
C220 15nF
C232 15nF
C210 15nF
C227 15nF
C
2
7
4
4
7
n
F
C
3
0
0
1
4
7
n
F
C
2
9
8
4
7
n
F
C
3
0
0
7
4
7
n
F
C
3
0
0
4
4
7
n
F
C
2
7
7
4
7
n
F
C
3
0
0
2
4
7
n
F
C
2
9
6
4
7
n
F
C
3
0
0
3
4
7
n
F
C
2
7
9
4
7
n
F
10 15
Route INCM between associated
left and right signals of same channel
The INCM trace ends at the
same point where the connector
ground connects to the board ground
(thru-hole connector pin).
Place test points, resistors
near audio connector.
Connect the other side of
the resistor to GND as close
as possible to the ground
connection of the associated
audio connector.
54MHz X-TAL
R220 : BCM recommened resistor 562 ohm
BROAD BAND STUDIO
JANG.J.H
When usding FUNDMENTAl then series R = 0 ohm and CL = 8 pF
MNT OUT FOR BCM
When usding Dip-type X-tal then series R = 22 ohm and CL = 12 pF
INCM
CONNECT NEAR BCM CHIP
A B C D E F G H I J K
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
BCM3556 VIDEO IN
BRAZIL VENUS
B_VID_INCM 14:A3
A2.5V
L105
BLM18PG121SN1D
BCM_I2S_BIT_CLK 3:D3
A2.5V
A3.3V
R128
0
C125 0.1uF
C133 0.1uF
HDMI0_RX2-_BCM 2:AC18
C140
4.7uF
L103
BLM18PG121SN1D
HDMI0_RX0-_BCM 2:AB18
A1.2V
L107
BLM18PG121SN1D
R137
10K
C
1
0
5
1
0
p
F
O
P
T
L110
BLM18PG121SN1D
COMP1_Y_IN 14:A6
C156
0.1uF
A1.2V
DSUB_B 14:A3
RGB_VSYNC 14:A3
C130 0.1uF
C163
10uF
A1.2V
R_VID_INCM 14:A4
C112
0.1uF
COMP2_VID_INCM 14:A5
C146
4.7uF
R172 0
OPT
C155
0.1uF
HDMI0_RX1+_BCM 2:AC18
C
1
0
3
1
0
p
F
C154
0.1uF
COMP2_Y_IN 14:A5
R166 0
OPT
BCM_I2S_DATA_OUT
3:D3
HDMI0_RXC-_BCM 2:AA18
C116
4.7uF
L102
BLM18PG121SN1D
A2.5V
HDMI0_RX2+_BCM 2:AD18
COMP1_VID_INCM 14:A6
C110 0.1uF
R169 0
OPT
C165
10uF
SIDE_CVBS_INCM 14:A5
BCM_I2S_WORD_CLK 3:D3
A1.2V
G_VID_INCM 14:A3
C134 0.1uF
HDMI_HPD_IN_5MA G5
COMP1_Pb_IN 14:A6
AV1_CVBS_IN 14:A5
C144
0.1uF
C131 0.1uF
D3.3V
A1.2V
L106
BLM18PG121SN1D
R165 0
OPT
C160
0.1uF
COMP2_Pb_IN 14:A5
C
1
0
1
1
0
p
F
C119
0.1uF
DSUB_G 14:A4
R163 0
OPT
R
1
4
6
1
0
K
C111
0.1uF
C164
10uF
R162 0
OPT
C
1
0
4
1
0
p
F
O
P
T
C150
0.1uF
COMP1_Pr_IN 14:A5
SIDE_CVBS_IN 14:A5
AV1_CVBS_INCM 14:A5
C157
0.1uF
C113
0.1uF
C124 0.1uF
C151
0.01uF
C145
4.7uF
HDMI0_RX1-_BCM 2:AC18
C117
1000pF
C161
0.1uF
R167 0
OPT
C158
1000pF
C129 0.1uF
A2.5V
L108
BLM18PG121SN1D
C149
0.01uF
C162
10uF
TU_CVBS_INCM 14:A6
A1.2V
RGB_HSYNC 14:A3
SPDIF_OUT14:A3
C153
0.1uF
C132 0.1uF
C135 0.1uF
C127 0.1uF
R168 0
OPT
R153 499
C152
0.01uF
C
1
0
2
1
0
p
F
R152 499
C120
1000pF
C147
0.01uF
HDMI0_RXC+_BCM 2:AB18
TU_CVBS_IN 14:A6
C123
0.01uF
C159
1000pF
C106
0.1uF
R164 0
OPT
A2.5V
COMP2_Pr_IN 14:A5
L109
BLM18PG121SN1D
C128 0.1uF
R139
12K
A2.5V
A3.3V
C148
0.01uF
C122
4.7uF
C166
10uF
HDMI0_RX0+_BCM 2:AB18
TU_SIF 14:A6
L104
BLM18PG121SN1D
C118
0.01uF
DSUB_R 14:A4
A2.5V
C121
0.1uF
R
1
1
9
7
5
R
1
1
8
7
5
R
1
1
5
7
5
R141 75
OPT
+5.0V
R
2
0
3
7
1
0
K
O
P
T
R
2
0
3
8
1
0
K
1
0
K
R
2
0
3
9
C3006
0.1uF
16V
HDMI_SCL 2:AA19
HDMI_SDA 2:AA19
R157 0
R158 0
Q906
ISA1530AC1
E
B
C
HDMI_HPD_IN 9:G4;9:I3
HDMI_HPD_IN_5MA
A2.5V A2.5V
R
3
0
4
1
2
7
0
O
P
T
R
3
0
4
2
4
7
0
O
P
T
IC100
BCM3556
DS_AGCI_CTL
AG28
DS_AGCT_CTL
AH28
EDSAFE_AVSS_1
AA21
EDSAFE_AVSS_2
AB22
EDSAFE_AVSS_3
AF26
EDSAFE_AVSS_4
AF27
EDSAFE_AVSS_5
AF28
EDSAFE_AVDD2P5
AG27
EDSAFE_DVDD1P2
AE26
EDSAFE_IF_N
AE28
EDSAFE_IF_P
AE27
PLL_DS_AGND
AD24
PLL_DS_AVDD1P2
AB19
PLL_DS_TESTOUT
AB25
SD_V5_AVDD1P2
AB18
SD_V5_AVDD2P5
AC17
SD_V5_AVSS
AB17
SD_V1_AVDD1P2
AD14
SD_V1_AVDD2P5
AD16
SD_V1_AVSS_1
AB15
SD_V1_AVSS_2
AC15
SD_V2_AVDD1P2
AD13
SD_V2_AVDD2P5
AE13
SD_V2_AVSS_1
AC13
SD_V2_AVSS_2
AB14
SD_V2_AVSS_3
AC14
SD_V3_AVDD1P2
AC12
SD_V3_AVDD2P5
AD12
SD_V3_AVSS_1
AB13
SD_V3_AVSS_2
AA14
SD_V4_AVDD1P2
AC11
SD_V4_AVDD2P5
AD11
SD_V4_AVSS
AB12
SD_R
AD10
SD_INCM_R
AC10
SD_G
AE9
SD_INCM_G
AF9
SD_B
AH9
SD_INCM_B
AG9
SD_Y1
AG15
SD_PR1
AE15
SD_PB1
AF15
SD_INCM_COMP1
AH15
SD_Y2
AG16
SD_PR2
AF16
SD_PB2
AH17
SD_INCM_COMP2
AH16
SD_Y3
AG14
SD_PR3
AE14
SD_PB3
AF14
SD_INCM_COMP3
AH14
SD_L1
AH10
SD_C1
AG10
SD_INCM_LC1
AE10
SD_L2
AE11
SD_C2
AF11
SD_INCM_LC2
AH11
SD_L3
AH13
SD_C3
AE12
SD_INCM_LC3
AF12
SD_CVBS1
AD9
SD_CVBS2
AG11
SD_CVBS3
AG12
SD_CVBS4
AF13
SD_INCM_CVBS1
AC9
SD_INCM_CVBS2
AF10
SD_INCM_CVBS3
AH12
SD_INCM_CVBS4
AG13
SD_SIF1
AF17
SD_INCM_SIF1
AG17
SD_FB
AD15
SD_FS
AE16
SD_FS2
AE17
PLL_VAFE_AVDD1P2
AB16
PLL_VAFE_AVSS
AA15
PLL_VAFE_TESTOUT
AC16
RGB_HSYNC
AG3
RGB_VSYNC
AF4
I2S_CLK_IN
AE18
I2S_CLK_OUT
AF18
I2S_DATA_IN
AD17
I2S_DATA_OUT
AH19
I2S_LR_IN
AD18
I2S_LR_OUT
AG18
AUD_LEFT0_N
AG26
AUD_LEFT0_P
AH26
AUD_AVDD2P5_0
AF23
AUD_AVSS_0_1
AA20
AUD_AVSS_0_2
AB21
AUD_AVSS_0_3
AC22
AUD_AVSS_0_4
AC23
AUD_AVSS_0_5
AD23
AUD_RIGHT0_N
AH25
AUD_RIGHT0_P
AG25
AUD_LEFT1_N
AH23
AUD_LEFT1_P
AG23
AUD_RIGHT1_N
AG24
AUD_RIGHT1_P
AH24
AUD_AVDD2P5_1
AE22
AUD_AVSS_1_1
AB20
AUD_AVSS_1_2
AC21
AUD_AVSS_1_3
AE23
AUD_LEFT2_N
AF21
AUD_LEFT2_P
AE21
AUD_RIGHT2_N
AF22
AUD_RIGHT2_P
AG22
AUD_AVDD2P5_2
AD21
AUD_AVSS_2_1
AC20
AUD_AVSS_2_2
AD22
AUD_SPDIF
AH2
SPDIF_AVDD2P5
AC6
SPDIF_AVSS
AE4
SPDIF_IN_N
AF3
SPDIF_IN_P
AH1
HDMI_RX_0_CEC_DAT
AG1
HDMI_RX_0_HTPLG_IN
AA6
HDMI_RX_0_HTPLG_OUT
AA5
HDMI_RX_0_DDC_SCL
AB3
HDMI_RX_0_DDC_SDA
Y6
HDMI_RX_0_RESREF
AC4
HDMI_RX_0_CLK_N
AC1
HDMI_RX_0_CLK_P
AC2
HDMI_RX_0_DATA0_N
AD1
HDMI_RX_0_DATA0_P
AD2
HDMI_RX_0_DATA1_N
AE1
HDMI_RX_0_DATA1_P
AE2
HDMI_RX_0_DATA2_N
AF1
HDMI_RX_0_DATA2_P
AF2
HDMI_RX_0_VDD3P3
AD3
HDMI_RX_0_VDD1P2
AE3
HDMI_RX_0_VDD2P5
AC3
HDMI_RX_0_AVSS_1
AD4
HDMI_RX_0_AVSS_2
AB5
HDMI_RX_0_AVSS_3
AB6
HDMI_RX_0_AVSS_4
AG2
HDMI_RX_0_AVSS_5
AB4
HDMI_RX_0_AVSS_6
AA7
HDMI_RX_0_PLL_AVSS
Y8
HDMI_RX_0_PLL_DVDD1P2
AC5
HDMI_RX_0_PLL_DVSS
W8
HDMI_RX_1_CEC_DAT
AA3
HDMI_RX_1_HTPLG_IN
V4
HDMI_RX_1_HTPLG_OUT
U6
HDMI_RX_1_DDC_SCL
V5
HDMI_RX_1_DDC_SDA
V3
HDMI_RX_1_RESREF
W4
HDMI_RX_1_CLK_N
W2
HDMI_RX_1_CLK_P
W3
HDMI_RX_1_DATA0_N
Y1
HDMI_RX_1_DATA0_P
Y2
HDMI_RX_1_DATA1_N
AA2
HDMI_RX_1_DATA1_P
AA1
HDMI_RX_1_DATA2_N
AB2
HDMI_RX_1_DATA2_P
AB1
HDMI_RX_1_VDD3P3
Y3
HDMI_RX_1_VDD1P2
Y4
HDMI_RX_1_VDD2P5
W5
HDMI_RX_1_AVSS_1
W1
HDMI_RX_1_AVSS_2
U5
HDMI_RX_1_AVSS_3
W6
HDMI_RX_1_AVSS_4
U7
HDMI_RX_1_AVSS_5
V7
HDMI_RX_1_AVSS_6
W7
HDMI_RX_1_AVSS_7
U8
HDMI_RX_1_AVSS_8
V8
HDMI_RX_1_AVSS_9
Y5
HDMI_RX_1_PLL_AVSS
V6
HDMI_RX_1_PLL_DVDD1P2
AA4
HDMI_RX_1_PLL_DVSS
Y7
R
2
0
3
5
0
R2036
1K
R188 10K
R
1
2
0
9
1
R
1
4
0
9
1
R
1
2
9
9
1
R
1
3
5
9
1
R
1
3
8
9
1
R
1
2
7
9
1
R142 91
OPT
R143 91
OPT
R3055
240
A2.5V
R4020
10K
R
4
0
2
1
1
2
K C4020
0.1uF
R
3
0
5
6
1
2
0
TP107
TP101
TP102
TP103
TP104
TP105
TP106
TP108
TP109
TP110
TP111
TP112
TP113
11 15
JANG.J.H.
CONNECT NEAR BCM CHIP
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
MICOM
BCM (BRAZIL VENUS)
UCOM_RX 14:H2
R
4
6
0
6
8
K
O
P
T
C410
0.1uF
16V
GND
GND
C414
0.1uF
16V
DDC_SDA 9:G7;14:A4
R417 22
EDID_WP 14:A4
R447 4.7K
IR 14:A3;14:E6
C402
0.1uF
16V
R
4
2
8
1
5
K
R
4
4
4
1
0
0
O
P
T
R465 100 GND
R404
220
O
P
C
_
E
N
7
:
I
5
R
4
6
1
6
.
8
K
R
4
4
1
1
0
0
UCOM_TX 14:I1
A
M
P
_
M
U
T
E
3
:
E
3
R
4
1
4
1
0
K
C412
0.1uF
OPT
100
R430
R
4
1
5
4
.
7
K
C406
0.1uF
16V
R420 22
R452
47K
OPT
S
D
A
2
_
3
.
3
V
9
:
B
5
;
9
:
I
4
X401
24MHz
C407
OPT
OPT
GND
+3.3V_ST
AMP_RST 9:G7;9:I3;3:C5
R
4
3
2
4
7
K
R403 0
OPT
R
4
1
3
4
.
7
K
+3.3V_ST
R
4
3
6
2
2
GND
GND
GND
IC405
24LC16BT-I/SN
3
A2
2
A1
4
VSS
1
A0
5
SDA
6
SCL
7
WP
8
VCC
Q401
2SC3875S(ALY)
E
B
C
H
D
M
I
_
C
E
C
2
:
A
D
2
6
R466 100 OPT
S
C
L
2
_
3
.
3
V
9
:
B
5
;
9
:
I
4
RL_ON 4:C7;14:E5
KEY1 14:E6
R459
4.7K
OPT
C411
100uF
16V
GND
R
4
0
7
4
7
K
R405
220
DDC_SCL 9:G7;14:A4
R
4
3
4
2
2
+3.3V_ST
GND
IC402
KIA7029AF
2
G
3 O 1 I
R
4
0
2
O
P
T
O
P
T
PANEL_CTL 4:H1
GND
R
4
4
6
0
O
P
T
R455
4.7K
OPT
+3.3V_ST
R
4
2
7
4
.
7
K
IC406
MTV416GMF
1
HSYNC/P1.5
2
VSYNC/P1.6
3
P1.7/SOGI
4
RST
5
HSCL1/P3.0/RXD
6
P4.3/AD3
7
HSDA1/P3.1/TXD
8
P3.2/INT0
9
P3.3/INT1
10
ISDA/P3.4/T0
11
ISCL/P7.5
1
2
H
S
D
A
2
/
P
7
.
4
1
3
H
S
C
L
2
/
P
7
.
3
1
4
X
2
1
5
X
1
1
6
V
S
S
1
7
P
4
.
0
/
A
D
0
1
8
P
6
.
0
/
C
L
K
O
1
1
9
P
6
.
1
2
0
P
6
.
2
2
1
P
6
.
3
2
2
P
6
.
4
23
P6.5
24
P6.6
25
P6.7
26
P7.2/HCLAMP
27
P7.1/VBLANK
28
P4.1/AD1
29
P7.0/HBLANK
30
P5.7/CLKO2
31
P5.6
32
P5.5
33
P5.4
3
4
P
5
.
3
3
5
P
5
.
2
3
6
P
5
.
1
3
7
P
5
.
0
3
8
V
D
D
3
9
P
4
.
2
/
A
D
2
4
0
P
1
.
0
/
E
T
2
4
1
P
1
.
1
/
D
A
0
4
2
P
1
.
2
/
D
A
1
4
3
P
1
.
3
/
D
A
2
4
4
P
1
.
4
/
D
A
3
KEY2 14:E6
+3.3V_ST
GND
C408
22pF
50V
R429
OPT
O
P
T
+3.3V_ST
R424 22
GND
R
4
4
5
0
O
P
T
GND
R423 OPT
OPT
C409
22pF
50V
C413
0.1uF
R425 22
C403
0.1uF
16V
R467 22
+3.3V_ST
R406
4.7K
R449 100
OPT
U
C
O
M
_
S
D
A
_
3
.
3
V
1
4
:
E
6
R450 100
OPT
U
C
O
M
_
S
C
L
_
3
.
3
V
1
4
:
E
7
+3.3V_ST
POWER_DET 9:C1
E
R
R
O
R
_
O
U
T
4
:
C
5
INV_ON/OFF 4:C5
R468 100
R
4
3
5
0
O
P
T
R
4
3
9
0
O
P
T
R
4
4
2
4
.
7
K
L
E
D
_
P
O
W
E
R
_
O
N
1
4
:
E
5
L
E
D
_
W
A
R
M
_
S
T
B
Y
1
4
:
E
5
R
4
7
4
1
0
0
R
4
7
1
1
0
0
R
4
6
4
1
0
0
RESET 9:A7
R479
1K
OPT
POWER_DET
9:A7;I4 +12V
+24V
+5.0V
+3.3V_ST
R431 100
OPT
R
4
0
1
1
K
R416 0
R
4
4
3
2
2
GND
R
4
9
9
4
.
7
K
R
4
9
4
4
.
7
K
R
4
7
0
1
0
0
R476
15K
R478
10K
O
P
T
R480
2.2K
OPT
IC1003
NCP803SN293
1
GND
3 VCC 2 RESET
+3.3V_ST
R487
100K
OPT
R484
30K
R482
30K
OPT
R486
0
OPT
R490
0
OPT
R485
10K
R481
0
OPT
R
4
9
1
5
.
1
K
R462
100
R456
100
R483
0
R492
0
OPT
Q404
2SC3052
OPT
E
B
C
Q405
2SC3052
OPT
E
B
C
R
4
5
3
1
K
R451 2K
R454 2K
R
4
8
8
3
3
K
R421 4.7K
R418
4.7K
C415
0.1uF
16V
Q402
RT1N141C-T112-1
E
B
C
R
4
7
2
4
.
7
K
+5.0V
GND
D3.3V
+5V_ST
R
4
4
0
1
0
0
R477
6.8K
+3.3V_ST
R475 1K
FLASH_WP_1 4:C5
R
4
9
5
4
.
7
K
R
4
9
6
4
.
7
K
R489
33K
12 15
M5V_ON
POWER DETECT
LIM.K.R
R
4
3
5

:

R
E
A
D
Y

F
O

1
.
2
V

B
C
M

E
N
A
B
L
E
R
E
A
D
Y

F
O

1
.
2
V

B
C
M

E
N
A
B
L
E
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23
BCM3549 POWER
BRAZIL DVR DV
R205
20
D1.2V
A3.3V
C2003
0.1uF
D1.8V
D3.3V
C251
0.01uF
C271
4.7uF
C289
0.1uF
C247
0.1uF
D1.8V
C250
1000pF
C248
1000pF
C276
0.1uF
C244
1000pF
C249
4.7uF
C281
1000pF
C294
0.1uF
C246
0.01uF
C264
1000pF
D3.3V
C267
0.01uF
D1.2V
D3.3V
C286
33uF
C258
4.7uF
C265
0.1uF
C216
0.1uF
C254
10uF
C283
1000pF
C285
0.01uF
C297
4.7uF
C2005
0.01uF
C272
0.1uF
C245
4.7uF
C255
1000pF
C288
1000pF
C2006
0.01uF
C287
33uF
C270
0.1uF
C259
1000pF
C293
0.01uF
C291
10uF
C268
1000pF
C263
4.7uF
C266
4.7uF
C278
4.7uF
C257
0.01uF
C2004
33uF
C262
0.01uF
C253
10uF
C284
0.01uF
C252
0.1uF
C282
1000pF
C290
0.01uF
C292
1000pF
C275
0.1uF
C280
4.7uF
C243
0.1uF
D1.2V
C261
0.1uF
D1.8V
C269
0.01uF
C256
0.1uF
C318
0.1uF
16V
C364
0.1uF
16V
C304
0.1uF
16V
C320
0.1uF
16V
C319
0.1uF
16V
C348
0.1uF
16V
D1.8V
C363
0.1uF
16V
C365
0.1uF
16V
C356
0.1uF
16V
C357
10uF
10V
IC100
BCM3556
DVSS_1
AD5
DVSS_2
AD6
DVSS_3
J7
DVSS_4
K7
DVSS_5
L7
DVSS_6
M7
DVSS_7
AB7
DVSS_8
AC7
DVSS_9
G8
DVSS_10
D9
DVSS_11
AA9
DVSS_12
G10
DVSS_13
A11
DVSS_14
L11
DVSS_15
M11
DVSS_16
N11
DVSS_17
P11
DVSS_18
R11
DVSS_19
T11
DVSS_20
U11
DVSS_21
V11
DVSS_22
D12
DVSS_23
G12
DVSS_24
L12
DVSS_25
M12
DVSS_26
N12
DVSS_27
P12
DVSS_28
R12
DVSS_29
T12
DVSS_30
U12
DVSS_31
V12
DVSS_32
L13
DVSS_33
M13
DVSS_34
N13
DVSS_35
P13
DVSS_36
R13
DVSS_37
T13
DVSS_38
U13
DVSS_39
V13
DVSS_40
G14
DVSS_41
L14
DVSS_42
M14
DVSS_43
N14
DVSS_44
P14
DVSS_45
R14
DVSS_46
T14
DVSS_47
U14
DVSS_48
V14
DVSS_49
L15
DVSS_50
M15
DVSS_51
N15
DVSS_52
P15
DVSS_53
R15
DVSS_54
T15
DVSS_55
U15
DVSS_56
V15
DVSS_57
A16
DVSS_58
G16
DVSS_59
L16
DVSS_60
M16
DVSS_61
N16
DVSS_62
P16
DVSS_63
R16
DVSS_64
T16
DVSS_65
U16
DVSS_66
V16
DVSS_67
AA16
DVSS_68
D17
DVSS_69
L17
DVSS_70
M17
DVSS_71
N17
DVSS_72
P17
DVSS_73
R17
DVSS_74
T17
DVSS_75
U17
DVSS_76
V17
DVSS_77
AA17
DVSS_78
AC19
DVSS_79
G18
DVSS_80
L18
DVSS_81
M18
DVSS_82
N18
DVSS_83
P18
DVSS_84
R18
DVSS_85
T18
DVSS_86
U18
DVSS_87
V18
DVSS_88
D20
DVSS_89
G20
DVSS_90
H20
DVSS_91
A21
DVSS_92
E21
DVSS_93
F21
DVSS_94
G21
DVSS_95
E22
DVSS_96
F22
DVSS_97
G22
DVSS_98
H22
DVSS_99
J22
DVSS_100
K22
DVSS_101
L22
DVSS_102
M22
DVSS_103
N22
DVSS_104
P22
DVSS_105
R22
DVSS_106
T22
DVSS_107
U22
DVSS_108
V22
DVSS_109
W22
DVSS_110
Y22
DVSS_111
AA22
DVSS_112
W23
DVSS_113
AB23
DVSS_114
F28
DVSS_115
M28
DVSS_116
T28
DVSS_117
AC28
IC100
BCM3556
VDDC_1
H8
VDDC_2
J8
VDDC_3
K8
VDDC_4
L8
VDDC_5
M8
VDDC_6
N8
VDDC_7
P8
VDDC_8
R8
VDDC_9
AA8
VDDC_10
H9
VDDC_11
H10
VDDC_12
H11
VDDC_13
H12
VDDC_14
H13
VDDC_15
H14
VDDC_16
H15
VDDC_17
H16
VDDC_18
H17
VDDC_19
H18
VDDC_20
H19
VDDC_21
H21
VDDC_22
J21
VDDC_23
K21
VDDC_24
L21
VDDC_25
M21
VDDC_26
N21
VDDC_27
P21
VDDC_28
R21
VDDC_29
T21
VDDC_30
U21
VDDC_31
V21
VDDC_32
W21
VDDC_33
Y21
AGC_VDDO
AH27
VDDO_1
AA12
VDDO_2
AA13
VDDO_3
AA18
VDDO_4
AA19
VDDO_5
E28
VDDO_6
L28
VDDO_7
U28
VDDO_8
AB28
DDRV_1
A9
DDRV_2
G9
DDRV_3
G11
DDRV_4
G13
DDRV_5
A14
DDRV_6
G15
DDRV_7
G17
DDRV_8
A19
DDRV_9
G19
15 13
JANG.J.H
A B C D E F G H I J
1
2
3
4
5
6
7
U
S
B

D
O
W
N

S
T
R
E
A
M
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23 BRAZIL VENUS
C711
0.1uF 16V
R701
0
R703
0
RS232C_RxD
A3
BCM_RX
9:G6
BCM_TX 9:G6
C712
47uF
16V
+5.0V
IC702
MC14053BDR2G
0ISTL00024A
3
Z1
2
Y0
4
Z
1
Y1
6
INH
5
Z0
7
VEE
8
VSS
9
C
10
B
11
A
12
X0
13
X1
14
X
15
Y
16
VDD
+5V_ST
R
7
0
5
0
RS232_BYPASS
R702
0
RS232_BYPASS
UCOM_RX
12:D4
UCOM_TX 12:D4
RS232C_TxD A3
R706
4.7K
R_RS232_SWITCHING
R704
100K
USB_OCD1 10:D4
USB_CTL1
10:D5
USB_DP2 10:D4
R717
47
D705
5.6V
CDS3C05GTA
OPT
USB_DM1 10:D4
BLUETOOTH_RESET
C716
0.1uF
16V
D3.3V
D706
5.6V
CDS3C05GTA
OPT
D703
5.6V
CDS3C05GTA
OPT
USB_DM2 10:D4
D704
5.6V
CDS3C05GTA
OPT
D3.3V
VREG_CTRL
L708
BLM18PG121SN1D
IC701
MIC2009YM6-TR
3
ENABLE
2
GND
4
FAULT/
1
VIN
6
VOUT
5
ILIMIT
USB_DP1 10:D4
R718
2.7K
R721
2.7K
R720
0
R719
0
JP712
JP711
JP713
+5V_ST
USB_POWER_OUT_2
USB_POWER_OUT_2
R722
27
R723
27
C714
100uF
C715
100uF
16V
P702
12507WR-10L
1
2
3
4
5
6
7
8
9
10
11
L709
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
USB_5VST
L706
MLB-201209-0120P-N2
L707
C
B
3
2
1
6
P
A
5
0
1
E
ZD703
C708
0.1uF
UCOM_SCL_3.3V 12:F6
L704
BG2012B080TF
L705
CB3216PA501E
C706
0.1uF
KEY2 12:H3
D701
C
D
S
3
C
0
5
H
D
M
I
1
C707
1000pF
50V
OPT
L703
BG2012B080TF
ZD701
+5V_ST
UCOM_SDA_3.3V 12:F6
KEY1 12:H3
C705
1000pF
50V
OPT
C704
0.1uF
D702 C
D
S
3
C
0
5
H
D
M
I
1
R
7
1
0
1
0
K
LED_WARM_STBY
+3.3V_ST
R712
0
Q702
2SC3052
OPT
E
B
C
R
7
1
5
1
2
0
K
O
P
T
R711
0
OPT
C710
0.1uF
16V
C702
100pF
ZD702
OPT
IR
12:D4;A3 L701
BG2012B080TF
C703
1000pF
50V
L702
CB3216PA501E
C701
0.1uF
+3.3V_ST
R708
0
OPT
R713
0
RL_ON
R
7
0
7
1
0
K
Q701
2SC3052
E
B
C
R709
4.7K
+3.3V_ST
C709
0.1uF
16V
R714
0
OPT
LED_POWER_ON
JK702
KJA-UB-4-0004
1
2
3
4
5
C713
10uF
16V
P701
12507WS-12L
1
SCL
2
SDA
3
GND
4
KEY1
5
KEY2
6
5V_ST
7
GND
8
WARM_ST
9
IR
10
GND
11
3.3V_ST
12
POWER_ON
13
GND
R716
130
L710
M
L
B
-
2
0
1
2
0
9
-
0
1
2
0
P
-
N
2
USB_+5V
+5.0V
JP715
JP716
15 14
RS232_SWITCHING
BCM Tolerance
USB JACK & USB +5V Current Protection
Blue Tooth
Make this trace minimum 12 mil
DO.J.G
CONTROL IR/BT/USB
Not enough space
CONTROL IR & LED
A B C D E F G H I J
1
2
3
4
5
6
7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.03.23 BRAZIL VENUS
GAIN_SWITCH
RF_SWITCH
R5007 22
C5012
0.01uF
SCL0_3.3V 3:T26
R5012
0
R5009 22
C5021
0.01uF
R50000
LGIT
TU_SYNC 3:T27
TU_+5.0V
R
5
0
1
9
5
6O
P
T
TU_+5.0V
R5006 22
GAIN_SWITCH 3:T24
Q5000
2SA1530A-T112-1R
E
B
C
C5011
0.1uF
L5002
L
5
0
0
0
L
G
I
T
C5003
22pF
50V
LGIT
LD5001
SAM2333
A2[GN]
C
A1[RD]
R
5
0
2
0
1
2
K
C5018
22uF
C5016
0.1uF
TU_SIF 3:T25
GND
R5018
56
C5010
22uF
C5005-*1
0.1uF
50V
LGIT
R50020 LGIT
TU_SCLK 3:T27
C5001
22pF
50V
LGIT
R
5
0
2
4
4
7
0
TU_SDATA 3:T27
L5006
C5019
0.01uF
C5017
0.1uF
R5013
0
R5005 22
R5004
0
R5023
1K
TU_CVBS_IN 3:T25
C5002
0.1uF
50V
LGIT
C5000
22uF
16V
LGIT
L5007
TUNER_RESETb 3:T26
C5005
2200pF
50V
R5008 22
R5014
0
R50010 LGIT
TU101
VA1G5BF8005
SHARP
14
RSEORF
13
SCL
5
AFT
12
SDA
11
RESET
2
GAIN_SW
10
B4
4
B1
1
RF_SW
17
SRDT
9
B3
8
B2
3
BB
16
SPBVAL
7
VIDEO
6
SIF
15
SBYTE
18
SRCK
19
SHIELD
C5014
22uF
TU_+5.0V
D3.3V
L5005
D3.3V
L5004
C5020
0.1uF
C5007
2200pF
50V
RF_SWITCH 3:T24
R5022
0
OPT
C5009 10uF
1
6
V
R5010 22
R5021
10K
D1.2V
R
5
0
1
5
4
.
7
K
O
P
T
LD5000
SAM2333
A2[GN]
C
A1[RD]
C5015
22uF
SDA0_3.3V 3:T26
D3.3V
R5025 330
C5023
100uF
16V
C5026
0.33uF
16V
C5029
0.1uF
50V
TU_+5.0V
C5032
0.1uF
16V
IC5002
AS7809DTRE1
2
GND
3 OUTPUT 1 INPUT
L5008
MLB-201209-0120P-N2
IC5001
KIA78R05F
1
V
I
N
2
V
C
3
V
O
U
T
4
N
C
5
G
N
D
1
6
G
N
D
2
C5028
47uF
16V
R
5
0
2
6
1
0
0
D3.3V
C5022
0.1uF
16V
C5030
0.01uF
50V
C5034
4.7uF
10V
OPT
C5033
4.7uF
10V
OPT
C5024
0.1uF
50V
C5025
100uF
16V
+5V
L5010
MLB-201209-0120P-N2
C5031
0.1uF
16V
+12V
L5009
MLB-201209-0120P-N2
C5035
100uF
16V
C5027
0.1uF
50V
C5036
100uF
16V
D2.5V
R
5
0
0
3
8
2O
P
T
L
5
0
0
1
F
I
-
C
3
2
1
6
-
1
0
3
K
J
T
O
P
T
C5004
91pF
50V OPT
TU102
TDYR-H071F
LGIT
14
B3[3.3V]
13
B2[2.5V]
5
RF_AGC
12
AIF
11
NC_3
2
RF-GAIN_SW
19
RSEORF
18
SCL
10
NC_2
4
VTU
1
CTR
17
SDA
9
VIDEO_OUT
8
SIF
3
B0[+5V]
16
RESET[SYRSTN]
7
NC_1
6
B1[+5V]
15
B4[1.2V]
24
SHIELD
20
SBYTE
21
SPBVAL
22
SRDT
23
SRCK
15 15
DO.J.G
TUNER
Place close to Pin
A B C D E F G H I J
1
2
3
4
5
6
7
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Block Diagram
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
I2C & RS232 Communication
I2C & RS232 Communication
BCM3556
HDMI
S/W
MST7323
NTP3100L
SCL0
D3.3V
SDA0
4
.
7
k

o
h
m
4
.
7
k

o
h
m
SCL2
SDA2
4
.
7
k

o
h
m
4
.
7
k

o
h
m
SCL1
SDA1
4
.
7
k

o
h
m
4
.
7
k

o
h
m
SCL3
SDA3
4
.
7
k

o
h
m
4
.
7
k

o
h
m
+3.3V_HDMI
2
.
7
k

o
h
m
2
.
7
k

o
h
m
100 ohm
33PF
100 ohm
33PF
0 ohm
0 ohm
100 ohm
100 ohm
MICOM
22 ohm
22 ohm
V
A
1
G
5
B
F
8
0
0
5
22 ohm
22 ohm
RS232C_RxD
RS232C_TxD
MAX3232
+5V_ST
4
.
7
k

o
h
m
4
.
7
k

o
h
m
P
7
0
2
100 ohm
100 ohm
P
7
0
1
Sub B/D
Main B/D
22 ohm
22 ohm
22 ohm
22 ohm
47PF
47PF
22 ohm
22 ohm
22 ohm
22 ohm
D3.3V
D3.3V
D3.3V
Block Diagram
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
BCM3556
BCM3556
FRC
MST7323
FRC
MST7323
CH1
CH2
CH3
CH1 (+3.3V)
CH2 (+3.3V)
CH3 (+3.3V)
HDMI SW
TDA9996
HDMI SW
TDA9996
Micom
MTV416
0x50
Micom
MTV416
0x50
CH0
EEPROM
AT24C512
0xA6
EEPROM
AT24C512
0xA6
AMP
NTP3100L
0x54
AMP
NTP3100L
0x54
TUNER 1
0xC2
Demod(0x30)
QPSK(0x32)
TUNER 1
0xC2
Demod(0x30)
QPSK(0x32)
CH0 (+3.3V)
I2C channel [LH70]
Block Diagram
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
MAIN MAIN
Board Board
Jack Jack
Board Board
D1.2V, D2.5V, +3.3V, +5.0V_ST
SCL0_3.3V, SDA0_3.3V, DDC_SCL, DDC_SDA
CVBS, SIF, AV, RGB ,COMPONENT, R/L,
TU_SCLK, TU_DATA, TU_SYNK..
< Signal Interface >
SPDIF , EDID_WP .
Block Diagram
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
1. Power-Up Boot Fail Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
1. Power-Up Boot Fail Trouble Shooting
Replace Power board
N Y
Check MicomIC406
Redownload or replace
Check P801 All Voltage Level
(24V, 12V, 5V_ST)
Check Power connector
Y
Check Voltage Level 3.3V at L830
N
Replace one of
IC809/Q812/L828/L829/L830/L822
& Recheck
Y
N
Check Voltage Level 2.5V at L827
N
Replace one of IC803/L824/L827
& Recheck
N
Y
Check Voltage Level 1.8V
at IC802 #2 pin or L815
N
Replace one of IC802/IC805/L815
& Recheck
N
Y
Check Voltage Level 1.2V at L821
N
Replace one of
IC804/Q809/L811/L817/L821
& Recheck
N
Y
Check X903 Clock 54MHz
N
Replace X903
Y
Check signal transition
at IC101 #9 pin
N
Maybe BCM3556 has troubles
Replace IC101 Flash Memory
Y
Check All Voltage Level
at L805/L807/L808
N
Replace one of L805/L807/L808
& Recheck
Y
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
2. No OSD Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
2. No OSD Trouble Shooting
Replace Power board
N Y
Check 12V Voltage Level
at P801 #13 Pin
Check Power connector
Y
Check 12V Voltage Level at L909
N
Replace one of
Q802/Q803/Q804/L801
& Recheck
Y
Check P903
#16(TXAC-), #17(TXAC+),
#32(TXBC-), #33(TXBC+)
Y
Check LVDS Cable
N
Replace Cable
Y
Check Voltage LCD Module
Check 12V Voltage Level
at L801
N
Replace one of L801/Q804
& Recheck
Y
Maybe BCM3556(IC100) or
7329A(IC901)
has troubles
Check Voltage Level 2.5V at L827
N
Replace one of IC803/L824/L827
& Recheck
Y
Check Voltage Level 1.8V
at IC802 #2 pin or L815
N
Replace one of IC802/IC805/L815
& Recheck
Y
Check Voltage Level 1.26V
at IC807 #6 pin
N
Y
N
Replace IC807
& Recheck
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. Digital TV Video Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. Digital TV Video Trouble Shooting
Check RF Cable
Y
Check TP Clock, Data, Sync
R107, R108, R109
N
Maybe Tuner(TU101) has problems
Y
Maybe BCM3556(IC100)
has problems
Check Tuner(TU101) Power
(5.0V, 2.5V, 3.3V, 1.2V)
N
Replace one of IC101, IC102 at
J ack Board or IC803/ IQ812/ C804/
Q809/+5V_ST and +12V of P801 at
Main Board& Recheck
Y
Check cable between P203 at J ack
Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
4. Analog TV Video Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
J ACK BACK J ACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
4. Analog TV Video Trouble Shooting
Check RF Cable
Y
Check CVBS Signal
TU101 #7 Pin and R118
N
Y
Check CVBS Signal
R703 and C110 at Main Baord
N
Replace one of R703 and C110
& Recheck
Y
Y
Maybe Tuner(TU101) has problems
Check Tuner(TU101) Power
(5.0V, 2.5V, 3.3V, 1.2V)
N
Maybe BCM3556(IC100)
has problems
Check cable between P203 at J ack
Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y
Replace one of IC101, IC102 at
J ack Board or IC803/ Q812/ IC804/
IC809/Q809/+5V_ST and +12V of
P801 at Main Board& Recheck
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
5. Component Video Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram Overall Block Diagram
for Brazil DTV ( for Brazil DTV (LH70) )
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
5. Component Video Trouble Shooting
Check Signal Format
Is it supported signal?
Y
Check Component J ack J K209 at
J ack Board
N
Y
Check Component Signal
R292, R293, R294
R295, R296, R297
at J ack Board
N
Replace one of
R292, R293, R294, R295, R296, R297
L212, L213, L214, L215, L216, L217
& Recheck
Y
Check Component Signal
C130, C131, C132
C133, C134. C135
N
Replace it
Y
Y
Check Component Cable
Replace J ack at J ack board
Maybe BCM3556(IC100)
has problems
Check cable between P203 at J ack
Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. RGB Video Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. RGB Video Trouble Shooting
Check Signal Format
Is it supported signal?
Y
Check RGB Cable
Check RGB J ack J K208 at J ack
Board
N
Y
Check RGB Signal
L207, L208, L209 at J ack Board
N
Replace one of L207, L208, L209
at J ack Board & Recheck
Y
Check RGB Signal
C127, C128, C129 at Main Board
N
Replace it
Y
Y
Replace J K208 at J ack board
Maybe BCM3556(IC100)
has problems
Check cable between P203 at J ack
Board and P701 at Main Board
N
Maybe Cable Pin has problems
Y
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. AV Video Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. AV Video Trouble Shooting
Y
Y
Check Signal Format
Is it supported signal?
Check AV Cable
Check AV J ack J K209 at J ack
Board
N
Y
Check AV Signal
R203, R204, R214, R215 at J ack
Board
N Replace one of R203, R204, R214,
R215 at J ack Board
& Recheck
Y
Check AV Signal
C124, C125 at Main Board
N
Replace it
Y
Y
Replace J K209 at J ack board
Maybe BCM3556(IC100)
has problems
Check cable between P203 at J ack
Board and P701 at Main Board
N
Maybe Cable Pin has problems
Y
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
8. HDMI Video Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
8. HDMI Video Trouble Shooting
Check Signal Format
Is it supported signal?
Y
Check HDMI J ack
J K600, J K601, J K602
N
Y
Y
Check HDMI Cable
Replace J ack
Check IC601 Voltage Level
+1.8V_HDMI, +5.0V_HDMI
N
Replace one of
L601/L602/R619/R615
Y
Check I2C Signal
R624/R625/R157/R158
N
Replace It & Recheck
Y
Maybe BCM3556(IC100)
has problems
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
9. All Source Audio Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
9. All Source Audio Trouble Shooting
Make sure you cant hear any audio
Y
Check Connector P501
N
Y
Y
Check Speaker
Replace Connector
Check Signal
L504, L505
N
Replace one of
L508/L509/L510/L507/L504/L505
& Recheck
Y
Check IC501 Power
24V, 3.3V, 1.8V
L511, L503, L501
N
Replace one of
L511L503/L501 and IC503
& Recheck
Y
Check BCM3556 I2S Output
R505, R506, R507
N
Replace It & Recheck
Y
Maybe BCM3556(IC100)
has problems
Replace Speaker
N
N
Maybe NTP3100 has problems.
Replace It
N
N
N
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
10. Digital TV Audio Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
10. Digital TV Audio Trouble Shooting
Check video output
Y
Follow procedure All source audio
trouble shooting
Maybe BCM3556 internal audio
DSP has problems. Replace It
N
Follow procedure digital TV video
trouble shooting
N
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
11. Analog TV Audio Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
11. Analog TV Audio Trouble Shooting
Follow procedure analog TV video
trouble shooting
N
Check video output
Y
Y
N
Y
Check SIF Signal
C128 at J ack Board
N
Replace one of C123, R120, R121,
R124, L109, Q101, C128
& Recheck
Y
Follow procedure All source audio
trouble shooting
N
Maybe BCM3556 audio block has
problems. Replace It
Y
Replace one of
L505/L514/C502/C511/Q500/Q502
IC501 & Recheck
Check SIF Signal
IC501 #4 Pin
Check SIF Signal
TU101 #6 Pin and R118 at J ack
Board
N
Check SIF Signal
R704 and C106 at Main Board
N
Replace one of R704/R128/C106
& Recheck
Y
Maybe Tuner(TU101) has problems
Check Tuner(TU101) Power
(5.0V, 2.5V, 3.3V, 1.2V)
N
Replace one of IC101, IC102 at
J ack Board or IC803/ Q812/ IC804/
IC809/Q809/+5V_ST and +12V of
P801 at Main Board& Recheck
Check cable between P203 at J ack
Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Y
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
12. Component / RGB / AV Audio Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
12. Component / RGB / AV Audio Trouble Shooting
Y
Check J ack J K208/J K209
N
Y
Check Signal
R235, R236 (Comp1)
R216, R217 (Comp2)
R249, R250 (RGB)
R219, R221 (AV1)
R218, R220 (AV2)
at J ack Board
N
Replace J ack
Check Video Output
Replace one of
R235/R236/C231/C232 (Comp1)
R216/R217/C207/C208 (Comp2)
R219/R221/C210/C212 (AV1)
R218/R220/C209/C211 (AV2)
R249/R250/C246/C247 (RGB)
& Recheck at J ack Board
N
Follow procedure external input
video trouble shooting
Y
Check Signal
C206, C210, C211, C232, C220,
C221, C224, C225, C226, C227
at Main Board
N
Y
Y
Follow procedure All source audio
trouble shooting
N
Maybe BCM3556 audio block has
problems. Replace It
Check cable between P203 at J ack
Board and P701 at Main Baord
N
Maybe Cable Pin has problems
Replace one of
R215/R228/C211/C232 (Comp1)
R229/R230/C220/C221 (Comp2)
R204/R214/C206/C210 (AV1)
R231/R232/C224/C225 (AV2)
R233/R234/C226/C227 (RGB)
& Recheck at Main Board
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
13. HDMI Audio Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
13. HDMI Audio Trouble Shooting
Check video output
Y
Follow procedure All source audio
trouble shooting
N
Y
Re-download EDID data
Maybe BCM3556 audio block has
problems. Replace it
N
Follow procedure HDMI video
trouble shooting
N
Replace IC601
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
14. USB Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
14. USB Trouble Shooting
Exception
- USB power could be disabled by inrushing current
- In this case, remove the device and try to reboot the TV (AC power off/on)
Check USB 2.0 Cable
Y
Check P704
N
Y
Y
Check USB device
If devuce is 2.5 inch HDD,
Check power adaptor
Replace J ack
Check 5V voltage level at L703
N
Y
Maybe BCM3556(IC100)
has problems. Replace It.
Replace one of
IC701/L703/IC806/Q810/L819
& Recheck
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
14. Bluetooth Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
14. USB Trouble Shooting
Check Bluetooth Module
Y
Check P705
N
Y
Y
Check Cable between Bluetooth
and Main Board
Replace J ack
Y
Maybe BCM3556(IC100)
has problems. Replace It.
N
Replace Bluetooth
N
Replace cable
Check Signal
R3022, R3023
N
Replace one of
R3022, R3023
& Recheck
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
15. Digital TV Recording Fail Trouble Shooting
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
N
Y
Check USB
N
Follow procedure USB trouble
shooting
15. Digital TV Recording Fail Trouble Shooting
Check video/audio output
Follow procedure digital TV
video/audio trouble shooting
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
18. Digital TV Video Trouble Shooting while recording (Watch & Record)
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Check RF Cable
Y
Y
18. Digital TV Video Trouble Shooting while recording (Watch & Record)
N
Y
Check USB
N
Follow procedure USB trouble
shooting
Check video/audio output
Follow procedure digital TV
video/audio trouble shooting
Check Watch
N
Follow procedure OSD trouble
shooting
Y
Check HDD (User)
N
Replace J ack
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
19. Digital TV Audio Trouble Shooting while recording (Watch & Record)
D-sub RGB
HDMI 1
AV2
SIDE_CVBS, SIDE_L/R, SIDE_DET
DDR2 (1Gbit)
Elpida/Hynix
NAND Flash
(512Mbit)
Digital Audio (Optic)
USB
Digital AMP
NTP3100L
RS-232C (Ctrl./SVC)
3x1
HDMI Switch
I2S
NVRAM
RGB/H/V
V
A
1
G
5
B
F
8
0
0
5
DDR_Data[0:15], DQS, DM
DDR2 (1Gbit)
Elpida/Hynix
Data[16:31]
Addr.[0:13], ctrl. data
MICOM
(MTV416GMF)
MAX3232
BCM3556 BCM3556
(Brazil) (Brazil)
Data [0 7]
TU_SCLK, TU_SDATA, TU_SYNC
TU_SIF
TU_CVBS_IN
X-tal
RF_Switch, Gain_Switch
SDA0/SCL0_3.3V
Reset Switch
J TAG
CLK,TDI,TDO,MS,RST
X-tal
24MHz
AV1
Component 1
Y Pb Pr, L/R, DET
CVBS, L/R, AV_DET
CS ,RE,WE
Component 2
Y Pb Pr, L/R, DET
Audio L/R
Audio L/R (for RGB)
HDMI 2
HDMI 3
SPDIF
RX/TX RX/TX
Reset IC
54MHz
JACK BACK JACK BACK
at REAR at REAR
SCL, SDA_3.3V
SCL, SDA_3.3V
FRC IC
(MST7323S)
DDR2(256Mbit)
Qimonda/Hynix
FRC Block FRC Block
LVDS
LCD Module
(FHD, 120Hz)
Overall Block Diagram
for Brazil DTV (LH70)
X-tal
12MHz
Bluetooth Module
DP1/DM1
USB_DM1
USB_DP1
DP2/DM2 USB_DM2
USB_DP2
O.C. Protector +5V +5V
Copyright 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Check video output
Y
Follow procedure All source audio
trouble shooting
Maybe BCM3556 internal audio
DSP has problems. Replace It
N
Follow procedure digital TV video
trouble shooting while recording
(watch & record)
N
19. Digital TV Audio Trouble Shooting while recording (Watch & Record)

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