gem5

An Architectural Simulator
28 Aug 2013 CADSL Seminar: The gem5 Simulator 2
What do we want ?

To play with our ideas

What sort of Ideas

Multicore Architecture

Cache Hierachy

Cache Coherency Protocol

Microarchitecture Ideas

Interconnection Topologies

Flexible and Modular Siulation fraewor!

To test ideas in di"erse fields

28 Aug 2013 CADSL Seminar: The gem5 Simulator 3
gem5 is Flexible

# CP$ Models

AtoicSiple %Fastest&

TiingSiple

In'rder

'( %)etailed&

* Syste execution odes

System-call Emulation %S+&

Full-System %FS&

* Meory Systes %Classic, -uby&

28 Aug 2013 CADSL Seminar: The gem5 Simulator 4
CPU Models

AtoicSiple

Minial single IPC

.on/pipelined

Attepts to F, )e, +x, C on e"ery cycle0

.o eory access latency

1ood choice for fast/forwarding

TiingSiple

2 Siulates tiing of eory reference

28 Aug 2013 CADSL Seminar: The gem5 Simulator 5
CPU Models

In'rder

3execute/in/execute4 CP$

Configurable pipeline stages

Issue Width

Supports ulti/threading

Instruction Tiing and Meory latency

'o' %'(&

'uter of 'rder

Paraeteri5able pipeline resources

28 Aug 2013 CADSL Seminar: The gem5 Simulator 6
Execution Modes

Syste/call +ulation %S+&

+ulates ost syste calls %e0g0 read()&

Passes syste call to host 'S

Siplified address translation odel

.o thread scheduling

Full/Syste %FS&

For wor!loads that re6uire 'S ser"ices

Support for interrupts, exceptions

More realistic
28 Aug 2013 CADSL Seminar: The gem5 Simulator 7
Features Available

For research in Micro/architecture

Configurable superscalar architecture

Paraeters for 'o' in O3CPU.py

For Syste le"el

Cloc! Fre6

7 of cores

7 of threads

Paraeters in Options.py
28 Aug 2013 CADSL Seminar: The gem5 Simulator 8
Features Available

Creating Chec!point

8eneficial if siulation tie is large

To analyse in detail the region of interest

Switch o"er

Switching between CP$ odels on fly0

Fro fast atoic to slow detailed

ISA Supported

Alpha, A-M, MIPS, Power, SPA-C, x9:

28 Aug 2013 CADSL Seminar: The gem5 Simulator 9
Features Available

S;ICC

;anguage for Cache Coherence Protocol

Perfors all operations at cache/bloc!

granuality0 %Word/le"el <&

'ne can a!e own Cache Controller

Interconnection .etwor!

28 Aug 2013 CADSL Seminar: The gem5 Simulator 10

Examle

. =ueens 8enchar!

Placing . 6ueens on an . x .
chessboard such that no 6ueen can
attac! any other
28 Aug 2013 CADSL Seminar: The gem5 Simulator 11
! "ueens #enchmar$

Copile: arm-linux-gnueabi-gcc -DUNIX \

-o ./queen/queens ./queen/queens.c -static

-un> ./build/ARM/gem5.opt \
configs/example/se.py -c ./queen/queen -o 8
--caches cpu-type=arm_detailed

Chec!point>

Copile> arm-linux-gnueabi-gcc -DUNIX

-o ./queen/queens ./queen/queens.c
util/m5/m5op_arm.S -static

Create chec!point

-estore fro chec!point

28 Aug 2013 CADSL Seminar: The gem5 Simulator 12
Features %et unexlored

Hac!ing ge?

)ebugging code in ge?

How ulticores can counicate

How SMT can be used on ulticore

Writing own cache controller

28 Aug 2013 CADSL Seminar: The gem5 Simulator 13
&MP 'e(erences

The ge? siulator

http://dl.acm.org/citation.cfm?id=2024718

1e? webpage www.m5sim.org

)iscussion pages
http://thread.gmane.org/gmane.comp.emulators.m5.users/
http://www.mail-archive.com/gem5-users@gem5.org/

Tutorial www.m5sim.org/Tutorials
)han$s *+
"uestions are welcome