ADVANCED LOW-POWER FULL-ADDER CELL FOR LOW

VOLTAGE

R.S. Kamala Kannan
a
, M.Srinivasan
b
, S. Durairaj
c

a Faculty of Electronics and Communication Engineering, Shree venkateshwra hi-tech engineering
college, TamilNadu,India.
b Faculty of Electronics and Communication Engineering, Shree venkateshwra hi-tech engineering
college, TamilNadu,India.
c. Faculty of Aeronautical Engineering, Park College of Engineering and Technology,
TamilNadu,India.

A B S T R A C T:-

This paper presents a novel low-power majority function-based 1-bit full adder that u s e s MOS
capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the
time- consuming XOR gates are eliminated. The ci rcui ts being studied are optimized for energy
efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used
adders based on power consumption, speed, power-delay product (PDP) and area efficiency.
Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has
more than 11% in power savings over a conventional 28-transistor CMOS adder. In addi t i on, it
consumes 30% less power than transmission function adder (TFA) and is 1.11 ti mes faster.

1. INTRODUCTION

With the explosive growth in laptops, portable personal communication systems
and the evolution of the shrinking technology, the research effort in low-power
microelectronics has been intensied and low-power VLSI systems have emerged as highly in
demand. Today, t h e r e is an increasing number of portable applications requiring small-area
l o w -power h i g h - throughput circuitr y. Therefore, circuits with l ow power con-sumption
become t he ma j o r candidates [ 13] for design of microprocessors and system-
components. The battery technology does not advance at t h e s a me r at e as the
microelectronics technology and there is a limited amount of power available for the mobile systems.
The goal of extending the battery life span of portable electronics is to reduce the energy
consumed per arithmetic operation, but low power consumption does not necessarily imply
low energy. To execute an arithmetic operation, a circuit can consume very low power by
clocking at extremely low frequency but it may take a very long time to complete the
operation. Therefore, designers are f a c e d with more c o n s t r a i n t s such as high speed, high
throughput, and small silicon area and at the same time low power consumption. This i s why
building l o w- power, high-performance adder cells is of great interest.
Addition is one of the fundamental arithmetic operations and is used extensively in many
VLSI systems. In addition to its main task, which is adding two binary numbers, it is the nucleus
of many other useful operations. [1, 49].
One of the objectives of this work is to design a circuit based on
0.18-mm CMOS process technology that can o p e r a t e at ultralow- power supply voltage. One o f
t he most important obstacles in decreasing supply voltage is the large transistor count and V
th loss

problem.
In nano-scaling, the biggest power consumption is static power dissipation. The proposed
adder has very low short-circuit current and reduced transition activity compared with previously pro-
posed low-power adders [12].
The rest of this paper is organized as follows. Section 2 explores a review of the full adder
design in different logic styles. Creating a full adder by using Majority Function is proposed in
Section 3. In Section 4, a new adder is presented and in Section 5 the circuits are simulated and the
simulation results of power consumption, delay, power -delay product, area efficiency and
immunity to noise are analyzed and compared. Finally, Section 6 concludes the paper.

2. REVIEW OF FULL-ADDER DESIGNS

The complementary CMOS full a d d e r ( C-CMOS) [1, 1316] is based on a regular CMOS
structure with conventional pull-up and pull-down transistors and has 28 transistors. C-
CMOS ge ne r a t e s Cout t h r o u g h o u t a s i n g l e static CMOS gate. The i nput capacitance of a
static CMOS gate is large because each input is connected to the gate of at least a PMOS and an
NMOS device. Additional buffers at the last stage are needed to provide the required driving power
because the series transistors in the out put s t a g e form a weak driver. The advantage of
complementary CMOS style is its robustness a ga i ns t v o l t a g e scaling and transistor
sizing.
Another adder, i s the complementary pass- transistor logic (CPL) [1, 13, 14, 16, 17] with swing
restoration, which uses 32 transistors. CPL produces many intermediate nodes and their
complement to make the out put s One pass-transistor network is enough to implement the
logic function; therefore results are generated by a smaller number of transistors and a smaller
input load. When t he transistor gates are oversized the inputs are overloaded and this creates
high capacitance values. Pass-transistor logic has an i n t r i n s i c problem, which is threshold
voltage drop, and output inverters are necessary to guarantee the drivability. CPL is not an
appropriate choice for low power due to its high switching activity of intermediate nodes, high
transistor count, static inverters and overloading of its inputs. Both circuits will be considered for
comparison in this paper.
The other two full-adder designs contain transmission function full adder (TFA) [13,14,19]
and transmission gate full adder (TGA) [13,14,20]. These designs are based on transmission
function theory and transmission gates and have 16 and 20 transistors, respectively.

3. IMPLEMENTING FULL ADDER BY MEANS OF MAJORITY FUNCTION

The Majority Function is a logic circuit that performs as a Majority vote to determine the
output of the circuit. This function has only odd numbers of input and its output is equal to 1
when the number of inputs 1 is more than 0.
Three-input and ve-input Majority Functions have been used in the proposed adder.
Majority Functions with three and ve inputs are illustrated in Fig. 2(a) and (b), respectively.



Fig. 2. Majority Function.
The full-adder operation can b e s t a t e d as follows: given the three inputs A, B and C, it is
desired to calculate two 1-bit outputs, SUM and Cout. Table 1 shows the truth table of Cout, SUM
and three-input Majority Function.
As t he above table s hows , Cout c a n b e implemented with a three-input Majority Function. This
fact is also proposed in Eq. (1)
Cout = AB + AC + BC (1)
If we i n v e r t the output of the circuit, Cout i s produced with Majority Not Function circuit which
is shown in Fig. 3. As Table 1 exhibits, SUM is different in merely two places with Majority Not
F u n c t i o n ; when inputs are 000 or 1 1 1 . Therefore, SUM can be calculated with Cout as shown in
Eq. (2): SUM = Cout(A + B + C) + ABC = Majority (A; B; C; Cout; Cout) (2)
Consequently, according to this fact, SUM is generated by meansof two Majority Not Functions as
illustrated in Fig. 4.
The rst one is a three-input Majority Not Function that makes Cout and the second one is a ve-
input Majority Not Function which creates SUM.










Fig. 3. Majority Not Function. Fig. 4. Majority Function-Based Full Adder



4. NEW MAJORITY FUNCTION-BASED FULL ADDER

In order to create this function, it uses three-input capacitors that prepare an input voltage for
driving the CMOS inverter. There are two ways to make the circuit shown in Fig. 5 working as
a Majority Not Function. The rst method is the transistor sizing that shifts VTC into the left
and right through changing the ratio of (W/L)
n
to (W/L)
p
.
The second method is based on high threshold voltages transistors [1,2431]. For
implementing the Majority Not Function by the circuit shown in Fig. 5, high-V
t
transistors have
been used. The NMOS transistor must be turned on (V
gs
4V
thn
) and the output has to be low
when at least two out of the three inputs are high and vice versa while two or three of inputs
are low. The threshold voltage of the PMOS and NMOS transistors are 0.48 and 0.47 V,
respectively. This method has the benet of a very low P
direct path
(Eq. (3)) and the short-
circuit current. The circuit also is a ratio less one and in addition the energy consumed
per switching activity is better:









Fig. 5. Three-input Majority Not Function. Fig. 6. Output waveforms of the circuit by changing size of transistors


The reason which results in low power dissipation is that the sum of Vtn and V tp is larger than VDD (Eq.
(4)) [1,16]; therefore to calculate the power consumption of this circuit Pdp can be ignored: Although
lowering supply voltage and increasing Vtn and V tp results in decreasing the power consumption,
modifying thresh- old voltages and reducing supply voltage have direct impact on latency of the circuit and as
shown in Eqs. (5) and (6) any increase in Vth or decrease in supply voltage causes reduction in the speed of the
circuit:

In our rst attempt for designing full-adder cell, the Majority Not Function that has been shown in Fig.
5 is used for implementing Cout and then in the next level of the full-adder design as shown in Fig. 7 the
SUM is implemented with a ve- input Majority Not Function. Two capacitors that have been connected to Cout
are parallel; hence, the capacitances of them can be added up. Each successive couple Inverter gates on top of Fig.
7 that provide A, B and C inputs for the ve-input Majority Not Function can be substituted with a new design of
Buffer circuit that is shown in Fig. 8. Fig. 9 offers a new sketch that uses buffer circuit. In practice, there is no need
for any kind of buffer and it can be eliminated. As shown in Fig. 10, the circuit uses only two Inverter gates. Indeed
there are not any general differences in practical environment among the adder cells which produce SUM and Cout
or their inverts [32,33]. The presented











Fig. 7. Full adder cell. Fig. Fig. 8. Buffer circuit.










Fig. 9. Full adder cell. Fig. 10. Proposed full-adder

adder can work reliably without additional inverters but extra inverters enhance the driving capability of the adder
cell.




5. SIMULATION RESULTS AND ANALYSIS

The investigation which includes the seven circuits C-CMOS, CPL, TFA, TGA, 14T, 10T, Hybrid full adder
of Fig. 1 and the proposed adder, has been based on simulation runs on Cadence environment by using a
0.18-mm technology [1]. In this paper, post-layout simulations have been performed. For the seven circuits
that have been shown in the threshold voltages of the NMOS and PMOS transistors are around 0.39 and 0.42 V
but the new full adder uses the high-Vt transistors with 0.47 and 0.48 V for NMOS and PMOS, respectively
[1,2431]. The supply voltage is 0.8 V and since the smallest voltage that 10T can work at it is 1.8 V [1]
furthermore, 14T cannot function under 1.0 V, will results in the supply voltage for them is 1.8 and 1 V,
respectively. By optimizing the transistor sizes of full adders considered, it is possible to reduce the delay of all
adders without signicantly increasing the power consumption, and transistor sizes can be set to achieve
minimum PDP.
5.1. Power comparison

The average power dissipation has been evaluated by applying casual pattern. Simulation results show that the
new design consumes 11%, 31%, 30%, 28% and 8% less power than the C-CMOS, CPL, TFA, TGA and Hybrid.
This is quite clear as the new design has much lower transistor count and has no Vth drop. The simulation results
also exhibit that C-CMOS, TFA, TGA, CPL, Hybrid and the delay degradation in this design is compensated
with the improvement in its power dissipation, leading to a better PDP.

5.2. Immunity to noise

As mentioned in area comparison section, capacitors in the presented adder structure are implemented by means
of MOS transistors. So this new design only consists of MOS transistor hence, it has not any extraordinary
differences as compared with conventional adder circuits and it makes this circuit strong from the noise point of
view. Simulations for delay, power and PDP comparison have been performed at 0.8Vdd supply voltage. The
values of PDP evaluated

6. CONCLUSION

In this paper, a novel low-power Majority Function-based 1-bit full adder has been proposed. The proposed
circuit uses only CMOS inverter and capacitance in its structure resulting in a signicant reduction in power
consumption.In addition,some techniques to improve the speed of the circuit resulted in this new adder beneting
from the best PDP and high performance. Simulation have been performed on Cadence environment and
HSPICE by using a 0.18-mm technology to evaluate the new design and seven other adders, including 28-transistor
complementary CMOS, CPL, TFA, TGA, 14T, 10T and Hybrid. Simulation results show the presented adder has
the best PDP in comparison with the others. This adder consumes 11%, 31% and 8% less power
compared with C-CMOS, CPL and Hybrid. The immunity to noise has been also evaluated in this paper.
Consequently, this new design is appropriate to be applied for construction of large low- power high-performance
VLSI systems and it can work better in the future at higher technology such as 0.13 mm or nano-scaling.

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