Electronix Garage (ESCS Labs), www.escslabs.

com
For more info call : 08802231883 or visit on www.escslabs.com
ESCS Labs, F-2, A. R. Plaza, Greater Noida presents VLSI
DESIGN (front end) short term course on:
DIGITAL DESIGN USING VERILOG HDL (4-weeks)
INTRODUCTION TO VLSI
Need, Scope, Use and History of VLSI.
Introduction to Chip Design Process.
Description of Hardware Description Languages
VLSI Design Flow
Applications of VLSI.
INTRODUCTION TO VLSI DESIGN USING HDLS
Introduction to VLSI, IC, and FPGA.
Chip Design Process (Front-end to Back-end)
Use of HDLs in VLSI design.
VLSI Design Flow.
INTRODUCTION TO Verilog HDL
Need of Verilog HDL.
Special Features of Verilog HDL.
Application of Verilog HDL in Electronics Market and Industries.
Comparison of Verilog HDL and other hardware description language.
DESIGNING WITH Verilog HDL
Design Methodology (Top-Down and Bottom-up)
Design Simulation and Synthesis.
Verilog HDL Design Flow.
Keyword and module description in Verilog HDL
DATA TYPES
Lexical Conventions.
Description of Data types
Scalar and Vector Data Description.
Parameters Description.
Array Description.
MODELING STYLES
Gate level Modeling.
Dataflow modeling.
Behavioral Modeling.
Switch level Modeling.
Mixed level modeling
GATE LEVEL MODELING
Logic Gate Primitive.
Gate Instantiation.
Design RTL from Logic Diagram.
Delays in Gate-Level Design.
DATAFLOW MODELING
Continuous Assignment statement.
Implicit Assignment statement.
Delay types
Expressions.
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Operators.
Operands.
Operator Precedence.
BEHAVIORAL MODELING
Structured Procedural Statements
Always Statements.
Initial Statements.
Blocking Statement.
Non blocking Statement.
Timing Control Statement
Delay Based Timing Control
Event Based Timing Control
Conditional statements
If-else statements.
Case statements
Loops
While loop.
For loop.
Repeat loop.
Forever loop
Block Statements
Parallel block.
Sequential block.
FINITE STATE MACHINE (FSM)
Introduction to FSM.
Mealey Machine.
Moore Machine.
Flip-flops.
Counters.
HARDWARE IMPLEMENATION
Introduction to FPGA and CPLD.
Brief discussion of Hardware kit.
Working on Physical FPGA and CPLD.
Interfacing of LEDs.
7-segment interfacing.
USEFUL MODELING TECHNIQUE
Procedural Continuous Assignment Statement
Assign Statement.
De-assign Statement.
Force Statement.
Release Statement.
SWITCH LEVEL MODELING STYLE
MOS Switches.
Bidirectional Pass Switches.
Resistive MOS Switches
Task and function.
USER DEFINED PRIMITIVES (UDPs)
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Combinational UDPS.
Sequential UDPS.
Verilog Test bench.
Begin-end and fork join.
Logic synthesis.
System Tasks
Compiler Directives
MEMORY MODELING
RAM & ROM designing.
Bi - directional ports.
Case X and Case Z statements.
PROJECTS
Arithmetic and Logical Unit Design.
Shift unit Design.
Memory Design (RAM and ROM)
Arithmetic unit design for Binary and BCD operands
Microprocessor Design



DIGITAL DESIGN USING VHDL (4-weeks)

INTRODUCTION TO VLSI
Need, Scope, Use and History of VLSI.
Introduction to Chip Design Process.
Description of Hardware Description Languages
VLSI Design Flow
Applications of VLSI.
INTRODUCTION TO VLSI DESIGN USING HDLS
Introduction to VLSI, IC, and FPGA.
Chip Design Process (Front-end to Back-end)
Use of HDLs in VLSI design.
VLSI Design Flow.
INTRODUCTION TO VHDL
Need, Scope, Use and History of VHDL.
Applications of VHDL in Market and Industries.
Special Features of this Language.
Discussion of VHDL & other Languages.
DESIGNING IN VHDL
Design Process and Steps.
Design Simulation
Design Synthesis.
Design Methodology
Top Down
Bottom Up
CODE STRUCTURE
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Library Declaration
Entity
Architecture
Configurations
DATA TYPES & DATA OBJECTS IN VHDL
Variables
Constants
Signals
Delta Delay
Operators in VHDL
Shift Operator
Relational Operator
Arithmetic Operator
User-Defined Data Types
Pre-Defined Data Types
Arrays
Record
DATA FLOW MODELING
Keyword description of Dataflow Modeling.
When else statement.
With Select Statement.
BEHAVIORAL MODELING
Process Keyword.
Conditional Statements
If else statement
Case statement
Loops in VHDL
For Loop
While Loop
No Iteration Scheme Loop
Sequential Circuits in Behavioral Modeling
Flip-flops
Counters
Combinational Circuits in Behavioral Modeling
Decoder
Encoder
Multiplexer
Logic gates
Attribute
Signal Attribute
Data Attribute
User-Defined Attribute
Package
Predefined Package
Userdefined Package
Sub programs.
Function
Local Function
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Predefined Function
Procedure.
Local Procedure
Predefined Procedure
NULL Statement
NEXT Statement
EXIT Statement
STRUCTURAL MODELING
Benefits of Structural Modeling.
Components
Component Interfacing
Port Mapping
FINITE STATE MACHINE
Introduction to FINITE STATE MACHINE (FSM).
Moores Machine.
Mealey Machine.
Counters (MOD-3, MOD-5, MOD-7)
Flip Flops using FSM.
SHIFT REGISTERS & MEMORIES
SISO
PIPO
SIPO
PISO
Memory Design
RAM
ROM
HARDWARE INTERFACING
Introduction to FPGA.
Introduction to CPLD.
Brief Description of Hardware KIT.
Working on Physical FPGA & CPLD.
Interfacing of LEDs.
Keypad Scanner
7-Segment interfacing.
Counter on 7-Segment.
LCD Interfacing.
PROJECTS
Design of ALU
Traffic Light Controller
Single way
Four way
Design of Shift Unit
Design of Comparator
Booth Multiplier
MEMORY DESIGN RAM / ROM.
CLOCK DIVIDER RTL Code
Arithmetic unit design for Binary and BCD operands
Microprocessor Design