Beruflich Dokumente
Kultur Dokumente
by
Tarun Vir Singh
2003EE10347
This is to certify that the thesis entitled “Modeling and Simulation of the Threshold
submitted by Tarun Vir Singh to the Indian Institute of Technology, Delhi, for the award
fide work carried out by him under my supervision and guidance. The research reports
and the results presented in this thesis have not been submitted in parts or in full to any
other University or Institute for the award of any other degree or diploma.
2
ACKNOWLEDGEMENTS
I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar for his
invaluable guidance and advice during every stage of this endeavor. I am greatly indebted
to him for his continuing encouragement and support without which, it would not have
been possible for me to complete this undertaking successfully. His insightful comments
I also wish to express my sincere thanks and acknowledgements to all those who directly
We have demonstrated for the first time, the effect of quantum confinement of
results from quantum theory and two-dimensional simulation, we show that strain-
A new analytical model for the threshold voltage (Vth) of fully depleted vertical
equation. Our model includes the effects of strain (Ge mole fraction in SiGe pillar), short-
channel length, pillar diameter, strained silicon thin film thickness, pillar doping, gate
work function and other device parameters. The model correctly predicts a decrease in
threshold voltage with increasing strain in the strained-silicon (s-Si) layer, i.e. with
increasing Ge concentration in the SiGe pillar. The results obtained using our analytical
In order to obtain a more accurate threshold voltage model for the vertical
made during developing the model. In particular, we have tried to include the electron
charge term in the Poisson equation. Although, we could not succeed in our ultimate goal
of deriving an accurate, compact threshold voltage model, the analysis provided a useful
insight into the issues involved in threshold voltage modeling of such devices.
We have demonstrated for the first time, the effect of strain on the conduction
4
we show that for low values of strain, the current flows in the middle of the cylindrical,
i.e. in the SiGe pillar and not in the s-Si layer at the surface. Only for large values of
strain does the current flow through the s-Si layer enabling the mobility enhancement of
carriers. Based on our simulation study, we provide the minimum amount of strain
necessary in a device for the current to flow through the s-Si layer.
5
TABLE OF CONTENTS
CERTIFICATE………………………………………………………………………......2
ACKNOWLEDGEMENTS…………………………………………………………..….3
ABSTRACT…………………………………………………………………………..….4
TABLE OF CONTENTS……………………………………………………………..….6
LIST OF TABLES……………………………………………………………………......8
LIST OF FIGURES………..………………………………………………………….….9
CHAPTER 1……………………………………………………………………………11
INTRODUCTION
1.1 Advantages of Strained-Silicon MOSFETs……………………………...…..11
1.2 Advantages of Double and Cylindrical Gate MOSFETs………………….....11
1.3 Recent Research Relevant to the Problem……………….…………………..11
1.4 Objectives of the Thesis………………………………………………….…..12
1.5 Thesis Organization……………………………………………………..…...12
CHAPTER 2……………………………………………………………………….....…14
THRESHOLD VOLTAGE OPTIMIZATION IN STRAINED-SILICON MOSFETS
USING QUANTUM CONFINEMENT EFFECT
2.1 Introduction……………………………………………………………….….14
2.2 Effect of Quantum Confinement on the Bandgap of Strained-Silicon………15
2.3 Quantum Confinement Simulations……………………………………....….17
2.4 Results and Discussion……………………………………………………....19
2.5 Conclusion………………………………………………………………..….23
CHAPTER 3………………………………………………………………….…………24
COMPACT THRESHOLD VOLTAGE MODEL OF VERTICAL SURROUNDING
GATE STRAINED-SILICON/SiGe MOSFETS
3.1 Introduction…………………………………………………………………..24
3.2 Effect of Strain………………………………………………………….……25
3.3 Simplifying Assumptions……………………………………...…….….…...27
3.4 Threshold Voltage Model…………………………………………….…...…29
6
3.5 Results and Discussion………………………………………………....…...34
3.6 Conclusion…………………………………………………………………..38
CHAPTER 4……………………………………………………………………………40
THRESHOLD VOLTAGE MODELING OF VERTICAL SURROUNDING GATE
STRAINED-SILICON/SiGe MOSFETS WITH CARRIER CHARGE TERM
INCLUDED IN THE POISSON EQUATION
4.1 Introduction……………………………………………………………….…40
4.2 Approach 1………………………………………………………………...…40
4.3 Approach 2……………………………………………………………….…..42
4.4 Conclusion……………………………………………………………...……44
CHAPTER 5……………………………………………………………………………45
EFFECT OF STRAIN ON THE CONDUCTION PATH IN CYLINDRICAL
STRAINED-SILICON MOSFETS
5.1 Introduction……………………………………………………………….…45
5.2 Effect of Strain……………………………………………….…………...…46
5.3 Minimum Required Strain……………………………………………….…..48
5.4 Results and Discussion..………………………………………………..……50
5.5 Conclusions………………………………………………………………….52
CHAPTER 6………………………………………………………………………...…..53
CONCLUSIONS……………………………………………………………………...…53
SCOPE FOR FUTURE WORK…………………………………………………………55
APPENDICES………………………………………………………………..……...….56
REFERENCES…………………………………………………………………………..60
7
LIST OF TABLES
Table Page
2.1 Device parameters used for the simulation of the s-Si MOSFETs. 17
Device parameters used in the model and the simulation of the
3.1 33
vertical, surrounding gate s-Si/SiGe MOSFETs.
Device parameters used for the simulation of the cylindrical s-Si
5.1 50
MOSFETs.
8
LIST OF FIGURES
Figure Page
9
Energy band diagram of the structure in Fig.5.1 (in the radial
5.2 direction, from the centre of the pillar to the surface) for different 47
values of strain x (Ge content in the SiGe film).
Electron concentration profile in the radial direction (from the centre
5.3 48
of the pillar to the surface).
Electron concentration profile in the radial direction at the threshold
5.4 49
point. The amount of strain here is the minimum required strain.
5.5 Variation of minimum required strain with SiGe pillar radius 50
Variation of minimum required strain with strained-Si film thickness
5.6 51
t s − Si
10
CHAPTER 1
INTRODUCTION
Strained-silicon MOSFETs are gaining popularity due to enhanced mobility and high
field velocity [1-3]. Strained-silicon on insulator (SSOI) MOSFETs combine the carrier
transport advantages of s-Si with reduced parasitic capacitance and increased scalability
Scaling down of devices is one of the key methods of enhancing the transistor switching
speed. But device length scaling beyond 100 nm has been seriously impeded by the
increasing short channel effects (SCEs). Several structures have been proposed to
overcome SCEs, with double gate (DG) and cylindrical surround gate MOSFETs being
the most promising concepts [1 - 4]. For an equivalent silicon and gate oxide thickness,
cylindrical MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs
for the same SCEs [5 ]. Cylindrical MOSFETs offer additional advantages of improved
subthreshold slope, higher packing densities, variable pillar doping (along the channel).
11
1.3 Motivation for Present Research
A major concern with s-Si MOSFETs is the decrease in the threshold voltage as strain
increases [6, 7, 8] due to the decrease in the bandgap of s-Si with strain [9]. In this paper,
we show that this effect can be reversed by decreasing the thickness of the s-Si layer,
To incorporate the advantages of both strain and cylindrical MOSFETs, s-Si surround
gate MOSFETs have recently been proposed [9, 10] and have been experimentally
demonstrated [11]. These structures, however, are not yet well investigated. In this paper,
we develop, for the first time, an analytical threshold voltage model by solving two
coupled 2D Poisson equations in s-Si and SiGe and analyze the dependence of the
MOSFETs can be overcome by decreasing the thickness of the s-Si layer to the
quantum regime.
gate s-Si/SiGe MOSFETs, and to verify the results using two dimensional device
simulations.
The dissertation is divided into six chapters and its outline is described as given below.
12
Chapter I: Introduction
This chapter demonstrates that the decrease in the threshold voltage of s-Si MOSFETs
An analytical model for the threshold voltage (Vth) of Nanoscale, Fully Depleted,
Poisson equation. The results obtained using our analytical model are verified using two-
This chapter illustrates some of our attempts to enhance the accuracy of the threshold
voltage model developed in chapter III, by relaxing some of the assumptions made in the
potential derivation.
Chapter V: Conclusions
13
Chapter 2
2.1 Introduction
high field velocity [1-3]. Strained-silicon on insulator (SSOI) MOSFETs combine the
carrier transport advantages of s-Si with reduced parasitic capacitance and increased
A major concern with s-Si MOSFETs is the decrease in the threshold voltage as
strain increases [6, 7, 8] due to the decrease in the bandgap of s-Si with strain [9]. In this
paper, we show that this effect can be reversed by decreasing the thickness of the s-Si
Although quantum confinement effects are well known [10], to the best of our
knowledge its impact on optimizing the threshold voltage of s-Si MOSFETs has not been
studied so far. Using two-dimensional simulation, we demonstrate in this study that the
decrease in the threshold voltage of s-Si MOSFETs with strain can be minimized by
decreasing the s-Si layer thickness. We show that any specified threshold voltage can be
14
2.2 Effect of Quantum Confinement on the Bandgap of s-Si
The s-Si SOI MOSFET structure used in the present study and its associated energy band
diagram in the middle if the channel are shown in Fig. 2.1 and Fig. 2.2 respectively.
Gate
Gate Oxide
n+ s-Si ts-Si n+
Source Drain
SiGe
Y
X
Buried Oxide
Substrate
The s-Si layer forms a quantum well between the two potential barriers formed by the
gate oxide and the SiGe layer. The confinement of electrons into a very thin region
increases the energy gap between allowed energy levels. The difference between energy
levels becomes large enough and they can no longer be considered continuous.
15
SiO2 s-Si SiGe
q=2
q=1
Ec
Eg/ Eg
Ev
q=1
q=2
ΔE g = E g′ − E g
Fig. 2.2: Energy band diagram of the structure in Fig. 2.1 (along the middle of the device
in the Y-direction)
The first energy level in the conduction band is above EC, while the first energy level in
the valence band is below EV. This leads to an increase in the energy bandgap [10]. The
η2 π 2
ΔE g = (2.1)
2mr t s2− Si
1 1 1
where = +
mr me m h
me and mh are the effective masses of the electron and hole respectively, t s − Si is the s-Si
h
layer thickness. Using η = and substituting h = 6.63 × 10 −34 J .s in (1), we get
2π
75
ΔE g = meV (2.2)
mrr t s2− Si
16
mr
where mrr =
m0
ΔE g = −0.4 x (2.3)
where x is the mole fraction of Ge in SiGe. Hence, the overall change in the bandgap of
silicon is given by
⎛ 0.075 ⎞
ΔE g = ⎜⎜ 2
− 0.4 x ⎟⎟eV (2.4)
⎝ mrr t s − Si ⎠
Thus, bandgap increases with decreasing t s − Si and decreases with increasing strain. These
two opposing effects can be used to optimize the threshold voltage of s-Si MOSFETs,
To verify the above theoretical predictions, the 2-D device simulator ATLAS [11] was
used to simulate the structure shown in Fig.1. The parameters used in our simulation are
17
Table 2.1: Device parameters used in the simulation
Parameter Value
Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%)
Strained-Silicon film thickness, ts-Si 2-7 nm
Channel Length, L 50 nm, 100 nm
Source/Drain doping, ND 1019 cm-3
Doping in SiGe layers, NA 1016 cm-3
Doping in s-Si layer, NA 1016 cm-3
Drain bias, VDS 0.05 Volts (50 mV)
Gate Oxide Thickness, t ox 2.0 nm
Work function of gate material, φM 4.8 eV
Poisson’s equations are solved alternately. Once the Schrödinger equation is solved, the
calculated carrier concentration is substituted into the charge part of Poisson’s equation.
The potential derived from the solution of the Poisson’s equation is substituted back into
equations is reached. The electron concentration calculated using the above process is
shown in Fig. 2.3 along the Y-direction in the middle of the device. We notice that the
inversion layer charge is confined to the s-Si layer. To estimate the threshold voltage, we
have used the electron concentration profile along the X-direction plotted at the peak of
electron concentration shown in Fig. 2.3. Threshold voltage is defined as the value of
gate voltage at which the minimum of this concentration profile becomes equal to the
18
1017
Electron Concentration (cm-3) s-Si SiGe
1016
ts-Si = 5 nm L = 100 nm
VDS = 50 mV
VGS = 0.28 V
1015 x = 0.2
1014
1013
1012
0 2 4 6 8 10 12 14 16
Distance (nm)
Fig. 2.3: Electron concentration profile along the middle of the device in the Y-direction.
Fig. 2.4 shows the electron concentration profile from source to drain in the centre of s-Si
layer along X-direction, for s-Si layer thicknesses of 2 nm and 7 nm with a Ge mole
fraction x = 0.4 . The lower electron concentration in the 2 nm s-Si layer device is due to
its higher bandgap caused by quantum confinement effects. This device therefore requires
a higher gate voltage for increasing its carrier concentration to a value high enough for
conduction to take place, thereby increasing its threshold voltage. Therefore, a reduction
19
1020
L = 100 nm
1019 Source VDS = 50 mV Drain
1017 ts-Si = 7 nm
1016
1015 ts-Si = 2 nm
1014
1013
0 10 20 30 40 50 60 70 80 90 100
Position along the Channel (nm)
Fig. 2.4: Electron concentration profile along the middle of the strained-Silicon layer in
the X-direction.
Fig. 2.5 shows the variation in the threshold voltage of the device as a function of
s-Si layer thickness for various values of strain (Ge mole fraction in SiGe) and for two
by equation (4) both for strained-silicon as well as strain free silicon channel. We notice
from Fig. 5 that even for the largest Ge mole fraction ( x = 0.4 ), s-Si MOSFETs with
reasonable threshold voltages can be realized if the thickness of the s-Si layer is reduced
to 2 nm.
20
L = 100nm
x=0 L = 50nm
0.5
Threshold Voltage (volts) VDS = 50 mV
0.4
x = 0.2
0.3
0.2
x = 0.4
0.1
0
2 3 4 5 6 7
s-Si Layer Thickness (nm)
Fig. 2.5: Variation of the threshold voltage with strained-Si film thicknesses for
different values of strain x (Ge content in the SiGe film).
Fig. 2.6 shows the variation in the threshold voltage of the device as a function of
strain for various values of s-Si layer thickness and channel length. The threshold voltage
decreases linearly as strain increases. Threshold voltage roll-off can also be observed as
channel length decreases from 100 nm to 50 nm. Threshold voltage roll-off with
increasing strain and decreasing channel length can both be overcome by decreasing t s − Si .
21
0.6
L = 100nm
L = 50nm
0.5 ts-Si = 2 nm VDS = 50 mV
Threshold Voltage (volts)
0.4
0.3
ts-Si = 4 nm
0.2
0.1 ts-Si = 7 nm
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Strain (%Ge)
Fig. 2.6: Variation of the threshold voltage with strain x (Ge content in the SiGe
film) for different strained-Si film thicknesses.
For two different channel lengths, Fig. 7 shows the various combinations of Ge
mole fraction x and s-Si film thickness t s − Si that results in a particular constant threshold
voltage. We can, therefore, clearly see that the benefits of strained-silicon using higher
Ge mole fraction can still be retained while keeping the threshold voltage reasonably
22
0.45
0.4 L = 100 nm
0.35 L = 50 nm
Strain (%Ge)
VDS = 50 mV
0.3
0.25 VT = 0.3 V
0.2
0.15
VT = 0.4 V
0.1
0.05
0
2 3 4 5 6 7
s-Si Layer Thickness (nm)
Fig. 2.7: The relation between strain x and strained-Si film thickness t s − Si for constant
threshold voltages.
2.5 Conclusions
For the first time, we have examined the effect of s-Si layer thickness on the
reducing the s-Si layer thickness to the quantum mechanical regime, the effective
bandgap of s-Si can be increased counter balancing the reduction in threshold voltage due
to increased strain. This, therefore, permits the designer to realize nanoscale strained-
silicon MOSFETs with good gate control while allowing a higher Ge mole fraction for
23
Chapter 3
3.1 Introduction
Scaling down of devices is one of the key methods of enhancing the transistor switching
speed. But device length scaling beyond 100 nm has been seriously impeded by the
increasing short channel effects (SCEs). Several structures have been proposed to
overcome SCEs, with double gate (DG) and cylindrical surround gate MOSFETs being
the most promising concepts [13 - 16]. For an equivalent silicon and gate oxide thickness,
cylindrical MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs
for the same SCEs [17]. Cylindrical MOSFETs offer additional advantages of improved
subthreshold slope, higher packing densities, variable pillar doping (along the channel).
The second main factor controlling transistor switching speed is the carrier
velocity (or mobility). Strained-Si has been used in recent years to improve carrier
transport properties i.e. mobility and high field velocity [18 - 20].
recently been proposed [21, 22] and have been experimentally demonstrated [23]. These
structures, however, are not yet well investigated. In this paper, we develop, for the first
time, an analytical threshold voltage model by solving two coupled 2D Poisson equations
in s-Si and SiGe and analyze the dependence of the threshold voltage Vth on various
device parameters. The accuracy of the proposed model is verified using two dimensional
24
simulations [11]. We also demonstrate that Vth is not significantly affected by pillar
diameter, thereby allowing higher drive current (large effective W/L ratio) without Vth
roll off.
experiences biaxial strain leading to changes in band structure [21,24]. Due to strain, the
electron affinity of silicon increases and the bandgap decreases. Also the effective mass
[21,24,25]
3/ 2
⎛ N ⎞ ⎛ m* ⎞
(ΔEC ) s − Si = 0.57 x , (ΔEg ) s − Si = 0.4 x , VT ln⎜⎜ V , Si ⎟⎟ = VT ln⎜⎜ *h , Si ⎟⎟ ≈ 0.075 x (3.1)
⎝ NV , s − Si ⎠ ⎝ mh, s − Si ⎠
where x is the Ge mole fraction in Si1-xGex substrate, (ΔEC ) s − Si is the decrease in electron
affinity of silicon due to strain, (ΔEg ) s − Si is the decrease in bandgap of silicon due to
strain, VT is the thermal voltage, NV , Si and NV , s − Si are the density of states in the valence
band in normal and strained silicon respectively, mh*, Si and mh*, s − Si are the hole density of
states (DOS) effective masses in normal and strained silicon, respectively. The band
structure parameters for relaxed Si1-xGex substrate can also be estimated as [12,25]:
(ΔEg ) SiGe = 0.467 x , NV , SiGe = ( 0.6 x + 1.04(1 − x) ) × 1019 cm −3 , ε SiGe = 11.8 + 4.2 x (3.2)
where (ΔEg ) SiGe is the decrease in bandgap of Si1-xGex from that of Si, NV , SiGe is the
density of states in the valence band in relaxed Si1-xGex, and ε SiGe is the permittivity of
Si1-xGex.
25
The flat-band voltage of a MOSFET modified due to strain can be written as [24]
where
− (ΔEC ) s − Si (ΔEg ) s − Si ⎛ N ⎞
(VFB , f ) Si = φM − φSi , ΔVFB , f = + − VT ln⎜⎜ V , Si ⎟⎟ ,
q q ⎝ NV , s − Si ⎠
χ Si Eg , Si ⎛ NA ⎞
φSi = + + φF , Si , φF , Si = VT ln⎜⎜ ⎟.
⎟
q 2q n
⎝ i , Si ⎠
In the above relations, φM is the gate work function, φSi is the unstrained Si work
unstrained Si, Eg , Si is the bandgap in unstrained Si, q is the electronic charge, NA is the
body doping concentration and ni , Si is the intrinsic carrier concentration in unstrained Si.
The built-in voltage across the source-body and drain-body junctions in the strained-Si
Eg , Si − (ΔEg ) s − Si ⎛ N ⎞
where Vbi , Si = + φF , Si , (ΔVbi ) s − Si = + VT ln⎜⎜ V , Si ⎟⎟ .
2q q ⎝ NV , s − Si ⎠
The built-in voltage across the source-body and drain-body junctions in the relaxed Si1-
Eg , Si −(ΔEg ) SiGe ⎛ N ⎞
where Vbi , Si = + φF , Si , (ΔVbi ) SiGe = + VT ln ⎜ V , Si ⎟ .
2q q ⎜N ⎟
⎝ V , SiGe ⎠
26
3.3 Simplifying Assumptions
shown in Fig. 3.1. The co-ordinate system consists of a radial direction r and a vertical
direction z as shown in the figure. The symmetry of the structure ensures that the
potential and hence the electric field have no variation in the θ direction. Thus a two-
n+ Source
SiGe
s-Si s-Si
z
r L
R1
R2
r=0
n+ Drain
Fig. 3.1: Cross-sectional view of the strained-Si vertical surrounding gate MOSFET.
To make an analytical solution possible and to get a closed form expression for Vth , the
the validity of the model needs to be checked by considering the potential at r = 0 and R1
27
3) A parabolic potential is assumed in the radial direction in both SiGe and s-Si [26]. This
is a justified assumption since a uniform charge distribution leads to a linear electric field
and a parabolic potential. However, this assumption may not always be valid at the
channel ends, especially under strain, due to charge injection from source/drain.
4) The centre potential φC (along r = 0 in Fig. 3.1) is determined using 1-D Poisson
equation as follows:-
The 1-D Poisson equation in the radial direction with ε 1 = ε SiGe ≈ ε Si can be written as:
d 2φ qN A
= (3.6)
dr 2 ε1
1) The electric field in the centre of the SiGe pillar ( r = 0 in Fig. 3.1) is zero by
symmetry.
dφ
=0 (3.7)
dr r =0
φ 2 ( R2 ) = φ s (3.8)
2
qN A R2
φC = φ s −
2ε 1
The above analysis is valid only near the middle of the device or for long channel
devices.
28
3.4 Threshold Voltage Model
The 2-D Poisson equation in the strained silicon thin-film and the SiGe pillar, before the
1 ∂ ⎛ ∂φ (r , z ) ⎞ ∂ 2φ (r , z ) qN A
⎜r ⎟+ = (3.9)
r ∂r ⎝ ∂r ⎠ ∂z 2 ε Si
Assuming a parabolic potential distribution in the radial direction, φ in SiGe pillar as well
The Poisson equation in SiGe pillar and s-Si film is solved using the following boundary
conditions:
1) The electric field in the centre of the SiGe pillar ( r = 0 in Fig. 1) is zero by symmetry.
∂φ1
=0 (3.12)
∂r r =0
φ1 (0, z ) = φC (3.13)
∂φ1 ∂φ 2
ε1 = ε2 (3.14)
∂r r = R1 ∂r r = R1
4) Potential at the interface of strained-Si thin film and SiGe substrate is continuous.
φ1 ( R1 , z ) = φ 2 ( R1 , z ) (3.15)
29
5) The surface potential φ s (z ) is a function of z only.
φ 2 ( R2 , z ) = φ s ( z ) (3.16)
∂φ 2
ε2 = C ox (VGS − VFB − φ s ) (3.17)
∂r r=R2
ε ox
where C ox =
t ox
R2 ln(1 + )
R2
qN A ⎡ R2 R1 ⎤ C ox ε
2 2 2
R1
⎢ + − ⎥+ (VGS − VFB − φ s )[ R2 − R1 (1 − 2 )]
2 ⎣ ε2 ε1 ε2 ⎦ ε2 2ε 1
c 23 =
ε
( R2 − R1 )[ R2 − R1 (1 − 2 )]
ε1
C ox
c 22 = (VGS − VFB − φ s ) − 2 R2 c 23
ε2
C ox R2
c 21 = φ s − (VGS − VFB − φ s ) + R2 c 23
2
ε2
d 2φ S ( z )
2
− k 2φ S ( z ) = β (3.18)
dz
where
30
⎡
2C ox ⎛ ε 2 ⎞⎤
⎢ R2 − R1 ⎜⎜1 − ⎟⎟⎥
C ε 2 R2
⎣ ⎝ 2ε 1 ⎠⎦
k 2 = 0x +
ε 2 R2 ⎡ ⎞⎤
(R2 − R1 )⎢ R2 − R1 ⎜⎜1 − ε 2 ⎟⎟⎥
⎛
⎣ ⎝ ε 1 ⎠⎦
⎡R 2 R 2 R 2 ⎤
qN A ⎢ 2 + 1 − 1 ⎥
β =− ⎣ ε2 ε1 ε2 ⎦
− k 2 (VGS − V FB )
⎡ ⎤
(R2 − R1 )⎢ R2 − R1 ⎜⎜1 − ε 2 ⎟⎟⎥
⎛ ⎞
⎣ ⎝ ε 1 ⎠⎦
equation with constant coefficients. It is solved using the following boundary conditions
β
φ s ( z ) = Ae kz + Be − kz − (3.21)
k2
where
β ⎞
⎜Vbi , s − Si + 2 ⎟(1 − e ) + VDS
⎛ − kL
A= ⎝
k ⎠
2 sinh (kL )
β ⎞ − kL
⎜Vbi , s − Si + 2 ⎟(e − 1) − VDS
⎛
B=⎝
k ⎠
2 sinh (kL )
31
dφ s ( z )
=0
dz
β
φ s min = 2 AB −
k2
In conventional MOSFETs, the threshold voltage is defined as the value of the gate
voltage at which φ s ,min = 2φ F , Si where φ F ,Si is the difference between the extrinsic Fermi
level in the bulk region and the intrinsic Fermi level. For the strained-Si MOSFETs, the
− (ΔEg ) s − Si ⎛ N ⎞
where Δφs − Si = + VT ln⎜⎜ V , Si ⎟⎟ .
q ⎝ NV , s − Si ⎠
Hence we can determine the value of threshold voltage by substituting (3.21) into (3.22)
− Vφ 1 + Vφ21 − 4ξVφ 2
Vth = (3.23)
2ξ
where
{
Vφ 1 = 2 d sinh 2 kL − (cosh kL − 1)(2c + V DS ) }
Vφ 2 = 2c(cosh kL − 1)(c + VDS ) − VDS − (d sinh kL )
2 2
32
⎡R 2 R 2 R 2 ⎤
qN A ⎢ 2 + 1 − 1 ⎥
c= ⎣ ε2 ε1 ε2 ⎦
+ V FB , s − Si + Vbi , s − Si
⎡ ⎛ ε 2 ⎞⎤
(R2 − R1 )⎢ R2 − R1 ⎜⎜1 − ⎟⎟⎥ + k 2
⎣ ⎝ ε 1 ⎠⎦
d = c − Vbi , s − Si + φth
To verify the proposed analytical model, the 2-D device simulator ATLAS [16] was used
to simulate the threshold voltage for various device parameters and compared with the
values predicted by the model. We notice that the inversion layer charge is confined to
the s-Si layer. To estimate the threshold voltage, we have used the electron concentration
profile along the X-direction plotted at the peak of electron concentration shown in Fig.
3.2. Threshold voltage is defined as the value of gate voltage at which the minimum of
forming a conducting path. The parameters used in our simulation are given in Table 1.
Parameter Value
Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%)
Strained-Silicon film thickness, ts-Si 2-12 nm
SiGe pillar radius (R2) 15-50 nm
Channel Length, L 30-120 nm
Source/Drain doping, ND 1019 cm-3
Doping in SiGe layers, NA 1016 cm-3
Doping in s-Si layer, NA 1016 cm-3
Drain bias, VDS 0.05 Volts (50 mV)
Gate Oxide Thickness, t ox 2.0 nm
Work function of gate material, φM 4.8 eV
33
1019 • • VGS = 0.25 V
× × VGS = 0 .41 V
1018 ×
•× * * VGS = 0 .50 V
•×
*• ×*
× •*
* • ו •× ×
Electron Conc. (/cm3)
1017 * × • •
• • • •× *
× • • • • • • • × *
* × ×
× × *
× ×
○ ○ *○ ○ ○ ○ ○ ○ × ○
× ×○ ×○ ○ ○ ○ ○ ○* ○ ○
1016 * *
* Background *
1015 *Doping *
* *
* *
1014 *
* *
* * *
* *
1013
1012
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Distance across Device (in Microns)
Fig. 3.2: Electron concentration profile along the channel for three different values of the
gate voltage.
Fig. 3.3 shows the variation of threshold voltage Vth with channel length for
different values of Ge mole fraction x in the SiGe pillar. It is observed that short channel
effects become prevalent below 50 nm channel length are marked by the sharp decrease
in Vth value. This can be explained on the basis of charge sharing from source and drain
which becomes significant for such short channel lengths. Also, the threshold voltage is
34
lower for higher strain for the same channel length. The Vth values from the analytical
model are in close proximity with the simulation results, except for very short channel
lengths. This is because at very short channel lengths, charge carried by electrons
Model R1 = 20 nm
0.5 Atlas R2 = 25 nm
0.45
x=0
0.4
Threshold Voltage (volts)
0.35
0.3 x = 0.2
0.25
0.2
x = 0.4
0.15
0.1
30 40 50 60 70 80 90 100 110 120
Channel Length (nm)
Fig. 3.3: Variation of the threshold voltage with channel length for different values of
strain x (Ge content in the SiGe film).
The variation of threshold with the thickness of the strained-Si thin film is plotted
in Fig. 3.4. As can be seen from the figure, there is no discernible change in threshold
voltage with change in strained-Si film thickness from 2 nm -12 nm. This suggests that
one can allow small variations and tolerances in the fabrication process without affecting
35
the Vth too much. The discrepancy between the Vth values from the analytical model and
from the simulation results is quite small but it increases as the strain increases. This is
because the bandgap of SiGe decreases as Ge content increases. Hence, electron injection
from source/drain into the channel increases making the charge carried by electrons
Model L = 50 nm
Atlas R1 = 20 nm
0.5
0.45 x=0
Threshold Voltage (volts)
0.4
0.35
x = 0.2
0.3
0.25
x = 0.4
0.2
0.15
0.1
0.05
0
2 3 4 5 6 7 8 9 10 11 12
s-Si Film Thickness (nm)
Fig. 3.4: Variation of the threshold voltage with strained-Si film thicknesses for different
values of strain x (Ge content in the SiGe film).
Fig. 3.5 shows the variation of threshold voltage Vth with SiGe pillar radius,
observed that Vth shows negligible variation with pillar radius. Thus, unlike single and
36
double gate MOSFETs, pillar diameter can be increased to achieve higher drive currents
without threshold voltage roll-off. This result is in accordance with experimental results
as reported in [23].
L = 50 nm
Model
R2 – R1 = 5 nm
0.5 Atlas
0.45 x=0
0.4
Threshold Voltage (volts)
0.35 x = 0.2
0.3
0.25
x = 0.4
0.2
0.15
0.1
0.05
0
15 20 25 30 35 40 45 50
SiGe Pillar Radius (nm)
Fig. 3.5: Variation of the threshold voltage with SiGe pillar radius for different values of
strain x (Ge content in the SiGe film).
Fig. 3.6 shows the variation of threshold voltage with change in strain i.e. Ge
mole fraction of SiGe substrate, for channel lengths of 80 nm and 30 nm. The threshold
voltage obtained from the model tracks the simulation values very well for relatively
large channel lengths. It is evident that there is a significant fall in threshold voltage with
37
increasing strain, and the decrease in Vth is almost linear. The threshold voltage decreases
onset of inversion due to decrease in φth (equation (3.22)). Also, it can be seen from the
figure that Vth for L=80 nm is noticeably greater than that for L=30 nm, indicating the
0.5
Model R1 = 20 nm
0.45
Atlas R2 = 25 nm
Threshold Voltage (volts)
0.4
0.35
L = 80 nm
0.3
0.25
0.2
L = 30 nm
0.15
0.1
0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Equivalent Ge Content Strain, x
Fig. 3.6: Variation of the threshold voltage with strain x (Ge content in the SiGe film) for
different channel lengths.
38
3.6 Conclusion
For the first time, we have examined the effect of various device parameters like
strain (Ge mole fraction in SiGe pillar), channel length, strained silicon thin film
thickness, and the pillar radius on the threshold voltage of nanoscale strained-Si/SiGe
equation is solved in the strained-Si thin film using appropriate boundary conditions. The
model results are compared with accurate two-dimensional simulations. The calculated
values of the threshold voltage obtained from the proposed model agree well with the
simulated results except for very small channel lengths and very large values of strain.
This discrepancy is due to the simplifying assumptions made in the analysis in order to
obtain a compact threshold voltage model. There is a significant drop in threshold voltage
with increasing Ge content of the relaxed SiGe pillar and decreasing channel length. The
demonstrated by our results, there are undesirable side effects with increasing Ge content
such as a roll-off in Vth which may affect the device characteristics and performance
significantly. Our compact model accurately predicts the threshold voltage over a large
range of device parameters. Our model is a first step in the accurate modeling of
improved upon by relaxing the assumptions made, by including the charge carried by
electrons in the Poisson equation (this has already been done for unstrained surround gate
MOSFETs [27]).
39
Chapter 4
4.1 Introduction
Vertical, surrounding gate s-Si/SiGe MOSFETs are becoming increasingly popular due to
several of their advantage mentioned in chapter 3. But so far, very little work has been
done on the analytical modeling of this device. In chapter 3, we have developed, for the
first time, a simplified compact threshold voltage model. This derivation was made
carried by electrons in the Poisson equation. In this chapter, we have made attempts at
relaxing this assumption and still obtaining a compact threshold voltage model. Although
we did not achieve total success in our endeavor, but the attempts provide a useful insight
4.2 Approach 1
The structure of the device is shown in Fig. 3.1. The 2-D Poisson equation in the strained
silicon thin-film and the SiGe pillar, before the onset of strong inversion can be written
as:
40
1 ∂ ⎛ ∂φ (r , z ) ⎞ ∂ 2φ (r , z ) q
⎜r ⎟+ = (n + N A ) (4.1)
r ∂r ⎝ ∂r ⎠ ∂z 2
ε Si
n = ni e φ / VT (4.2)
φ ( z, r ) = φ 0 ( z ) + f1 ( z ) f 2 (r ) (4.3)
r only. f 2 (r ) is given by
f 2 (r ) = c1 I 0 (γ r ) + c 2 K 0 (γ r ) (4.4)
conditions, I 0 and K 0 are zeroth order modified Bessel functions of the first and second
applicable in the SiGe pillar as well as the s-Si layer. This is a justified assumption since
the solution given by equation (4.3) is valid independent of the range of values taken by
r . Thus,
φ s − Si (r , z ) = φ1 ( z ) + f1 ( z ){c3 I 0 (γ r ) + c 4 K 0 (γ r )} (4.6)
The Poisson equation (4.1) is solved using the following boundary conditions:
1) The electric field in the centre of the SiGe pillar ( r = 0 in Fig. 1) is zero by symmetry.
41
∂φ1
=0 (4.7)
∂r r =0
2) Potential at the interface of strained-Si thin film and SiGe substrate is continuous.
φ SiGe ( R1 , z ) = φ s − Si ( R1 , z ) (4.8)
∂φ SiGe ∂φ s − Si
ε1 = ε2 (4.9)
∂r r = R1 ∂r r = R1
∂φ s − Si
ε2 = C ox (VGS − VFB − φ s − Si ( R2 , z )) (4.10)
∂r r=R 2
c2 = 0 (4.11)
Using the boundary conditions (4.7) – (4.11), we can determine the constants c1 , c3 , and
c 4 .On doing so, it is found that ci are functions of z , which is not allowed by equations
(4.3) and (4.4). Hence, the ongoing analysis is not a valid one.
4.3 Approach 2
In order to simplify the problem, a one-dimensional analysis of the device is done instead
assumption is valid near the middle of the device and for long channel devices. The 1-D
42
Poisson equation in the strained silicon thin-film and the SiGe pillar, before the onset of
d 2φ 1 dφ q
+ = (n + N A ) (4.12)
dr 2
r dr ε Si
n = ni e φ / VT (4.13)
Equation (4.12) is a second order, non-linear ODE having two independent solutions.
Unfortunately, there is no standard method to solve even this simplified ODE. One
2kT
φ = A− ln( Br 2 + 1) (4.14)
q
where A and B unknown constants. This solution is not the most general solution to
dφ
=0 (4.15)
dr r =0
This boundary condition is satisfied by the potential in the SiGe pillar but not by the
potential in the s-Si layer. Hence, there must exist another independent solution to
equation (4.12), which will give the potential in the s-Si layer. After a tedious analysis,
we did manage to reach to a solution of equation (4.12), but it turned out to be the same
as given by equation (4.14). Hence, the model for the potential in the s-Si layer is still
undetermined.
43
4.4 Conclusion
In this chapter, we have attempted to enhance the accuracy of the threshold voltage
assumptions made earlier. In particular, we have included the electron charge term in the
Poisson equation. Although, we could not succeed in our ultimate goal of deriving an
accurate, compact threshold voltage model, the analysis provided a useful insight into the
44
Chapter 5
5.1 Introduction
Scaling down of devices is one of the key methods of enhancing the transistor switching
speed. But device length scaling beyond 100 nm has been seriously impeded by the
increasing short channel effects (SCEs). Several structures have been proposed to
overcome SCEs, with double gate (DG) and cylindrical surround gate MOSFETs being
the most promising concepts [13 - 16]. For an equivalent silicon and gate oxide thickness,
cylindrical MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs
for the same SCEs [17]. Cylindrical MOSFETs offer additional advantages of improved
subthreshold slope, higher packing densities, variable pillar doping (along the channel).
The second main factor controlling transistor switching speed is the carrier
velocity (or mobility). Strained-Si has been used in recent years to improve carrier
transport properties i.e. mobility and high field velocity [18 - 20].
recently been proposed [21, 22] and have been experimentally demonstrated [23].
However, as we demonstrate in this paper, the amount of strain in such devices must be
difference between lateral and cylindrical MOSFETs. In the former, the current flows
near the surface of the device whereas in the latter (as shown in this paper), the current
45
flows in the centre of the device i.e. in the middle of the pillar. As demonstrated in this
paper, the current can be made to flow at the surface of the pillar through the s-Si layer
provided the amount of strain in the s-Si layer is large enough. Using two-dimensional
simulation, we estimate the minimum amount of strain necessary for the current to flow
through the s-Si layer. We show that the minimum strain required increases as the pillar
experiences biaxial strain leading to changes in band structure [21,24]. Due to strain, the
electron affinity of silicon increases and the bandgap decreases. The effect of strain on Si
where x is the Ge mole fraction in Si1-xGex pillar, (ΔEC ) s − Si is the decrease in electron
affinity of silicon due to strain, and (ΔEg ) s − Si is the decrease in bandgap of silicon due to
strain. A schematic view of a fully depleted cylindrical surround gate strained MOSFET
is shown in Fig. 5.1. The associated energy band diagram from the centre of the pillar to
its surface is shown in Fig. 5.2 for different values of strain. With increasing strain, the
larger electron affinity leads to electron injection from the SiGe pillar into the s-Si layer
and the lower bandgap leads to larger pumping of electrons from the valence band to the
conduction band. Hence, more current flows through the s-Si layer as strain is increased.
46
n+ Source
SiGe
s-Si s-Si
z
r L
R1
R2
r=0
n+ Drain
Fig. 5.1: Cross-sectional view of the strained-Si vertical surrounding gate MOSFET.
x=0
x = 0.1
SiGe s-Si SiO2 x = 0.2
EC
EV
Fig. 5.2: Energy band diagram of the structure in Fig. 5.1 (in the radial direction) for
different values of strain x (Ge content in the SiGe film).
47
Fig. 5.3 depicts the electron concentration across the device from the centre of the
pillar to its surface for different values of strain. For low values of strain, the majority of
the current flows through the SiGe pillar, whereas for high values of strain, the current
1018
s-Si
0 10 20 30 40 50 60 70 80 90
SiGe
Electron Concentration (cm-3)
L = 100 nm
1017 VG = 0.3 V
Background x = 0.3
Doping
1016
x = 0.2
1015
1014
x=0
1013
0 10 20 30 40 50 60 70 80 90
Distance from the centre (nm)
Fig. 5.3: Electron concentration profile in the radial direction (from the centre of the
pillar to the surface).
To determine the minimum amount of strain required to make the current flow through
the s-Si layer, the 2-D device simulator ATLAS [11] was used to simulate the electron
48
concentration profile across the device. The definition used for the minimum required
strain is as follows: the amount of strain such that when the peak electron concentration
in the s-Si layer equals the background doping, the electron concentration in the centre of
the pillar must be 10 times smaller than the background doping. In other words, at the
threshold point of the device, the peak electron concentration in the SiGe pillar must be
10 times smaller than the peak electron concentration in the s-Si layer. This condition is
1018
s-Si
0 10 20 30 40 50 60 70 80 90
SiGe
Electron Concentration (cm-3)
L = 100 nm
17
10 VG = 0.1 V
Background
x = 0.36
Doping
1016
Minimum required
15
10 strain = 0.36
1014
1013
0 10 20 30 40 50 60 70 80 90
Distance from the centre (nm)
Fig. 5.4: Electron concentration profile in the radial direction at the threshold point. The
amount of strain here is the minimum required strain.
49
The parameters used in our simulation are given in Table 5.1.
Parameter Value
Channel Length, L 100 nm
SiGe pillar radius (R1) 30-80 nm
Strained-Silicon film thickness, ts-Si 5-20 nm
Source/Drain doping, ND 1019 cm-3
Doping in SiGe layers, NA 1016 cm-3
Doping in s-Si layer, NA 1016 cm-3
Drain bias, VDS 0.05 Volts (50 mV)
Gate Oxide Thickness, t ox 2.0 nm
Work function of gate material, φM 4.8 eV
Fig. 5.5 shows the variation of minimum required strain, x with the SiGe pillar
radius. It is observed that the amount of strain necessary to make the current flow through
0.4
Minimum Required Ge Content Strain, x
0.35 L = 100 nm
ts-Si = 10 nm
0.3
0.25
0.2
0.15
0.1
0.05
0
30 35 40 45 50 55 60 65 70 75 80
SiGe Pillar Radius (nm)
Fig. 5.5: Variation of minimum required strain with SiGe pillar radius
50
This happens because for larger radii, much more electrons must be transferred from the
thick pillar to the s-Si layer. Thus, thick cylindrical s-Si MOSFETs must employ a large
amount of strain.
Fig. 5.6 shows the variation of minimum required strain, x with s-Si film
thickness, t s − Si for different values of SiGe pillar radius. It is observed that minimum
0.4
L = 100 nm
0.35
Minimum Required Ge Content Strain, x
Pillar radius = 80 nm
0.3
0.25
0.2
Pillar radius = 50 nm
0.15
0.05
0
5 10 15 20
s-Si Film Thickness (nm)
Fig. 5.6: Variation of minimum required strain with strained-Si film thickness t s − Si
51
5.5 Conclusions
For the first time, we have examined the effect of strain on the conduction path in
cylindrical strained-silicon MOSFETs using 2-D simulation. We have shown that in order
to be effective, the amount of strain in cylindrical s-Si MOSFETs must be above a certain
minimum value. Only then will the current flow occur through the s-Si layer, enabling the
52
Chapter 6
Conclusions
The work presented in this thesis can be divided into two categories, namely, (1)
confinement effect, and (2) Modeling and simulation of the threshold voltage of vertical,
In chapter 2 of the thesis, we have examined the effect of s-Si layer thickness on
the threshold voltage of strained-silicon MOSFETs using simulation. We have shown that
by reducing the s-Si layer thickness to the quantum mechanical regime, the effective
bandgap of s-Si can be increased counter balancing the reduction in threshold voltage due
to increased strain. This, therefore, permits the designer to realize nanoscale strained-
silicon MOSFETs with good gate control while allowing a higher Ge mole fraction for
In chapter 3, we have examined the effect of various device parameters like strain
(Ge mole fraction in SiGe pillar), channel length, strained silicon thin film thickness, and
the pillar radius on the threshold voltage of nanoscale strained-Si/SiGe surrounding gate
MOSFETs by developing an analytical model. The 2-D Poisson equation is solved in the
strained-Si thin film using appropriate boundary conditions. The model results are
threshold voltage obtained from the proposed model agree well with the simulated results
except for very small channel lengths and very large values of strain. There is a
53
significant drop in threshold voltage with increasing Ge content of the relaxed SiGe pillar
and decreasing channel length. The increase in strain, i.e. Ge content, enhances the
in the carrier mobility. However, as demonstrated by our results, there are undesirable
side effects with increasing Ge content such as a roll-off in Vth which may affect the
model developed in chapter 4, by including the electron charge term in the Poisson
equation. Though, we could not succeed in our ultimate goal of deriving an accurate,
compact threshold voltage model, the analysis provided a useful insight into the issues
cylindrical s-Si MOSFETs. We have shown that for small values of strain, the channel is
formed in the middle of the device in the SiGe pillar. For larger values of strain, the
channel shifts to the s-Si layer at the surface. We have also shown that as the pillar
diameter increases, the amount of strain necessary to shift the currrent flow to the surface
increases.
54
Scope for Future Work
1 The structures studied in this thesis can be fabricated. Experimental results can be
2 Accurate threshold voltage models for vertical, surrounding gate s-Si/SiGe MOSFETs
may be derived by the inclusion of the carrier charge term in the Poisson equation.
55
APPENDIX A
go atlas
#
mesh space.mult=1.0
# Specify the mesh
x.mesh loc=0.00 spac=0.002
x.mesh loc=0.2 spac=0.002
#
y.mesh loc=0.000 spac=0.0001
y.mesh loc=0.004 spac=0.0001
y.mesh loc=0.0045 spac=0.002
y.mesh loc=0.032 spac=0.002
y.mesh loc=0.0325 spac=0.02
y.mesh loc=0.232 spac=0.02
56
doping uniform conc=1e16 p.type regions=4
doping uniform conc=1e16 p.type regions=5
doping uniform conc=1e19 n.type regions=6
doping uniform conc=1e19 n.type regions=7
method carriers=0
method Newton
solve init
57
APPENDIX B
go atlas
#
mesh cylindrical space.mult=1.0
#
x.mesh loc=0 spac=0.002
x.mesh loc=0.05 spac=0.002
x.mesh loc=0.051 spac=0.001
x.mesh loc=0.06 spac=0.001
x.mesh loc=0.0602 spac=0.0002
x.mesh loc=0.062 spac=0.0002
#
y.mesh loc=0 spac=0.001
y.mesh loc=0.07 spac=0.001
#
region num=1 material=Air
region num=2 x.min=0 x.max=.06 y.min=0 y.max=.01 material=Silicon
region num=3 x.min=0 x.max=.06 y.min=.06 y.max=.07 material=Silicon
region num=4 x.min=0 x.max=.05 y.min=.01 y.max=.06 material=SiGe x.comp=0.2
region num=5 x.min=.05 x.max=.06 y.min=.01 y.max=.06 material=Silicon
region num=6 x.min=.06 x.max=.062 y.min=.01 y.max=.06 material=SiO2
#
contact name=gate workfunction=4.8
contact name=drain neutral
contact name=source neutral
58
material region=5 affinity=4.284 eg300=1.00
mobility region=5 mumaxn.cvt=2409
save outfile=sim.str
tonyplot sim.str
method newton
output ex.field ey.field con.band val.band qfn qfp
solve init
59
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