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Circuit Design Laboratory: Digital Design (SS 14)

Prof. Dr.-Ing. W. Krautschneider
Instructors: Dr.-Ing. Paola Vega-Castillo / Dipl.-Ing. Aljoscha Reinert

Lab Document No.2:

Introduction to Design Synthesis

1. What is synthesis?

Once the RTL description of a digital system is coded and its functionality is verified by
means of simulation, the HDL description has to be translated into an actual netlist. The
process of converting the RTL description into a netlist for a given target technology is called
synthesis. To produce the synthesized netlist, the synthesis tools require the RTL code, the
cell libraries and the design constraints. The cell libraries provide information about all the
available cells, including connectivity and functionality, timing, area, corresponding symbol,
among others. The design constraints include maximum permissible area and timing-
constraints. In this laboratory, the synthesis tool RTL Compiler in Cadence (RC) is going to
be applied. In the rest of this handout, youll find basic information about the use of RTL
Compiler and the simulation of the synthesized design.

2. Basic steps in the synthesis script

Figure 1: RTL Compiler Work Flow

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The synthesis flow commands are usually grouped in a scripting file that is executed by the
rc. The basic steps included in the synthesis script are illustrated in figure 1, and will be
quickly presented in the following paragraphs. This summary is intended to be just a guide
for further investigation of the literature. For more information about RTL Compiler and other
Cadence tools, you can use the Cadence Online Documentation by typing cdnshelp in the
rc tool.

2.1 Set search paths and target library

In order to synthesize the design, some technology libraries have to be specified. These
libraries can be found in specified search paths. The search paths should be written in the rc
start script. There are several search paths:

Library search path: contains the paths to the cells that are going to be used to implement
the design. These libraries exist in the Kit of the target technology.

HDL search path: contains the path to the HDL files

The target technology libraries must then be set.

2.2 Load HDL files

The Load read_hdl command reads HDL files into the RTL compiler. The RTL compiler
reads the HDL files and performs a syntax checks. HDL files contain design information,
such as structural code or RTL implementations.

2.3 Performing elaboration

Elaboration is only required for top level design. During elaboration RTL compiler performs
the following tasks:
Builds data structures
Infers registers in the design
Performs high level HDL optimizations, such as dead code removal
Checks semantics

At the end of elaboration, RTL compiler displays any unresolved reference (immediately after
the key words Done elaborating). After elaboration, RTL compiler has an internally created
data structure for the whole design so you can apply constraints and perform other operation.
For more information about elaboration please refer to the rc documentation.

2.4 Applying design constraints

The design constraints include:
Operating conditions
Clock waveforms
I/O timing

Timing constraints include definition of the input and output delays, specify wire-load models
(Wireload models (WLM) are statistical models used to estimate the interconnect delays
during pre-layout simulation, and are provided by the technology vendors.), defining a clock,
creating a clock, among others.




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2.5 Applying optimization constraints

The RTL Compiler offers the following optimizations:
Remove designer-created hierarchies (ungrouping)
Create additional hierarchies (grouping)
Synthesize a sub-design
Create custom cost groups for paths in the design to change the synthesis cost
function

2.6 Performing synthesis

After constraints an optimization are set for your design, you can proceed with synthesis by
issuing the synthesize command. Synthesis is performed in two steps:
Synthesize the design to generic logic (RTL optimizations are performed in this step)
Map to the technology library and perform incremental optimization

The goal of optimization is to provide the smallest possible implementation of the scheduled
design that satisfies the timing requirements.

2.7 Analyzing the synthesis results

After synthesizing the design you can generate reports on the timing, area, gate selection
and other log files. These reports help you decide on the fulfillment of the constraints of the
design.

2.8 Writing out files for place and route

The last step in the flow involves writing out gate-level netlist and the SDC file for processing
in your place and route tool. The write commands write output to standard out.
Only two representations of the gate-level netlist are relevant to RTL compiler:
Mapped gate-level netlist
RTL Compiler generic library mapped netlist

To create a gate-level netlist that is not technology specific, type the following command:
rc:> write_hdl generic > generic_rtl.v
To create a gate-level netlist file containing the optimized, technology specific gate-level
netlist type:
rc:> write_hdl > file_net.v

3. Timing violations

There are two types of timing violations:

a) Set up violations: In a setup violation, the data is not traveling from the launch edge to the
capture edge quickly enough. You can increase the clock period to push the capture edge
out in time, giving the path enough time to reach the capture edge. The design runs,
although at a reduced speed.

b) Hold violations: In a hold violation, the data arrives at the capture flip-flop before the clock
pulse does. The same clock edge (or synchronously related clock edges) arrives at both
flip-flops at about the same time. The hold violation persists no matter how you adjust the
clock period. You must fix the hold violation or the design will not function...

As a recommendation for better understanding Design Compilers timing report, read about
set up and hold timing slack calculations. This will help you to understand the information of
your timing report in order to fix your design and make it achieve the timing specifications.
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4. Using NCLaunch

An alternative way to compile, test and simulate your designs is the use of the Cadence tool
NCLaunch. To run NCLaunch, do the following steps:
Open a shell
Source ams.csh
Go to your work directory
Start NCLaunch
> nclaunch

This will open a window where you can choose between different choices:
Multiple Step
Single Step
Help
Exit

Choose Multiple Step and the NCLaunch Design Directory configuration window will appear.
Just click OK to continue with default settings. You can change your library settings later if
you want to.

The left side of NCLaunch GUI is a file explorer, while the right side shows you your
compiled or simulated designs.
With the Toolbar on the top you are able to compile, elaborate and simulate your designs to
check their functionality.

5.1 Verifying hardreg.v with NCLaunch

To quickly verify the functionality of a design, it is much faster and comfortable to use
NCLaunch than typing all commands in a shell.

Make sure that you have copied the following files to your work directory:

http://www.et5.tu-harburg.de/Studium/Praktikum/Circuit_Design_digital/Scripte/hardreg.v

http://www.et5.tu-harburg.de/Studium/Praktikum/Circuit_Design_digital/Scripte/harddrive.v

Source ams.csh and change to your work directory, afterwards start NCLaunch. If this is your
first time starting NCLaunch, select multiple step and keep the default design directory
settings by pressing OK.

In the file explorer window (left side of the GUI) the two files hardreg.v and harddrive.v
should appear. If not, make sure that you copied them into your work directory or browse to
the corresponding folder.

To compile the file hardreg.v, select it in the file explorer and click the second button in the
tools bar (Launch Verilog compiler with current selection). In your design explorer (right side)
new designs will appear. If you cant see it, press the plus sign left to your work library
(default: worklib, marked with a lightbulb) to see all compiled designs.

There are two new designs visible, flop and harddrive. They match the module names from
your herdreg.v file. In case there where errors while compilation, these will be displayed in
the log window below.

If you want to change the contents of your file, just right click on it in the file explorer and
choose edit. An editor window will appear, you can now modify the contents of the chosen
file. If you change the contents, make sure that you recompile your files. All changed
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modules are marked with a symbol in the design explorer, so you dont have to recompile all
designs.

After compiling the hardreg.v file, do the same with the harddrive.v file. Make sure that you
keep this order, as a simple compilation of the harddrive.v file can lead to an error, because it
will use modules that are unknown at the moment of compilation.

After compilation three modules are visible in the work library, flop, harddrive and hardreg.
To elaborate the design, select the module harddrive (on the right side) and click the third
button in the tools bar (Launch Elaborator with current selection).

The Snapshot folder now contains a new snapshot, named after your work library and your
elaborated module (default: worklib.harddrive:module).

To simulate that snapshot, select it and press the fourth button of the tools bar, Launch
Simulator with current selection. A simvision window will appear and allow you to view the
simulation. Send all signals you want to observe to the waveform window and press the play
button to start the simulation.

6. Becoming familiar with RTL Compiler

A simple script example has been made available to you to introduce you to the basic
synthesis steps. In order to use RTL Compiler, please follow the procedure presented below:
Open a shell
source ams.csh
go to your work directory
make a new design directory
> mkdir HardReg
For the next step you have to open the following links and save the files into the
HardReg directory.
http://www.et5.tu-
harburg.de/Studium/Praktikum/Circuit_Design_digital/Scripte/verilog_to_netlist.tcl
http://www.et5.tu-
harburg.de/Studium/Praktikum/Circuit_Design_digital/Scripte/hardreg.v
Open the verilog_to_netlist.tcl in a text editor and go through the commands there to
understand what steps the compiler is going to implement.
Start the RTL Compiler by entering the following:
> rc gui
Source the RTL-Script by clicking File Source script and choose
verilog_to_netlist.tcl

Now you have synthesized the design and you can take a look at the schematic of the design
in the Cadence Encounter RTL Compiler gui interface.

7. Verifying the synthesized netlist

In order to verify the design functionality, simulation of the Verilog code before synthesis was
performed. Once the design is synthesized, simulation of the synthesized netlist is required
in order to verify its functionality and correct any mismatch between simulation and
synthesis. For prelayout timing verification, refer to timing reports.

To simulate your synthesized netlist, follow the steps presented below:
Copy your netlist (hardreg_net.v) to your work directory
Open your synthesized netlist by typing nedit hardreg_net.v
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To add a `timescale directive in the first line of the file, (that is, previous to the module
definition), type `timescale 1ns / 1ps
Note: This directive must be identical to that used in the stimuli file, you can copy it
from the harddrive.v file.

Save and close the file hardreg_net.v.

Copy the following files to your work directory:
http://www.et5.tu-harburg.de/Studium/Praktikum/Circuit_Design_digital/Scripte/udp.v
http://www.et5.tu-
harburg.de/Studium/Praktikum/Circuit_Design_digital/Scripte/c35_CORELIB.v
These files contain information about primitives and gates that are used to build your design.
They are basically Verilog files for the most basic parts used in your design (e.g. inverters or
gates etc.).

Open NCLaunch and browse to your work directory so that you see the following files:
udp.v
c35_CORELIB.v
hardreg_net.v
harddrive.v

Compile these files in the order given above. Make sure that you did not compile
hardreg.v, as this is still the original file!

You will now have a lot of modules in your design library, as you compiled all the primitives
from udp.v and c35_CORELIB.v.

Elaborate your design (harddrive) and simulate it

8. Apply correct delays to your netlist simulation

After verifying that your design is still working, you can now start to check the timing of your
design. Do the following to add real gate delays to your design:

Edit harddrive.v and enter $sdf_annotate("hardreg.sdf", h1, , "annotation.log");after
the initial block, but before $shm_open
This command now uses the delays given in the hardreg.sdf file to simulate the timing of
your modules.
Do a netlist simulation just as described in Verifying the synthesized netlist. After
opening NCLaunch make sure that you change the following setting:
o Click Tools Elaborator in NCLaunch
o Click advanced options and open the Annotation Tab
o Choose Specify delay types and set it to maximum
You will see afterwards, that small delays have been added to your gates. Zoom in to see the
single bits switch.