ISCAS 2000 - IEEE International Symposiumon Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

CMOS VCO-PRESCALER CELL-BASED DESIGN FOR

RF PLL FREQUENCY SYNTHESIZERS
A. Ahmed, K. Sharaf*, H. Haddara, H. E Ragai*
Mentor Graphics Egypt
51 Beirut St., Heliopolis, Cairo, Egypt.
* Ain Shams Univ., Faculty of Engineering
1 Sarayat St., Abassiya, Cairo, Egypt.
ABSTRACT
Cell-based design using a new D-latch is employed to design a
VCO and prescaler for RF PLL frequency synthesizers using a
standard 0.5pm CMOS process and 3.3V supply. The divide-by 641
65 dual-modulus prescaler has a maximum operating frequency of
1.6 GHz and dissipates 9 mW. The VCO is a single-stage ring
oscillator with a maximum frequency of 2.2 GHz and consumes 20
mW. The VCO and prescaler combination operates at a maximum
frequency of 1.6 GHz and consumes 56 mW.
1. INTRODUCTION
The frequency synthesizer acts as one of the challenging RF blocks
that is frequently implemented using a phase-locked loop (PLL), Fig. 1.
The high frequency components of the loop are the voltage-controlled
oscillator (VCO) and the prescaler. In this paper, a cell-based design
approach has been used to design an RF CMOS differential prescaler
and VCO using a standard 0.5pm CMOS process and a 3.3V supply.
A new D-latch is proposed and compared with a conventional static
D-latch when used in a divide-by 2 circuit. The designed VCO is a sin-
gle-stage ring oscillator capable of operating at a maximum frequency
of 2.2 GHz. The same cell is used to build a divide-by 64/65 dual-mod-
ulus prescaler and VCO combination operating at a maximum fre-
quency of 1.6 GHz and consumes 56 mW. Further improvement of
performance is expected when using an optimized layout since the sim-
ulations use over-estimated areas for the drain and source of the
devices. Section 2 describes the cell-based approach and the circuit
details of the proposed D-latch. Sections 3 and 4 detail the design of
the prescaler and VCO respectively displaying rhe simulation results
and design performance.
I
N
I high frequency
Ctrl
Figure 1. Frequency synthesizer block diagram
2. CELL-BASED DESIGN
2.1 Approach
Studying the frequency synthesizer block diagram one realizes that
several blocks may be designed based on a single cell, a D-latch. The
prescaler is basically a high frequency divider that may be built using
amaster-slaveDFF while the VCO (if implemented as aring oscillator)
uses delay cells in aring. If we realize that a D-latch when enabled may
be used as a delay cell it is clear that we can base our prescaler and VCO
designs on a high performance D-latch cell. Advantages of such an
approach include decreasing design time since the insight and experi-
ence gained in designing one block is re-used in another. This approach
is also expected to improve the layout of the complete chip and may
also open way to partially automating the layout.
2.2 Proposed D-Latch
In designing monolithic frequency synthesizers, there is always
great concem for the noise generated by the digital circuitry that can
adversely affect the spectral purity of the RF output. To minimize this,
all circuits need to be differential. A low power high-speed D-latch is
targeted to fulfill requirements of the RF blocks.
The proposed D-latch circuit is shown in Fig. 2 and has differential
inputs Din and DinB and outputs Q and QB. A single clock CLK is
needed and is used to enable and disable the latch. When CLK is high,
Fig. 2b, the latch is enabled and the inputs Din and DinB operate on
M1 and M2 respectively switching ON one and OFF the other. Intemal
nodes db and d will be charged to Din and DinB respectively with the
help of M3 and M4 which arecross-coupled resulting in positive feed-
back between d anddb thus decreasing the transition time. The outputs
Q and QB are charged through transistor switches M9 and M10 that
are ON since CLK is high. Transistors M5 and M6 are also cross-cou-
pled to help charge and discharge the output nodes faster. It is to be
noted that M3 and M4 use CLK as their positive supply while M7 and
M8 use CLK as their negative supply and so play no role when CLK
is high and are removed during analysis.
When CLK is low, Fig. 2c, the switch-transistors M9 and M10 are
OFF so are M3 and M4 and so these transistors areremoved during the
analysis. This results in the disconnectionof the input of the latch from
the output and transistors M7 and M8 are now ON using the low CLK
as their negative supply. The group of transistors M5, M6, M7 and M8
will hold the data on the output nodes Q and QB as well as act as the
output drivers to the following stage. The cross-coupling of M7 and
0-7803-5482-6/99/$10.00 02000 IEEE
11-737
(a) (b)
Figure 2. (a) Proposed D-latch circuit, (b) D-latch when CLK=l and (c) D-latch when CLK=O.
M8 will act to amplify the differential voltage between Q and QB and
due to the positive feedback will force the outputs to one of the
extremes. This will help improve the speed of the D-latch since during
the high state of CLK, Q and QB do not have to reach the maximum
swing. It is sufficient to generate a differential voltage big enough for
M5, M6, M7 and M8 to force Q and QB to their extreme values.
In designing the D-latch it can be seen that to preserve the symmetry
in the topology one must constrain the size of the transistors such that
the left side transistors are of the same size as the right side. Further-
more, a constant ratio between the PMOS and nMOS transistors will
be assumed for a balanced contribution such that (WL)3,5 / (WL)l,7
=r, which is chosen according to the process used. Since one of the
targets is to maximize the operating frequency, the minimum channel
length will always be used. In fact, all transistors will be a multiple of
the minimum area device geometry. This leaves us with three design
parameters to change and optimize the latch performance by:
b =(W/L)1/ ( WL ) ~n (EQ 1 )
In optimizing the latch performance one will look for a minimum
delay between the output and input for maximum frequency operation.
However, there are two delays: the first is the delay from the data input
Din and DinB to the outputs Q and QB. The second is the delay from
enablingof the latch CLK high until outputs Q and QB follow the avail-
able data Din and DinB. The first delay is the one encountered when
using the cell as a delay in aring oscillator while the second is the delay
of importance when using the D-latch in the prescaler.
3. DUAL-MODULUS PRESCALER
3.1 Divide-by 2 Circuit Design
The proposed D-latch cell described earlier will be used to build a
master-slave DFF. The dimensions of the transistors will be chosen to
voo
T
QB a
CLK=O
Figure 3. D-latch used in a divide-by 2 circuit connected.
minimize the delay of the DFF when configured for divide-by 2 and
loaded by a D-latch (Fig. 3). It is found through multiple simulations
that minimum delay is achieved when transistors M5, M6, M7 and MS
have minimum dimensions. This leaves us with two parameters to
reach minimum delay, s and b. Fig. 4 shows curves of the delay time
between the input CLK and Q (Q=Din), against b for different values
of S. It has been realized that the minimum of each curve satisfies the
condition b=s and this acts as the envelope of the family of curves as
shown in the figure. The minimum of this curve gives the required set
of design parameters and results in a maximum input clock frequency
of 2.15 GHz and apower dissipation of4.9 mW using a standard 0.5pm
CMOS technology. Fig. 5 shows the input and output wavehnns of
the divider at the maximum frequency. For comparison a conventional
single-ended static D-latch implementation exhibits a maximum fre-
quency of 1.37 GHz and apower dissipation of 2.18 mW while the pro-
posed D-latch dissipates only 1 .I 2 mW.
3.2 Prescaler Design
The functional block diagram of a divide-by 64/65 dual-modulus
prescaler is shown in Fig. 6. The prescaler is composed of two main
blocks: a divide by 4/5 block and a divide-by 16 block. The former is
a synchronous divider built using three high-speed DFFs that may be
configured to divide the input clock by 4 or 5 using the control signal
ctrl-45. The second divider is asynchronous and uses four DFFs each
configured as a TFF thus dividing its input by 2. The specifications of
the second four DFFs can be relaxed since the frequency now is lower.
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Figure 4. Delay curves of the divider for different values of s and b.
Figure 6. Divide-by 64/65 dual-modulus prescaler schematic.
on the number of identical stages N and the delay of each tde[ and is
given by:
f,,, =1 12.N. tdet (EQ 4)
Figure 5. Input and output waveforms of the divide-by 2 circuit.
Proper operation requires timely arrival of the ctrl-45 signal which will
be derived from the outputs of the low frequency asynchronous divider.
This is achieved by deriving the ctrl-45 signal from the AND gate
closer to the input of the low frequency divider which will be waiting
for only one signal, Q4, to go high. The maximum frequency of oper-
ation of the prescaler will be dependent on the total delay of the high-
speed DFF and NAND gate.
The proposed D-latch was used to build the prescaler. The high-
speed DFFs were implemented using the set of parameters giving min-
imum delay from the curve in Fig. 4 while the other DFFs were imple-
mented using lower values to decrease power dissipation. A maximum
operating frequency of 1.6 GHz was attained at a power dissipation of
9 mW.
4. VOLTAGE-CONTROLLED
OSCILLATOR
4.1 Single-Stage Ring Oscillator
An important block in the frequency synthesizer is the VCO. This
block is usually implemented either using LC-tanks [I ], [3], [4] or a
ring of delays [ 2] , [5]. The former compared to the latter has superior
phase-noise performance but more difficult to design, has asmaller tun-
ing range and uses a larger area. The oscillation frequency is dependent
For a higher oscillation frequency it is then beneficial to decrease
tdel and N. The minimum possible delay will be dependent on the delay
cell circuit while the minimum possible N is in fact one [5]. Using a
single-stage ring oscillator will decrease the transistor count and results
in lower power consumption and noise. However, as the number of
stages decrease the phase contribution of each stage increases and it
becomes more difficult to achieve oscillation [5]. Using a single stage
requires a phase shift of 180Ofromthis stage and unity loop gain to be
satisfied simultaneously. As the delay of the stage decreases this con-
dition will not be met and will act as a limiting factor for the oscillation
frequency.
4.2 VCO Design
The D-latch cell described earlier, when enabled, is used as a delay
stage. Since transistors M7 and M8 will always be OFF they are
removed from the design. To control the delay of the cell, and in turn
the frequency of the VCO, a control voltage is applied on the gates of
transistors M9 and MI 0 which act as voltage-controlled resistors
between node sets (d and db) and (Q and QB) respectively. The delay
of the first set of nodes is not affected much by the control voltage while
the second set is; as the control voltage decreases M9 and M10 will be
delayed in switching ON and will have a higher equivalent resistance
resulting in a longer delay. Fig. 7 shows the complete VCO circuit.
Choosing the transistor dimensions for maximum oscillation fre-
quency is achieved by scanning the design space. For each value of s,
the parameters a and b are changed resulting in a set of families of
curves where each curve represents the variation of b for a constant
value of a. As parameter b is decreased, the oscillation frequency
increases until the delay of the cell is too low to fulfill the oscillation
condition and oscillation stops. This is clearly seen in the plot of the
oscillation frequency versus b as a sharp decay of the frequency after
11-739
f
Power Consumption (mW)
Technology
5. CONCLUSION
20 (max.)
ClVlOS i
36
0.8Fm 5V 0 . 6 ~ m 3V 0.5pni 3.3V
CMOS CMOS
OUT 0-
Vcont
Max. Frequency (GHz) 1.45
@
N2 t-
1.6 1.6 1
---D OUTB
Figure 7. VCO using a single-stage ring oscillator.
reaching the peak. Fig. 8 shows aplot ofthe VCO oscillation frequency
versus the parameter b. Each curve in the figure represents the best in
its family (constants and a). From the results it is found that the VCO
has a maximum frequency of 2.2 GHz and dissipates 20 mW.
S=3. A d S-4, A 4 *S=S,A=7 S=6, A=9 S=7, A=l l OS = & A=13
S=9, A=14 S-10, A=16 *S=l l , A=17
- 1 2 4
I
b
Figure 8. Oscillation frequency for different values of a, b and s.
Fig. 9 shows the variation of oscillation frequency with control volt-
age for typical and extreme temperatures. The mid-range temperature
coefficient is 2900 ppd0C over a temperature range of -40-85OC. The
VCO has excellent linearity and a wide tuning range (600 MHz - 2.2
GHz) with a gain of 977 MHz/V. The designed VCO has been used to
drive the divide-by 64/65 dual-modulus prescaler through a high-speed
buffer. The combination operates from 600 MHz to 1.6 GHz and dis-
sipates 56 mW.
oTemp=-4(PC*Temp=25CtT~p~oC
1.9 2.0 2.1 2.4 21 2 8 3.0 32 3.3
Vcont (V)
Figure 9. VCO transfer function at different temperatures.
This paper presents acell-based design approach of a VCO and dual-
modulus prescaler using a D-latch cell. The proposed D-latch was used
in a divide-by 2 circuit and operated at a maximum frequency of 2.15
GHz dissipating 4.9 mW. A divide-by 64/65 prescaler and VCO were
designed using the same cell and multiple simulations were used to
choose optimum transistor dimensions. Table 1 shows a summary of
the designed VCO and prescaler performance along with comparison
with reported work. A disadvantage of the proposed latch is its need
to sink and source current from its input during switching. This resulted
in a need of a strong buffer between the VCO and prescaler that. con-
sumes a considerable portion of the pverall power. A drawback of the
VCO is its higher temperature coefficient compared to [l] and [2]. Per-
formance may be further improved using an optimized layout since the
simulations used over-estimated drain and source areas. A cell-based
approach will help achieve this target as the optimized cell layout is
re-used.
Table 1. VCO andprescaler performance summary andcomparison.
Spec. I 121JSSC97 I 111JSSC98 I T h i s v ? A
I
vco
I
1 VCORange(GHz) I 0 6 - 1 0 I 1 6 9 - 1 8 1 I 0 6 - 2 2 I
I VCOGain(MHzN) I 290 I 40 I 917 I
I Temp.Cceff. (ppmPC) I 1200 I 430 I 2900 I
Prescaler
Division Factor 64/65
Power Consumption (mW)
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