Vsim Snippet

# do simulate_mti.
do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Reading c:\Modeltech_pe_edu_10.2b\modelsim.ini
# "work" maps to directory ./work. (Default mapping)
# // ModelSim PE Student Edition 10.2b May 17 2013
# //
# // Copyright 1991-2013 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# // NOT FOR CORPORATE OR PRODUCTION USE.
# // THE ModelSim PE Student Edition IS NOT A SUPPORTED PRODUCT.
# // FOR HIGHER EDUCATION PURPOSES ONLY
# //
# vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L work -L secureip -L unisi
ms_ver -voptargs=\"+acc\" -t 1ps work.board glbl
# Loading work.board
# Loading work.xilinx_pci_exp_ep
# Loading unisims_ver.IBUFDS
# Loading unisims_ver.IBUF
# Loading work.pci_exp_64b_app
# Loading work.PIO
# Loading work.PIO_EP
# Loading work.PIO_EP_MEM_ACCESS
# Loading work.EP_MEM
# Loading unisims_ver.RAMB36
# Loading unisims_ver.ARAMB36_INTERNAL
# Loading work.PIO_64_RX_ENGINE
# Loading work.PIO_64_TX_ENGINE
# Loading work.PIO_TO_CTRL
# Loading work.pcie_endpointblkplus
# Loading work.pcie_ep_top
# Loading work.pcie_top_wrapper
# Loading work.pcie_clocking
# Loading unisims_ver.PLL_ADV
# Loading unisims_ver.BUFG
# Loading unisims_ver.PCIE_EP
# Loading unisims_ver.PCIE_INTERNAL_1_1
# Loading secureip.PCIE_INTERNAL_1_1_SWIFT
# Loading work.prod_fixes
# Loading work.pcie_mim_wrapper
# Loading work.bram_common
# Loading work.pcie_gt_wrapper_top
# Loading work.pcie_blk_if
# Loading work.pcie_blk_ll
# Loading work.pcie_blk_plus_ll_tx
# Loading work.pcie_blk_ll_tx_arb
# Loading work.pcie_blk_ll_tx
# Loading unisims_ver.LUT6
# Loading work.pcie_blk_plus_ll_rx
# Loading work.tlm_rx_data_snk
# Loading work.tlm_rx_data_snk_mal
# Loading work.tlm_rx_data_snk_pwr_mgmt
# Loading work.tlm_rx_data_snk_bar
# Loading work.cmm_decoder
# Loading work.pcie_blk_ll_oqbqfifo
# Loading work.sync_fifo
# Loading work.pcie_blk_ll_arb
# Loading work.pcie_blk_ll_credit
# Loading work.my_SRL16E
# Loading work.pcie_blk_cf
# Loading work.pcie_blk_cf_mgmt
# Loading unisims_ver.LUT5
# Loading work.pcie_blk_cf_err
# Loading work.cmm_errman_cor
# Loading work.cmm_errman_cnt_en
# Loading work.cmm_errman_ftl
# Loading work.cmm_errman_cpl
# Loading work.cmm_errman_ram4x26
# Loading work.cmm_errman_ram8x26
# Loading work.pcie_blk_cf_arb
# Loading work.pcie_blk_cf_pwr
# Loading work.pcie_soft_cf_int
# Loading work.cmm_intr
# Loading work.extend_clk
# Loading work.xilinx_pcie_2_0_rport_v6
# Loading work.pcie_2_0_rport_v6
# Loading unisims_ver.FDCP
# Loading work.pcie_reset_delay_v6
# Loading work.pcie_clocking_v6
# Loading unisims_ver.MMCM_ADV
# Loading work.pcie_2_0_v6_rp
# Loading unisims_ver.PCIE_2_0
# Loading work.pcie_pipe_v6
# Loading work.pcie_pipe_misc_v6
# Loading work.pcie_pipe_lane_v6
# Loading work.pcie_gtx_v6
# Loading work.gtx_wrapper_v6
# Loading work.pcie_bram_top_v6
# Loading work.pcie_brams_v6
# Loading work.pci_exp_usrapp_rx
# Loading work.pci_exp_usrapp_tx
# Loading work.pci_exp_usrapp_cfg
# Loading work.pci_exp_usrapp_com
# Loading work.pci_exp_usrapp_pl
# Loading work.sys_clk_gen
# Loading work.sys_clk_gen_ds
# Loading work.glbl
# Loading unisims_ver.RAMB36SDP
# Loading work.pcie_gt_wrapper
# Loading work.TX_SYNC_GTP
# Loading work.reset_logic
# Loading unisims_ver.SRL16E
# Loading work.GTX_TX_SYNC_RATE_V6
# Loading unisims_ver.GTXE1
# Loading work.pcie_bram_v6
# Loading unisims_ver.FD
# Loading unisims_ver.GTP_DUAL
# Loading secureip.GTP_DUAL_FAST
# ** Warning: (vsim-3017) ../../example_design/xilinx_pci_exp_ep.v(289): [TFMPC]
- Too few port connections. Expected 66, found 65.
#
# Region: /board/xilinx_pci_exp_ep/app
# ** Warning: (vsim-3722) ../../example_design/xilinx_pci_exp_ep.v(289): [TFMPC]
- Missing connection for port 'cfg_turnoff_ok_n'.
#
# ** Warning: (vsim-3017) ../../source/pcie_endpointblkplus.v(480): [TFMPC] - To
o few port connections. Expected 96, found 88.
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0
# ** Warning: (vsim-3015) ../../source/pcie_endpointblkplus.v(480): [PCDPC] - Po
rt size (7 or 7) does not match connection size (32) for port 'gt_daddr'. The po
rt definition is at: ../../source/pcie_ep.v(340).
#
rt size (1 or 1) does not match connection size (32) for port 'gt_den'. The port
definition is at: ../../source/pcie_ep.v(341).
#
rt size (1 or 1) does not match connection size (32) for port 'gt_dwen'. The por
t definition is at: ../../source/pcie_ep.v(342).
#
rt size (16 or 16) does not match connection size (32) for port 'gt_di'. The por
t definition is at: ../../source/pcie_ep.v(343).
#
# ** Warning: (vsim-3722) ../../source/pcie_endpointblkplus.v(480): [TFMPC] - Mi
ssing connection for port 'trn_pfc_nph_cl'.
#
ssing connection for port 'trn_pfc_npd_cl'.
#
ssing connection for port 'trn_pfc_ph_cl'.
#
ssing connection for port 'trn_pfc_pd_cl'.
#
ssing connection for port 'trn_pfc_cplh_cl'.
#
ssing connection for port 'trn_pfc_cpld_cl'.
#
ssing connection for port 'trn_rfc_cplh_av'.
#
ssing connection for port 'trn_rfc_cpld_av'.
#
# ** Warning: (vsim-3017) ../../source/pcie_clocking.v(160): [TFMPC] - Too few p
ort connections. Expected 28, found 10.
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0/pcie_blk/clocking_i/use_p
ll/pll_adv_i
# ** Warning: (vsim-3722) ../../source/pcie_clocking.v(160): [TFMPC] - Missing c
onnection for port 'CLKFBDCM'.
#
onnection for port 'CLKOUT4'.
#
onnection for port 'CLKOUT5'.
#
onnection for port 'CLKOUTDCM0'.
#
#
#
#
#
#
onnection for port 'DO'.
#
onnection for port 'DRDY'.
#
onnection for port 'CLKIN2'.
#
onnection for port 'DADDR'.
#
onnection for port 'DCLK'.
#
onnection for port 'DEN'.
#
onnection for port 'DI'.
#
onnection for port 'DWE'.
#
onnection for port 'REL'.
#
# ** Warning: (vsim-3017) ../../source/pcie_top.v(2001): [TFMPC] - Too few port
connections. Expected 278, found 277.
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0/pcie_blk/pcie_ep
# ** Warning: (vsim-3015) ../../source/pcie_top.v(2001): [PCDPC] - Port size (1
or 1) does not match connection size (32) for port 'L0CFGDISABLESCRAMBLE'. The p
ort definition is at: C:/Xilinx/13.2/ISE_DS/ISE/verilog/src/unisims/PCIE_EP.v(20
4).
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0/pcie_blk/pcie_ep
# ** Warning: (vsim-3722) ../../source/pcie_top.v(2001): [TFMPC] - Missing conne
ction for port 'LLKTXCONFIGREADYN'.
#
# ** Warning: (vsim-3017) ../../source/bram_common.v(170): [TFMPC] - Too few por
t connections. Expected 28, found 16.
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0/pcie_blk/pcie_mim_wrapper
_i/bram_tl_tx/genblk1/generate_tdp2[0]/ram_tdp2_inst
# ** Warning: (vsim-3722) ../../source/bram_common.v(170): [TFMPC] - Missing con
nection for port 'CASCADEOUTLATA'.
#
nection for port 'CASCADEOUTLATB'.
#
nection for port 'CASCADEOUTREGA'.
#
nection for port 'CASCADEOUTREGB'.
#
nection for port 'DOPA'.
#
nection for port 'DOPB'.
#
nection for port 'CASCADEINLATA'.
#
nection for port 'CASCADEINLATB'.
#
nection for port 'CASCADEINREGA'.
#
nection for port 'CASCADEINREGB'.
#
nection for port 'DIPA'.
#
nection for port 'DIPB'.
#
#
_i/bram_tl_tx/genblk1/generate_tdp2[1]/ram_tdp2_inst
#
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_i/bram_tl_rx/genblk1/generate_tdp2[0]/ram_tdp2_inst
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_i/bram_tl_rx/genblk1/generate_tdp2[1]/ram_tdp2_inst
#
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#
# ** Warning: (vsim-3015) ../../source/pcie_blk_plus_ll_rx.v(339): [PCDPC] - Por
t size (1 or 1) does not match connection size (32) for port 'td_ecrc_trim_i'. T
he port definition is at: ../../source/tlm_rx_data_snk.v(212).
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0/pcie_blk_if/ll_bridge/rx_
bridge/snk_inst
# ** Warning: (vsim-3017) ../../source/pcie_blk_ll_oqbqfifo.v(266): [TFMPC] - To
o few port connections. Expected 14, found 11.
#
# Region: /board/xilinx_pci_exp_ep/ep/pcie_ep0/pcie_blk_if/ll_bridge/rx_
bridge/fifo_inst/bq_fifo
# ** Warning: (vsim-3722) ../../source/pcie_blk_ll_oqbqfifo.v(266): [TFMPC] - Mi
ssing connection for port 'mark_addr'.
#
ssing connection for port 'clear_addr'.
#
ssing connection for port 'rewind'.
#
# ** Warning: (vsim-3017) ../dsport/gtx_wrapper_v6.v(556): [TFMPC] - Too few por
#
# Region: /board/RP/rport/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0]/GTX
# ** Warning: (vsim-3722) ../dsport/gtx_wrapper_v6.v(556): [TFMPC] - Missing con
nection for port 'RXDLYALIGNMONENB'.
#
# ** Warning: (vsim-3722) ../dsport/gtx_wrapper_v6.v(556): [TFMPC] - Missing con
nection for port 'TXDLYALIGNMONENB'.
#
# ** Warning: (vsim-3015) ../dsport/pcie_2_0_rport_v6.v(2977): [PCDPC] - Port si
ze (72 or 72) does not match connection size (69) for port 'mim_tx_wdata'. The p
ort definition is at: ../dsport/pcie_bram_top_v6.v(83).
#
# Region: /board/RP/rport/pcie_2_0_i/pcie_bram_i
ze (72 or 72) does not match connection size (69) for port 'mim_tx_rdata'. The p
#
ze (72 or 72) does not match connection size (68) for port 'mim_rx_wdata'. The p
#
ze (72 or 72) does not match connection size (68) for port 'mim_rx_rdata'. The p
#
# ** Fatal: Attempting to load -nodebug design unit.
# Nodebug designs are not supported.
#
# Time: 0 ps Iteration: 0 Instance: /board File: ../board.v
# FATAL ERROR while loading design
# Error loading design
Error loading design

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# do simulate_mti.

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