Sie sind auf Seite 1von 11

# Lecture 6

Inner product

Multiplication

n-1

p=ax

s=

n-1

x(i) y(i) =

p(i)

i=0

i=0

n-1

S=

x(i)

x(i) [0..2k-1]

i=0

Smin = 0

Smax = n (2k-1)

## # of bits of S = log2 (Smax + 1)

= log2 (n (2k-1) + 1)

log2 n 2k =

= k + log2 n

a2 b2

an-1 bn-1
cn

FA

cn-1

...

c3

FA

a1 b1
c2

s2

sn-1

FA

a0 b0
c1

s1

FA

c0

s0

cn

a2 b2 c2

a1 b1 c1

a0 b0 c0

FA

...

FA

FA

FA

sn-1 cn-1

s3 c3

s2 c2

s1 c1

s0

Example
24 23 22 21 20

x
y
z

0 1 0 1 0
1 1 0 1 1
1 0 1 1 1

0 0 1 1 0
s
c 1 1 0 1 1

x+y+z = s + c

in dot notation

in dot notation

## Carry-save adder for four operands

x3 x2 x1 x0
y3 y2 y1 y0
z3 z2 z1 z0
w3 w2 w1 w0
s3 s2 s1 s0
c4 c3 c2 c1
w3 w2 w1 w0
c4 s3 s2 s1 s0
c4 c3 c2 c1
S5 S4 S3 S2 S1 S0

c4

c4

s3

c3

s3

c3

s2

c2

s2

s1

s1

c2

c1

c1

s0

s0

z

x
4

CSA
c

CSA
s

c
CPA
S

## Carry-save adder for six operands

CSA tree

Implementation of
one-bit slice

## Tree of carry save adders reducing

seven numbers to two

six-bit numbers
in dot notation

k-bit numbers:
block diagram

Latency
LatencyCSA =

Tree height
for n operands

Widths

CSA

k .. k + log2 n

CPA

k + log2 n

typically
close to k bits

## Parameters of tree carry-save adders (2)

Maximum number of inputs that can be reduced
to two by an h-level tree, n(h)
n(0) = 2
n(h) = 3 n(h-1)
2
n(1) = 3
n(2) = 4
n(3) = 6

n(4) = 9
n(5) = 13
n(6) = 19

## Parameters of tree carry-save adders (3)

Smallest height of the tree carry save adder
for n operands, h(n)
2
n
3

h(n) = 1 + h

h(2) = 0

h(n) log 3
2

( 2n )

## Wallace vs. Dadda Trees

Wallace trees
Reduce the size of the final Carry Propagate Adder (CPA)
Optimum from the point of view of speed
Reduce the cost of the carry save tree
Optimum (among the CSA trees) from the point of
view of area

## 5-to-3 Parallel Counter

24 23 22 21 20

0
a
1
b
1
c
1
d
1
e
0
s0
0 1
s1
s2 1 0 0

1
1
0
0
1

0
0
1
1
1

1
1
1
1
1

0
1
1
1
1

1 1 1 0
1 0 0
1 1

a+b+c+d+e = s0+s1+s2

## Implementation of 1-bit of 5-to-3 parallel counter

using single CLB slice of a Virtex FPGA
S2

d
c
b

LUT G

d
c
b

S1
0

LUT F

S0

## Carry Save Adder vs. 5-to-3 Parallel Counter

a
w

c
w

d e
w w

a
w

b
w

CSA

d
w

e
w

PC
s1

s2

CSA

s0

CSA

CSA

CPA

CPA

w
y=a+b+c+d+e mod 2w

y=a+b+c+d+e mod 2w

## Generalized Parallel Counters

Multicolumn
reduction

(5, 5; 4)-counter
Unequal
columns

## Fig. 8.17 Dot notation for a (5, 5; 4)-counter

and the use of such counters for reducing five
numbers to two numbers.

## Generalized parallel counter =

Parallel compressor
(2, 3; 3)-counter

10

x(i6) + x(i7)
x(i1)
compute
Delay

x(i)

Delays

s (i12)

+ x(i1)

x(i)
x(i4)

+ x(i5)

11