What are FPGAs?

FPGAs are programmable digital logic chips. What that means is that you can program
them to do almost any digital function.

Here's the general workflow when working with FPGAs:
You use a computer to describe a "logic function" that you want. You might draw
a schematic, or create a text file describing the function, doesn't matter.
You compile the "logic function" on your computer, using a software provided by
the FPGA vendor. That creates a binary file that can be downloaded into the
FPGA.
You connect a cable from your computer to the FPGA, and download the binary
file to the FPGA.
That's it! Your FPGA behaves according to your "logic function".
Keep in mind that
You can download FPGAs as many time as you want - no limit - with different
functionalities every time if you want. If you make a mistake in your design, just
fix your "logic function", re-compile and re-download it. No PCB, solder or
component to change.
The designs can run much faster than if you were to design a board with discrete
components, since everything runs within the FPGA, on its silicon die.
FPGAs lose their functionality when the power goes away (like RAM in a
computer that loses its content). You have to re-download them when power goes
back up to restore the functionality.
Who makes FPGAs?
There are (at least) four companies making FPGAs in the world. The first two (Xilinx and
Altera) hold the bulk of the market.
Xilinx invented FPGAs and is the biggest name in the FPGA world.
Altera is the second FPGA heavyweight, also a well-known name.
Lattice and Actel are smaller players.
Xilinx

Xilinx has traditionally been the density and technology leader. Their general philosophy
is to be very open about their devices architecture and to provide lots of (useful) features
at the cost of a bit more complexity.
Altera

Altera's focus is on ease of use, with an HDL software suite that has traditionally been
very good. Their silicon has a bit less features and their architecture is not as open.
FPGAs vs. CPLDs
Are FPGAs and CPLDs the same thing? No
Both are programmable digital logic chips and are made by the same companies. But they
have different characteristics.
FPGAs are "fine-grain" devices - that means that they contain a lot (up to 100000)
of tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices - they
contain relatively few (a few 100's max) large blocks of logic with flip-flops.
FPGAs are RAM based - they need to be "downloaded" (configured) at each
power-up. CPLDs are EEPROM based - they are active at power-up (i.e. as long
as they've been programmed at least once...).
FPGAs have special routing resources to implement efficiently arithmetic
functions (binary counters, adders, comparators...). CPLDs do not.
In general, FPGAs can contain large digital designs, while CPLDs can contain small
designs only.
FPGAs vs. microcontrollers
Are FPGAs and microcontrollers the same thing? No
FPGAs implement programmable logic elements running in a parallel fashion.
Microcontrollers are based on a CPU architecture (executes a set of instructions in
a sequential manner).
Microcontrollers have on-chip peripherals that also execute in parallel with their CPU.
But they are still much less configurable than FPGAs.


How FPGAs work
Logic-cells
FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A
logic-cell is basically a small lookup table ("LUT"), a D flip-flop and a 2-to-1 mux (to
bypass the flip-flop if desired).

The LUT is like a small RAM that can implement any logic function. It has typically a
few inputs (4 in the drawing above), so for example an AND gate with 3 inputs, whose
result is then OR-ed with another input would fit in one 4-input LUT.
Interconnect
Each logic-cell can be connected to other logic-cells through interconnect resources
(wires/muxes placed around the logic-cells). Each cell can do little, but with lots of them
connected together, complex logic functions can be created.

IO-cells
The interconnect wires also go to the boundary of the device where I/O cells are
implemented and connected to the pins of the FPGAs.

Dedicated routing/carry chains
In addition to general-purpose interconnect resources, FPGAs have fast dedicated lines in
between neighboring logic cells. The most common type of fast dedicated lines are "carry
chains". Carry chains allow creating arithmetic functions (like counters and adders)
efficiently (low logic usage & high operating speed).

Older programmable technologies (PAL/CPLD) don't have carry chains and so are
quickly limited when arithmetic operations are required.
For more info on carry chains, check this page.

Internal RAM
In addition to logic, all new FPGAs have dedicated blocks of static RAM distributed
among and controlled by the logic elements.

Internal RAM operation
There are many parameters affecting RAM operation. The main parameter is the number
of agents that can access the RAM simultaneously.
"single-port" RAMs: only one agent can read/write the RAM.
"dual-port" or "quad-port" RAMs: 2 or 4 agents can read/write. Great to get data
across clock domains (each agent can use a different clock).
Here's a simplified drawing of a dual-port RAM.

To figure out how many agents are available, count the number of separate address buses
going to the RAM. Each agent has a dedicated address bus. Each agent has also a read
and/or a write data bus.
Writing to the RAM is usually done synchronously. Reading is usually done
synchronously but can sometimes be done asynchronously.
Blockram vs. Distributed RAM
Now there are two types of internal RAMs in an FPGA: blockrams and distributed
RAMs. The size of the RAM needed usually determines which type is used.
The big RAM blocks are blockrams, which are located in dedicated areas in the
FPGA. Each FPGA has a limited number of these, and if you don't use them, you
"loose" them (they cannot be used for anything but RAM).
The small RAM blocks are either in smaller blockrams (Altera does that), or in
"distributed RAM" (Xilinx does that). Distributed RAM allows using the FPGA
logic-cells as tiny RAMs which provides a very flexible RAM distribution in an
FPGA, but isn't efficient in term of area (a logic-cell can actually hold very few
bits of RAM). Altera prefers building different size blockrams around the device
(more area efficient, but less flexible). Which one is better for you depends on
your FPGA application.

FPGA pins
FPGAs tend to have lots of pins... So to make it a little simpler, let's put them into two
bins: "user pins" and "dedicated pins".
User pins
The user pins are called "IOs", or "I/Os", or "user I/Os", or "user IOs", or "IO pins", or ...
you get the idea.
IO stands for "input-output".
You usually have total control over user IOs. They can be programmed to be
inputs, outputs, or bi-directional (i.e. with tri-statable buffers).
Each IO pin is connected to an "IO cell" inside the FPGA. The "IO cells" are
powered by the VCCIO pins (IO power pins) - more details below.
Dedicated pins
The "dedicated pins" are hard-coded to a specific function. They fall into the three
following sub-categories.
Power pins.
Configuration pins: used to "download" the FPGA.
Dedicated inputs, or clock pins: these are able to drive large nets inside the FPGA,
suitable for clocks or signals with large fan-outs.
The power pins fall into two categories: "core voltage" and "IO voltage".
The core voltage is named "VCC" for Xilinx and "VCCINT" for Altera. It is fixed
(set by the model of FPGA that you are using). It is used to power the logic gates
and flip-flops inside the FPGA. The voltage was 5V for older FPGA generations,
and is coming down as new generations come (3.3V, 2.5V, 1.8V, 1.5V, 1.2V and
even lower for the latest devices).
The IO voltage is named "VCCO" for Xilinx and "VCCIO" for Altera. It is used
to power the I/O blocks (= pins) of the FPGA. That voltage should match what
the other devices connected to the FPGA expect.
An FPGA has many VCCIO pins that may be all powered by the same voltage. But new
generations of FPGAs have a concept of "user IO banks": the IOs are split into groups,
each having its own VCCIO pins. That allows using the FPGA as a voltage translator
device, useful for example if one part of your board works with 3.3V logic, and another
with 2.5V.

Clocks and Global lines
An FPGA design is usually "synchronous". Simply put, that means that the design is
clock based and each clock rising edge allows all the D flip-flops to simultaneously take
a new state.
In a synchronous design, a single clock may drive a lot of flip-flops. That can cause
timing and electrical problems inside the FPGA. To get that working properly, FPGA
manufacturers provide special internal wires called "global routing" or "global lines".
They allow distributing the clock signal all over the FPGA with a low skew (i.e. the clock
signal appears almost simultaneously to all the flip-flops).
Most FPGA designs use at least one clock that is generated outside the FPGA and then
fed to the FPGA through one pin. Just make sure you use a clock pin (only them have the
ability to drive global lines).
Clock domains
An FPGA can use multiple clocks (using multiple global lines and clock pins). Each
clock forms a "clock domain" inside the FPGA.
Flip-flops and combinatorial logic in each clock domain
For each flip-flop inside the FPGA, its clock domain is easy to determine. Just look at the
flip-flop clock input.
But what about the combinatorial logic that sits in between flip-flops?
If there is some combinatorial logic in between "same clock domain" flip-flops,
the logic is said to be part of the clock domain too.
If there is some combinatorial logic in between "different clock domains" flip-
flops, the logic is not owned by any clock domain. But in a typical FPGA design,
there is no such logic; the only paths from different clock domains are
synchronizers.
Clock domain speeds
For each clock domain, the FPGA software will analyze all flop-to-flop paths and give
you a report with the maximum allowed frequencies. In the general case, only the paths
from within each clock domains are analyzed. The synchronizer paths (from different
clock domains) usually don't matter and are not analyzed.
One clock domain may work at 10MHz, while another may work at 100MHz. As long as
each clock uses a global line, and you use clock speeds that are lower than the maximums
reported by the software, you don't have to worry about internal timing issues, the design
is guaranteed to work internally timing-wise.
There may still be some timing issues from the FPGA input and output pins though. The
software will give you a report about that. See also the next section.
Signals between clock domains
If you need to send some information across different clock domains, special
considerations need to apply.
In the general case, if your clocks have no relationship with one another, you cannot use a
signal generated from one clock domain into another as-is. Doing so would violate setup
and hold flip-flop timings (in the destination clock domain), and cause metastability.
Crossing clock domains requires special techniques, like the use of synchronizers (that's
simple), or FIFOs (that's more complicated). See the Crossing clock domains project to
get some practical ideas, plus Interfacing Two Clock Domains and What Is
Metastability?.

FPGA download cables
FPGA vendors provide many ways to "configure" (i.e. download) their devices. One way
uses a cable that connects your PC to the FPGA board. These cables are usually called
"JTAG cables" (because they can connect to the JTAG pins of the FPGA).
FPGA cables are vendor specific
The FPGA configuration interface from all the FPGA vendors are very much alike. That
doesn't prevent each vendor to have their own proprietary connectors and cables.
The complete list of Xilinx cables can be found here.
o The most popular one is the Platform Cable USB II (and its PDF).
o Xilinx parallel cable is called Parallel cable III. See also the cables
Hardware user guide.

The complete list of Altera cables can be found here.
o The most popular one is the USB-Blaster.
o Altera parallel cable are the ByteBlasterMV and ByteBlaster II.
Parallel cables
Parallel cables connect to PCs parallel (printer) ports. They are less popular than USB
cables but can still be interesting due to their simplicity. They buffer a few pins of the PC
parallel interface, and connect to the target board using a flat cable or flying leads.
Parallel cables are active devices and need power, but they are usually powered from the
target FPGA board.
FPGA vendors sometime provide the schematic of the cables, which is valuable if you
want to understand how they work or build a cable yourself.

FPGA configuration
An FPGA can be into 2 states: "configuration mode" or "user mode".
When an FPGA wakes up after power-up, it is in configuration mode, sitting idle with all
its outputs inactive. You need to configure it.
Configuring an FPGA means downloading a stream of 0's and 1's through some special
pins. Once the FPGA is configured, it goes into "user-mode" and becomes active.
There are three classical ways to configure your FPGA:
You use a "JTAG cable" from your PC to the FPGA, and run a software on your
PC to send data through the cable.
You use a microcontroller on your board, with an adequate firmware to send data
to the FPGA.
You use a "boot-PROM" on your board, connected to the FPGA, that configures
the FPGA automatically at power-up (FPGA vendors have such special boot-
PROMs in their catalogs).
During development, the first method is the easiest and quickest. Once your FPGA
design works, you probably don't need the PC anymore, so the other two methods come
into use.
Configuration works in surprisingly identical ways between Xilinx and Altera devices.
The differences are mostly in the naming (pin names and modes of operation are named
differently), but the functionality is similar.
Most FPGAs have two sets of pins dedicated to configuration:
The JTAG interface.
The "synchronous serial" interface.
FPGA configuration can quickly become a complex subject, so you might want to skip
this section, especially if you intend to use an already-made FPGA development board.
Development boards usually come with a JTAG cable, or a special cable that you can use
with no knowledge of the underlying interface. But if you want to learn a little more,
read-on.
The JTAG interface (or JTAG "port")
FPGAs have the ability to be configured through JTAG (using proprietary JTAG
commands). Note that JTAG was originally designed for test and manufacturing purposes
(to allow a computer to take control of the device pins). FPGAs are certainly JTAG-
testing able too.
See here for more info.
The "synchronous serial" interface
It is a simple data/clock interface. It is synchronous and you usually provide one bit at a
time to the FPGA.
Here's a description of the five most important pins of this interface:
Xilinx
pin
name
Altera pin
name
Direction Pin function
data data0
FPGA
input
configuration data bit
clk dclk
FPGA
input
configuration clock (the configuration data bit is
shifted in the FPGA at the clock rising-edge)
prog_b nConfig
FPGA
input
When asserted (i.e. when it goes low - this is an active
low pin), the FPGA is reset-ed and looses its
configuration. If the FPGA was in user-mode, it stops
operation immediately, and all IOs become inactive.
init_b nStatus
FPGA
output
This pin indicates when the FPGA is ready to start the
configuration process (it takes a few milliseconds for
the FPGA to get ready).
done ConfDone
FPGA
output
When high, indicates that the FPGA is configured (i.e.
in user-mode).
Note: the init_b and done pins are actually open-collector pins, so pull-up resistors are
required on these. Also if multiple FPGAs are to be configured, these pins are usually
connected together so that all the FPGAs switch into "user-mode" together. There is
many more details, so for a complete description, check your FPGA datasheet.