Expt.No.

: Operational Amplifier Applications

Date:

Aim:
To design an inverting amplifier, Non-inverting amplifier, summer,
Comparator, Integrator and Differentiator using Operational Amplifier.

Apparatus Required:

Sl.No. Components Range Quantity
1 Op Amp LM741 1

2

Resistors
1K, 10K
30K
1
3
3 Capacitor 10F, 0.1F 1
4 CRO 0-25MHz 1
5 Function Generator 0-1MHz 1
6 Breadboard - 1
7 Connecting wires - As required
8 IC Trainer Kit/Breadboard - 1

Theory:

The op-amp is basically a differential amplifier having a large voltage
gain, very high input impedance and low output impedance. The op-amp has
a "inverting" or (-) input and "non-inverting" or (+) input and a single output.
The op-amp is usually powered by a dual polarity power supply in the range
of + 5 volts to + 22 volts.

INVERTING AMPLIFIER:
The op-amp is connected using two resistors R
1 and
R
f
such that the
input signal is applied in series with R
1
and the output is connected back to
the inverting input through R
f
. The non-inverting input is connected to the
ground reference or the center tap of the dual polarity power supply. In
operation, as the input signal moves positive, the output will move negative
and vice versa. The amount of voltage change at the output relative to the
input depends on the ratio of the two resistors R
1
and R
f
. As the input moves
in one direction, the output will move in the opposite direction, so that the
voltage at the inverting input remains constant or zero volts in this case. If R
1
is 1K and R
f
is 10K and the input is +1 volt then there will be 1 mA of
current flowing through R
1
and the output will have to move to -10 volts to
supply the same current through R
f
and keep the voltage at the inverting input
at zero.
The voltage gain in this case would be Rf/ R
1
or 10K/1K = 10. For higher input
impedances, both resistor values can be increased.

CIRCUIT DIAGRAM:



TABULAR COLUMN:
DC INPUT:
V
in
(VOLTS)
THEORETICAL
OUTPUT
(VOLTS)
PRACTICAL
OUTPUT
(VOLTS)










AC INPUT:











V
in
(VOLTS)
T
in

(ms)
V
0
(VOLTS)
T
0

(ms)






Signal
Generator
R
COMP=
1k
CRO
+15V
-15V
R
f
=10k
R
in
=1k
V
0
= [-R
f
/R
in
] V
i

-
+
V

MODEL GRAPH:
































V
in

(Volts)
V
o

(Volts)
t (ms)
t (ms)

NON INVERTING AMPLIFIER:
The non-inverting amplifier is connected so that the input signal goes
directly to the non-inverting input (+) and the input resistor R
1 which is
connected to inverting input (-)
is grounded. In this configuration, the input
impedance as seen by the signal is much greater since the input will be
following the applied signal and not held constant by the feedback current. As
the signal moves in either direction, the output will follow in phase to maintain
the inverting input at the same voltage as the input (+). The voltage gain is
always more than 1 and can be worked out from
A = 1 +
R
]
R
1


CIRCUIT DIAGRAM:





















TABULAR COLUMN:
DC INPUT:








V
in
(VOLTS)
THEORETICAL
OUTPUT
(VOLTS)
PRACTICAL
OUTPUT
(VOLTS)





CRO
~
+15V
-15V
R
f
=5.6k
R
in
=1k
Signal
Generator
V
0
= [1+R
f
/R
in
]
+
-


AC INPUT:









MODEL GRAPH:





V
in
(VOLTS)
T
in

(mS)
V
0
(VOLTS)
T
0

(mS)




V
in

(Volts)
V
o

(Volts)
t (ms)
t (ms)

SUMMI
Op
input sig
output vo
propor

DESIGN

If
Th
Rc

If R
1
=


CIRCUI
TABUL
Wave fo
Sine I/




O

ING AMP
p-amp may
gnals. Such
oltage V
ou
rtional to th
N:
R
1
=

R
2
=

hen Vo= -
comp =R
1
R
2
=

R
3
=R
IT DIAGR
LAR COLU
orm A
/P
O/P

PLIFIER:
y be used t
h a circuit
ut
becomes
he sum of

R
3
=R
f
[V
1
+V
2
+
|| R
2
|| R
3
|
R
f
= 10 K
RAM:
UMN:
mplitude (
to design a
t is called
s
I
out
=
I
R
the input v
V
3
] and
|| R
f
,then

R c
(v)


a circuit wh
a summin
I
1
R
1
+
I
2
R
2
+
I
R
voltages, V
comp =2.5
Time (mS
hose outpu
ng amplifi
I
3
R
3

V
1
, V
2
, V
3
K
S)
ut is the sum
ier or a su
.

m of severa
ummer. Th
al
he

MODEL GRAPH:











































V
2

V
m
t
V
m
t
V
m
V
3

3V
m
t
V
0

t
V
1


INTEGR
mathem
input v
which
words
voltage
or disc
is the
integra
time in
feedba


DESIGN
In
signal an
10Khz, R
From wh

F
a
=1/ (2
F
b
= 1(2

CIRCUI




RATOR:
The Integ
matical op
voltage ov
is proport
the magni
e is presen
charges th
time integ
ating ampl
nterval and
ack model.
N:
n an integra
nd F
b
is th
R
1
= 1 K
hich
R
f
C
f
) =
R
1
C
f
)=
IT DIAGR
grator is an
eration of
er time an
tional to th
itude of th
nt at its inp
he capacito
gral of th
lifier. Integ
d the circu
ator circui
he break fre
= C
f
= 1/(2
= R
1
= 1(2
RAM:
n operatio
f Integratio
nd the integ
hat of its i
e output si
put as the
or. A circu
he input vo
grator prod
uit is based
I
0
=
it, F
a
= F
b
/
equency, a
R
1
F
a
) =
F
b
C
f
) =
onal ampli
n, the outp
grator amp
input volta
ignal is de
current thr
uit in whic
oltage wa
duces the
d on the g
= -
1
RC
I
n
J
/10 where
assuming t
=> C
f
= 0.0
=> R
1
= 1.0
ifier circu
put to resp
plifier prod
age with re
termined b
rough the f
ch the out
aveform is
summing
general par
Jt
Fa is the
the values
015f
06K
uit that p
pond to ch
duces a vo
spect to tim
by the leng
feedback l
put voltag
called in
action ove
rallel inver
frequency
F
a
= 1khz,
performs th
anges in th
oltage outp
me. In oth
gth of time
loop charg
e wavefor
ntegrator
er a require
rting voltag
of the per
R
f
=10K

he
he
put
her
e a
es
rm
or
ed
ge
riodic
, F
b
=

TABULAR COLUMN:


Wave form Amplitude (v) Time (mS)
Sine I/P

O/P

Square I/P

O/P


MODEL GRAPH:



















DIFFERENTIATOR:
The differentiator can perform the mathematical operation of
differentiation that is the output voltage is the differentiation of the input
voltage. This operation is very useful to find the rate at which a signal varies
with time. The Differentiator circuit is the exact opposite to that of the
Integrator, the position of the capacitor and resistor have been reversed and
now the Capacitor, C is connected to the input terminal of the inverting
amplifier while the Resistor, R
f
forms the negative feedback element across
the operational amplifier. This circuit performs the mathematical operation of
differentiation that is it produces a voltage output which is proportional to the
input voltage's rate-of-change and the current flowing through the capacitor.
In other words the faster or larger the change to the input voltage signal, the
V
i
V
0
t(ms)
t(ms)
Vi(volts)
Vo(volts)
t(ms)
t(ms)

greater the input current, the greater will be the output voltage change in
response becoming more of a "spike" in shape.

DESIGN:

F
b
=20 F
a
, selecting C
1
=0.1 F (C<1F) and F
a
= 1KHZ then F
b
= 20KHZ
From which

F
a
= 1/(2 R
f
C
1
) = R
f
= 1/(2 F
a
C
1
) = R
f
= 1.5 K

F
b
= 1(2 R
f
C
f
) = C
f
= 1/(2 F
b
R
f
) = C
f
= 0.005F


CIRCUIT DIAGRAM:














TABULAR COLUMN:


Wave form


Amplitude(v)

Time (mS)
Sine I/P

O/P

Square I/P

O/P




C
f
=0.01f Vo
6
4
R
1
=1K
7
2
V
V+
3
R
f
=1.5K
C
f
=0.005f

+
Signal
Generator
V
i
(volt
V
0
(volt


MODEL



















COMPA

CIRCUI




ts)
ts)
L GRAPH
ARATOR
IT DIAGR
H:
:
RAM:
t(m
t(ms
ms)
)
V
V
Vi(volts)
Vo(volts)

t(mms)
t(ms)

TABULAR COLUMN:

Input Output Gain
Vamp t(ms) Vamp t(ms)
Vi =
Vref =

Vi =
Vref =


Op-amp may be used to design a circuit whose output is the difference of
twoinput signals. Such a circuit is called a comparator. The output voltage V
out
becomes
I
out
= I

-I
c]


MODEL GRAPH:



























V
m

V
ref

0V
0V
t
t


Pin Dia


Procedu
1. Co
2. Co
3. Fo
tab
4. In
co

Viva-Vo
1. W
2. W
3. W
4. W
5. W
6. Gi
7. W
8. Gi


Result:



Pe

agram:
ure:
onnections
onnect a D
or various
bulated.
n case of
orrespondin
oce Questi
What is oper
What is the o
What is the d
What is inpu
What is inpu
ive any ana
Why the out
ive any tw

erformance
s are made
DC voltage
values of
f compara
ng change
ons:
rational Am
operating v
difference
ut offset vo
ut offset cu
alogy to ex
tput gets ph
o practical
e(25)

as per the
source at t
f input vo
ator, the r
in the wav
mplifier?
voltage ran
between g
oltage?
urrent?
xplain the o
hase differ
l applicatio
Viva Vo
circuit dia
the input.
oltages, th
reference
veforms are
nge of oper
gain and ef
operation o
rence when
ons of instr
oce(10)
agram.
he correspo
voltage V
e observed
rational Am
fficiency?
of IC 741.
n the input
rumentatio
Record


onding ou
Vref is v
d.
mplifier?
given at P
n amplifie
d(15)


utput value
varied and
in.No.2
er.
Total(50)
es are
d the

Expt. No: Instrumentation Amplifier

Aim:

To design an instrumentation amplifier circuit and to obtain the CMRR
Value.

Apparatus Required:

Sl.No. Components Range Quantity
1 OpAmp LM741 3
2 Resistors 1K,10K 2
3 Power Supply -12 to +12 V 1
4 IC Trainer kit --------------- 1
5 Bread board --------------- 1
6 Multimeter --------------- 1
7 Connecting wires --------------- As required

Theory:

An amplifier that accepts a voltage signal as an input and produces a
linearly scaled version of this signal at the output, it is a closed-loop
fixed-gain amplifier, usually differential, and has high input impedance, low
drift, and high common-mode rejection over a wide range of frequencies.

Basic instrumentation amplifier:

Instrumentation Amplifiers are high gain differential amplifiers with
high input impedance and a single ended output. They are mainly used to
amplify very small differential signals from strain gauges, thermocouples or
current sensing resistors in motor control systems. They also have very good
common mode rejection (zero output when V1 = V2) in excess of 100dB at
DC. The amplifiers A
1
and A
2
are non inverting amplifiers. The
preamplifier amplifies the differential input (V
in1
~ V
in2
) which is
given as V
o1
. The differential amplifier in turn amplifies this V
o1
to
produce a final output of V
o
. Thus the differential input is amplified and
converted to a single ended output.

Features of instrumentation amplifier are:

1. High gain accuracy
2. High CMRR
3. High gain stability with low temperature coefficient
4. Low DC offset
5. Low output impedance

Circuit



Tabula

Sl.

No.
V

(
1
2
3

Pin Dia

Diagram
tion:
V1
(V)
V2

(V)



agram:
:
Vd

(V)
V

(V



Vc
V)
Vo

(V)



Ad=

Vo/Vd



Ac=

Vo/Vc



CMRR=
Ad/Ac

CMRR

(dB)




R

Procedure:
1. Connections are made as per the circuit diagram.

2. Connect a DC voltage source at the input.

3. For various values of input voltages, the corresponding output values are
tabulated.

4. Common mode gain and differential mode gain are calculated using

Common mode gain = Ac=Vo/Vc

Common mode input = Vc = (V1+V2)/2

Differential mode gain, Ad=Vo/Vd

CMRR = 20 log Ad/Ac

Vo = (R2/R1)(V1-V2) Volt

















Result:








Expt. N
Date:

Aim:
To
IC

Appara

Sl.No
1
2 T

3
R
4
5 C
6 F
7 B
8

Astable
741: Th
T
to opera
fed bac
and ma
invertin
Whenev
place re
states ar

Circuit

No: Ast
design and
555 Time
atus Requi
Com
Op Amp
Timer
Resistors
Capacitors
CRO
Function G
Breadboar
Connectin
e Multivib
heory:
The princip
ate in the
k to the o
ay take va
ng termina
ver input a
esulting in
re quasi st
Diagram
table Mult
d test the A
r.
ired:
mponents
s
Generators
rd
g wires
brator usin
ple of gene
saturation
on-invertin
alues as +
al after int
at the inv
n a square
table.
:
tivibrator
Astable mu
50K,

ng LM
eration of s
region. Th
ng input ter
V
sat
or
tegrating b
erting term
wave ou
ultivibrator
Rang
LM74
IC 55
, 11.6K,
3 3
0.01F, 0
0-25M
0-1MH
----
----
square wav
he fraction
rminal. Th
V
sat
. T
by means o
minal just
utput. In a
r using ope
ge
41
55
10K, 6.8

0.1F
MHz
Hz
ve output
n =R
2
/R
1
hus the ref
The output
of a low p
t exceeds
astable m
erational am
Q
8,
As
is to force
1
+R
2
of t
ference vol
t is also
pass RC c
V
ref
, swit
multivibrato

mplifier 74
Quantity
1
1
1
1
1
1
1
s required
e an OpAm
the output
ltage is V
feedback
combinatio
tching tak
or, both th
41 and
mp
is
V
o
to
on.
kes
he

Tab



Sl.No.



Mod


Asta

state
t o g
train
circu
build
outp
pin 7
anot
once
all o

C1's
T1 =
is gi
bulation:

Ton (sec

del Graph
able Multi
An asta
es are both
g l e s be
n of pulses
uit. In this
ding up en
put flip-flo
7, which is
ther intern
e again all
ver again.
s charge-up
= 0.693(R1
ven by T2
)

Toff
(sec)

h:
ivibrator u
able multiv
h unstable.
etween 'l
s. This cir
s circuit, c
nough volt
p. Once to
s the disch
al compar
ows C1 to
p time t1 is
1+R2) C1.
= 0.693(R
Amplitu
(V)

using IC55
vibrator is
The
low' and 'h
rcuit is the
capacitor C
tage to trig
oggled, the
harge pin. W
rator is trig
o charge up
s given by
C1's disch
R2) C1.
Output
ude Tim
(Se

55:
a timing
output o
high' conti
erefore als
C1 charges
gger an in
e flip-flop
When C1'
ggered to
p through
harge time

Freq
me
ec)

circuit w
o f a n a s
inuously, i
so known
through R
nternal com
discharge
s voltage b
toggle the
R1 and R
t2
quency
Vol
(V)

whose 'low
s t a b l e m
in effect g
as a 'pulse
R1 and R2
mparator to
s C1 throu
becomes l
output flip
R2 and the
Capacito
ltage Ti
(S

w' and 'hig
multivibrato
generating
e generato
, eventuall
o toggle th
ugh R2 int
ow enough
p-flop. Th
cycle star
or
ime
Sec)

h'
or
a
or'
ly
he
to
h,
his
rts

Thus

The
there

Circui


Tabul


Sl.No.




Model

s, the total
frequency
efore given
it Diagram
lation:
.

Ton
(Sec)


l Graph:
period of
y f of the ou
n by f = 1.4
m:
Toff
(Sec)
Am
(V


one cycle
utput wave
44/(C1(R1
Out
mplitude
V)
is T1+T2 =
e is the reci
+2R2))
tput
Time
(Sec)


= 0.693 C1
iprocal of t
Frequency
1 (R1+2R2
this period

y
C
Voltage
(V)


2).
d, and is
apacitor
Time
(Sec)





Proced

1.

2.

3.

Pin Dia




Result:









Pe


dure:
Connectio
Switch on
See the ou
the CRO a
agram:

erformance
ons are mad
n the power
utput wave
and measur
e(25)

de as per th
r supply.
form and t
re the amp
Viva Vo
he circuit d
the capacit
litude and
oce(10)
diagram
tor voltage
frequency
Record

waveform
y.
d(15)

m on
Total(50)


Expt. N
Date:

Aim:
To
and

Appara
Sl.No.
1 O

2

R
3 C
4 D
5 C
6 F
7 B
C

Monost
Theory
A
state. Th
duration
depends
clamps
going p
and dio
the (+)
output V
capacito
Circuit D
No.: M
design and
d IC 555 T
atus Requ
Comp
Op Amp
Resistors
Capacitor
Diode
CRO
Function G
Bread Boar
Connecting
table mult
y:
A Monosta
he circuit i
n in respo
s only on
the capac
pulse signa
ode D2 pro
terminal. T
V0is at +V
or c gets cl
Diagram:
Monostable
d test the M
imer.
ired:
ponents
Generator
rd
g Wires
tivibrator
able multiv
is useful f
onse to a t
n external
citor voltag
al of magn
oduces a n
To analyze
Vsat. The
lamped to 0
e Multivib
Monostable
using LM
vibrator ha
for generati
triggering s
l compone
ge +0.7V
nitude V1
negative g
e the circu
diode D1
0.7v.
rator
e multivibr
Range
LM741
10K
1K,100 K
0.1F, 4n
IN4002
0-25MH
0-1MHz
-----
-----
M741:
as one sta
ing single
signal. Th
ents conne
when the
passing t
going trigg
it let us as
Conducts
rator using
1
K
nF
2
Hz
z
able and t
output pu
he width
ected to th
output is
through th
gering impu
ssume that
s and Vc t
g operation
Qua
As R
the other
ulse of adju
of the o
he op amp.
at +Vsat.
he differen
ulse and i
in the stab
the voltage
al amplifie
antity
1
4
1
1
2
1
1
1
equired
quasi stab
ustable tim
output pul
. A diode
A negativ
ntiator R4C
s applied
ble state, th
e across th
er 741
ble
me
lse
D
ve
C4
to
he
he

Vamp (V



Tabula










Model


Monost

A
triggere
its outp
circuit,
off pin
same tim
C1 as c
time ma
which d
whose w
which m
should b
Input
V) T
(



tion:
Graph:
table mult
A monosta
ed, but retu
ut states is
a negative
7's discha
me, the flip
charged up
aking the p
discharges
width t is j
may be us
be tied to t
Time
Sec)



tivibrator
able multiv
urns to its
s stable. It
e pulse app
arge transi
p-flop brin
p to about
pin 3 outp
C1 to grou
just the pr
sed to res
the V
cc
if
Out
Vamp (V)
using IC5
vibrator is
original sta
t is also kn
plied at pi
istor, allow
ngs the out
2/3 V
cc
,
put 'low' an
und. This
roduct of R
set the tim
it will not
tput
Time
(Sec)



555:
a timing
ate after a
nown as a
n 2 trigger
wing C1 to
tput (pin 3)
the flip-fl
nd turning
circuit, in
R1 and C1
ming cycle
be used.
Vam



circuit tha
certain tim
'one-shot'
rs an intern
o charge u
) level to 'h
lop is trigg
g on pin 7'
effect, pro
1, i.e., T=
by pullin
Capacit
mp (V)



at changes
me delay.
' Multivibr
nal flip-flo
up through
high'. Wh
gered once
's discharg
oduces a pu
=R1C1. Th
ng it mome
tor
Time
(ms)

s state on
Only one
rator. In th
op that turn
h R1. At th
hen capacit
e again, th
ge transisto
ulse at pin
he reset pi
entarily low
ce
of
his
ns
he
or
his
or,
n 3
in,
w,

Circuit


Tabula


Sl.No.





Model

diagram:
tion:
Ton
(sec)

T
(


Graph:
:
Toff
(sec)
Amp
(V)


Output
plitude
t
F
Time
(Sec)


Frequency

Cap
Voltage
(V)


pacitor
Time
(Sec)




Pin Diag


Procedu
1. Co
2. Ap
3. Ad
wi
4. Dr

Viva-Voc
1. W
2. G
3. W
4. W
tr
5. W
6. W
re
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Exp.No.10 PLL and VCO
Date:

AIM:
(a) To study about voltage controlled oscillator
(b) To study about Phase locked loop.

(a) VOLTAGE CONTROLLED OSCILLATOR
THEORY:
A common type of VCO available in IC form is sign tics NE/SE 566. It
consists of a timing capacitor C
T
linearly charged or discharged by a constant current
source/sink. The amount of current can be controlled by changing the voltage V
c

applied at the modulating input (Pin 5) or by changing the timing resistor R
r
external
to the IC chip. The voltage at Pin 6 is held at the same voltage as Pin 5. Thus, if the
modulating voltage at Pin5 is measured, the voltage at Pin6 also increases, resulting in
less voltage across R and thereby decreasing the changing current.

The voltage across the capacitor C
T
is applied at the inverting input terminal of
Schmitt trigger A
2
via buffer amplifier. The output voltage swing of the Schmitt
trigger is designed to V
cc
and 0.5V
cc
. If R
a
= R
b
in the positive feedback loop, the
voltage at the non-inverting terminal of A2 swings from 0.5V
cc
to 0.25 V
cc
.

When the voltage on the capacitor C
T
exceeds 0.5V
cc
during charging the output
of the Schmitt trigger goes low (0-5) V
cc.
The capacitor now discharges and when it is
at 0.25V
cc
the output of Schmitt trigger goes high (V
cc).
Since the source and sink
currents are equal, capacitor charges and discharges for, the same amount of the time.
Thus v = 0.25V
cc

V = i
t C
T

0.25Vcc = i
t C
T

t = 0.25VccC
T

i
The frequency of oscillator f
0
is
f
0
= 1/t
= 1/2t
= i
0.5Vcc C
T

i = Vcc - Vc
R
t

PIN DIAGRAM:















CIRCUIT DIAGRAM:


























Ground
Square wave
output
Triangular
wave output
NC
+Vc
C
T
R
T
Modulated
input
8
7
6
5
1
4
3
2

NE/SE566
VCO
Modulating input

1 7
5
6 8
4
3
C
T

R
2
R
f
+Vcc

Vc
566

R
1

OUTPUT WAVEFORMS:























b) PHASE LOCKED LOOP

THEORY:
MONOLITHIC PHASE LOCKED LOOP:
All the different building blocks of the PLL are available as independent IC
packages and can be externally interconnected to make a PLL. Moreover a number of
manufacturers have introduced monolithic PLLs too.

Some of the important monolithic PLLs are SE/NE 560 series introduced by
signetics and LM560 series by rational semiconductor. The SE/NE 560,561,
562,564,565 and 567 mainly differ in operating frequency range, power supply
requirement, frequency and bandwidth adjustment ranges. Since 565 is the most
commonly used PLL.

565 iss available as 14-Pin DIP Packages and as 10 Pin Metal can package.
The output frequency of the VCO (both inputs 2,3 grounded)

f
0
= 0.25/R
t
C
t
Hz
Vcc
0.5Vcc
O/P at Pin4
0.5 Vcc
0.25 Vcc
Schmitt trigger
O/P
O/P at Pin3
Vcc
0.5Vcc

where R
t
and C
t
are the external resistor and capacitor connected to Pin8 and
Pin 9. A value between 2K and 20K is recommended for R
t
.
The VCO free running frequency is adjusted with R
t
and C
t
to be at the
centre of the input frequency range.
It may be seen that phase locked loop is internally broken between the VCO
output and the phase comparator input. A short circuit between pins 4 and 5 connects
the VCO output to the phase comparator, so as to compare f
0
with input signal f
s
. A
capacitor C is connected between Pin 7 and Pin 10 to make a low pass filter with
internal resistance of 3.6K.

PIN DIAGRAM:
































Reference
VCO
NC
+Vcc
External capacitor for VCO
NC
NC
-Vcc
External resistor for VCO
input
VCO
Demodulated
input
12
11
10
9
1
4
3
2
NE/SE565
5
8 7
6
13
14
NC

CIRCUIT DIAGRAM:


















Viva-Voce Questions:
1. Why do we need a divider in a PLL feedback loop?
2. What was the frequency of the divider you worked on?
3. What is a VCO? What kind of VCO was used in the PLL and do you know the
reason why?
4. Give any two practical applications of PLL and VCO.
5. What is lock-in range?
6. What is capture range?
7. Draw the block diagram of PLL.

Result:





Performance(25) Viva Voce(10) Record(15) Total(50)





+Vcc
Vco o/p 4
R
T

9
3.6k
C
Phase
detector
Amplifier
VCO
i/p 2
i/p 3
i/p 5
-Vcc Vcc
C
T
Demodulated
o/p
Ref o/p
8
10