The BF533 DSP video talkthrough project

Dani Cherkassky, Ronen Globinski, Department of electrical engineering,

AFEKA - Tel-Aviv academic college of engineering.



















TABLE OF CONTENTS
Overview....................................................................................................................... 3
Hardware...................................................................................................................... 4
EZ-Kit Lite hardware setup ....................................................................................... 4
SPORT cable.............................................................................................................. 5
Data flow diagram...................................................................................................... 6
Memory management ................................................................................................ 7



























Overview
The objective of this project is to perform real-time video input and output using the
ADSP-BF533 EZ-KIT Lite. The BF533 has only one PPI peripheral, this means that
simultaneous acquisition and generation of video stream is not possible. The first and
simplest solution is to configure the PPI as input, store one video frame in the
memory and then configure the PPI as output to display it. The big limitation of that
solution is that at least every second frame is lost and the configuration of the PPI
requires resetting the DMA and the video codec which results in image flicker. To
avoid this hardware limitation, 2 ADSP-BF533 EZ-KIT Lite boards with a serial
communication can be used. A master program that store a frame from a camera, send
it on the SPORT and a slave program that reads a frame via the SPORT and builds the
NTSC display signal are presented here.

The master program sends the video stream to the Slave, so the video source (a
camera in our case) needs to be connected to the master and the TV screen to the slave
as presented in fig. 1:

Fig. 1: System diagram








Hardware
EZ-Kit Lite hardware setup
To ensure correct operation, you must set the proper DIP switches on the SW9. Make
sure that the switch positions 5-6 on SW9 are in the OFF setting, as shown in fig. 2.

Fig. 2: EZ-KIT Lite hardware setup
(Analog Devices BF533_EZ_KIT evaluation system manual)

After the configuration of the SW9, the SPORT cable and the video IO cables must be
connected as shown in fig. 3.


Fig. 3: cable connections








Slave
Master
J8 (OUT)
To TV
J8 (IN)
From camera
SPORT cable
connected to
the SPORT0
(P3) connector
SPORT cable
The SPORT cable enables the full-duplex serial communication between the two
DSP's. We used the following hardware to build the cable:

Part Description: 20 position ribbon cable connector (AMP-LATCH)
Manufacturer: AMP
Part Number: 111196-4
Connector Image:


The cable's connections should be made exactly as shown in fig. 4.


Fig. 4: SPORT cable wiring diagram.























Data flow diagram

ADSP BF 533 EZ-KIT MASTER
ADSP BF 533 EZ-KIT SLAVE
Video
camera
Monitor
ADV7183 PPI DMA
SDRAM CORE
DMA SPORT
SPORT DMA
SDRAM
DMA
CORE
PPI ADV 7171

















Memory management

The slave program (video output) requires multiple simultaneous access to the
external on-board SRAM memory: 1) hardware access - storing of the input image in
the memory and reading the output NTSC frames 2) processor core access - building
the NTSC output frames from the stored input image.
Suppose an NTSC frame stored in a memory bank is accessed for display. When the
processor core is simultaneously trying to access the same bank using the same
address lines, it will cause some unwanted visual interferences. The solution to this
multiple access problem is to partition the SRAM with several different banks.
The SRAM is accessed through the EBIU (External Bus Interface Unit). The EBIU
hardware architecture enables access to each separate memory bank via different
address lines and thus providing us with the ability to access the external SRAM
memory simultaneously. We used 3 different image buffers and 3 memory banks, one
for the input image and two for NTSC output frames as illustrated in fig. 4.



Fig. 4: memory partitions and access diagram