Lecture 1 ECE 425

Lecture 2 -- The Inverter

Lecture 1 ECE 425
Outline
Signalling in Digital Systems
Inverters -- CMOS and Otherwise
Circuit Analysis of CMOS Inverters
Lecture 1 ECE 425
Signaling Conventions
Choose ranges of voltages to represent logic 0 and 1
Decide that logic 0 goes with low voltage, logic 1 with
high voltage
Need to guarantee that an input in the legal range
produces an output in the legal range
Better if the output for any legal input is closer to the
supply rails than the input (restoring logic)
Requires gain in the circuit
Need to tolerate some amount of electrical noise to be
practical
Lecture 1 ECE 425
CMOS Signaling Conventions
Voltage
Input Output
Logic
1
Logic
0
V
ih
V
il
forbidden
region
Logic
1
V
dd
0
V
oh
Logic
0
V
ol
Noise
Margin
Noise
Margin
forbidden
region
Lecture 1 ECE 425
CMOS Inverter
Vin
Vout
D
D
G
S
S
G
Vout
Vin
Vdd
Ground
Slope = 1
Lecture 1 ECE 425
CMOS
Complimentary Metal-Oxide Semiconductor
P-FETs connect output to V
dd
, N-FETs connect output
to ground
Good Points
Rail-to-rail outputs
Restoring logic
In principle, 0 current flows in steady state
In reality, leakage matters
Bad Points
Requires twice as many transistors as some other
logic styles
Lecture 1 ECE 425
Analyzing Inverter I-V Characteristics
KVL and KCL always apply
I
ds
(n) = -I
ds
(p)
V
ds
(n) + [-V
ds
(p)] = V
dd
Lecture 1 ECE 425
Inverter Transfer Characteristics
Lecture 1 ECE 425
Solving the System
Five regions of operation
A: N-FET off, P-FET in linear region
B: N-FET in saturation, P-FET in linear
C: Both devices in saturation
Want this region as small as possible
In this (ideal) case, its a single point at V
dd
/2
D: N-FET linear, P-FET saturated
E: N-FET linear, P-FET off
Lecture 1 ECE 425
Solving the System
Region A
V
in
< V
tn
, no current through N-FET, P-FET pulls V
out
to
V
dd
Region B
N-FET in saturation (current source)
P-FET in linear (resistor)
Lecture 1 ECE 425
Solving the System
Grinding the math, get
V
out
= (V
in
- V
tp
) + sqrt[(V
in
- V
tp
)
2
- 2V
dd
(V
in
- V
dd
/2 - V
tp
)
- (!
n
/!
p
)(V
in
- V
tn
)
2
]
(Remember that ! = * C
ox
* W/L)
Region C
Both FETs in saturation, in our ideal model happens at exactly
one point
If !
n
= !
p
and V
tn
= -V
tp
, this point is at V
in
= V
out
= V
dd
/2
Note that V
tp
is usually defined as a negative quantity to make
the equations symmetric
This input voltage is called the gate threshold
In reality, I
ds
increases slightly as V
ds
increases, even in
saturation, and region C is a small interval, not a point
Lecture 1 ECE 425
Solving the System
Region D:
N-FET in linear region, P-FET in saturation, dual of
region B
Model P-FET as current source, N-FET as resistor
V
out
= (V
in
- V
tn
) + sqrt[(V
in
- V
tn
)
2
- (!
p
/!
n
)(V
in
- V
dd
- V
tn
)
2
]
Region E:
N-FET is off, P-FET in linear region (V
in
> V
dd
- |V
tp
|)
No current through N-FET, P-FET pulls output voltage
to V
dd
Lecture 1 ECE 425
Changing Beta
Transfer curve
affected by ratio of
N, P device betas
Lecture 1 ECE 425
Pass-Gates -- A CMOS Switch
Lots of cases where wed like to be able to connect or
disconnect two wires at will
Multiplexors
Bi-Directional wires
Since one model of a MOS transistor is a switch, can we use
MOS transistors to build pass-gates?
Lecture 1 ECE 425
Idea #1 -- N-FET as Pass Gate
Passing a logic 0, V
gs
= V
dd
at all times
Lecture 1 ECE 425
Idea #1 -- N-FET as Pass Gate
Passing a logic 1 V
ds
= V
gs
, therefore capped at V
dd
- V
t
Lecture 1 ECE 425
Better Pass-Gate: N- and P-FET in Parallel
P-FET alone has opposite problem to N-FET -- passes 1s
well but 0s badly
Connect both types of device in parallel to pass both
signals well
Takes four transistors, though (counting the two to
invert the control signal)
!
!
!
!
Lecture 1 ECE 425
Trade-offs
Full pass-gate takes something like 4x the area of one pass-
transistor, but passes all signals well
However, V
t
and V
dd
- V
t
are typically well within the V
OL
and V
OH
regions
For safety, use full pass-gate anywhere youre not sure exactly what
the transistor will be driving
Single-transistor pass-gates can work in cases where the pass gate
drives a single CMOS gate
Never, ever connect multiple single-transistor pass-gates in series
Use of single-transistor pass-gates can make your design less
portable across fabrication processes -- correctness now depends
on electrical issues
Given the number of transistors/chip these days, the more important
trade-off is the amount of time youll have to spend verifying that a
single-transistor pass gate will work
Lecture 1 ECE 425
Next Time
Designing arbitrary CMOS gates
Lecture 1 ECE 425
Reading
Sections 2.5 - 2.7