Lecture 3 ECE 425 Outline Static CMOS Logic Gates Concepts Formalized design process Lecture 3 ECE 425 Static CMOS In steady state, a gate will have either a path from output- ground through N-FETs or a path from output-power through P-FETs Strong drive of gates that use the output Rail-to-rail signaling, with restoring logic Low static power consumption Inputs to logic gates connect to gate terminals of FETs High input resistance allows large fanout with correct behavior, although performance will suffer Lecture 3 ECE 425 Remember the Inverter Lecture 3 ECE 425 Generalizing to Other Gates Lecture 3 ECE 425 Computing AND Connect two transistors in series, and you get an AND Lecture 3 ECE 425 OR Functions Transistors in parallel give OR Lecture 3 ECE 425 CMOS NAND Gate P-FETs in parallel to V dd , N-FETs in series to ground Lecture 3 ECE 425 CMOS NOR Gate P-FETs in series to power, N-FETs in parallel to ground Lecture 3 ECE 425 Generalizing to More Complex Gates CMOS gate has a p-network that connects to power and an n-network that connects to ground Define: f p is a function that is true if and only if the p-network conducts f n is a function that is true if and only if the n-network conducts If the gate implements a function F, then f p = F = !f n Lecture 3 ECE 425 Other Logic Functions are Combination of AND, OR Take the function Find the n-network function !F Replace AND/OR subexpressions with series/parallel connections Lecture 3 ECE 425 p-network is Again, replace AND/OR subexpressions with series/parallel transistors Lecture 3 ECE 425 Combine the p- and n-networks to get the full gate Lecture 3 ECE 425 Your Turn Implement Lecture 3 ECE 425 Our Solution p-function n-function Circuit Lecture 3 ECE 425 Non Series-Parallel Designs This technique gives you a correct circuit, which may not be the best circuit Finding the best circuit may be non-trivial Lecture 3 ECE 425 Representing Circuits as Graphs Draw graph from circuit by Mapping nodes in the circuit to vertices in the graph Mapping transistors to edges labeled with the gate input of the transistor Lecture 3 ECE 425 Ok, Sure, but Why Would You Do That? Graph representation of circuit is easier for CAD programs to manipulate Generating the dual of a circuit from its graph may be easier than negating the Boolean expression Lecture 3 ECE 425 Planar Dual Graphs If the graph for a circuit is planar, theres a simple process to generate its dual (the graph of the negation of the circuits function) Lecture 3 ECE 425 Creating the Dual of a Planar Graph 1. Add vertical lines from the output and V dd /ground nodes of the original graph out to infinity 2. Create one node in each of the half-planes defined by the original graph. These will be the output and V dd /ground nodes of the new graph. 3. Place a vertex of the new graph (G) in every finite region of the plane defined by the original graph G 4. For each edge E in G 1. Find the vertices in G that lie on either side of E 2. Join those vertices with an edge E 3. Label that edge with the negation of the label on E Lecture 3 ECE 425 Huh? Time for an example! Lecture 3 ECE 425 Going the Other Way -- From Circuit to Function Lecture 3 ECE 425 Example Lecture 3 ECE 425 Next Time Overview of fabrication Reading: Section 1.5