Operational Amplifiers:

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to
which feedback is added to control its overall response characteristic i.e. gain and bandwidth.
The op-amp exhibits the gain down to zero frequency.
Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since
these would reduce the amplification to zero at zero frequency. Large by pass capacitors may be
used but it is not possible to fabricate large capacitors on a IC chip. The capacitors fabricated are
usually less than 20 pf. Transistor, diodes and resistors are also fabricated on the same chip.
Differential Amplifiers:
Differential amplifier is a basic building block of an op-amp. The function of a differential
amplifier is to amplify the difference between two input signals.
How the differential amplifier is developed? Let us consider two emitter-biased circuits as shown
in fig. 1.

Fig. 1
The two transistors Q
1
and Q
2
have identical characteristics. The resistances of the circuits are
equal, i.e. R
E1
=R
E2
, R
C1
=R
C2
and the magnitude of +V
CC
is equal to the magnitude of V
EE
.
These voltages are measured with respect to ground.
To make a differential amplifier, the two circuits are connected as shown in fig. 1. The two +V
CC

and V
EE
supply terminals are made common because they are same. The two emitters are also
connected and the parallel combination of R
E1
and R
E2
is replaced by a resistance R
E
. The two
input signals v
1
& v
2
are applied at the base of Q
1
and at the base of Q
2
. The output voltage is
taken between two collectors. The collector resistances are equal and therefore denoted by R
C
=
R
C1
=R
C2
.
Ideally, the output voltage is zero when the two inputs are equal. When v
1
is greater then v
2
the
output voltage with the polarity shown appears. When v
1
is less than v
2
, the output voltage has
the opposite polarity.
The differential amplifiers are of different configurations.
The four differential amplifier configurations are following:
1. Dual input, balanced output differential amplifier.
2. Dual input, unbalanced output differential amplifier.
3. Single input balanced output differential amplifier.
4. Single input unbalanced output differential amplifier.


Fig. 2
These configurations are shown in fig. 2, and are defined by number of input signals used and
the way an output voltage is measured. If use two input signals, the configuration is said to be
dual input, otherwise it is a single input configuration. On the other hand, if the output voltage is
measured between two collectors, it is referred to as a balanced output because both the
collectors are at the same dc potential w.r.t. ground. If the output is measured at one of the
collectors w.r.t. ground, the configuration is called an unbalanced output.
A multistage amplifier with a desired gain can be obtained using direct connection between
successive stages of differential amplifiers. The advantage of direct coupling is that it removes
the lower cut off frequency imposed by the coupling capacitors, and they are therefore, capable
of amplifying dc as well as ac input signals.
Dual Input, Balanced Output Differential Amplifier:
The circuit is shown in fig. 1, v
1
and v
2
are the two inputs, applied to the bases of Q
1
and Q
2

transistors. The output voltage is measured between the two collectors C
1
and C
2
, which are at
same dc potentials.
D.C. Analysis:
To obtain the operating point (I
CC
and V
CEQ
) for differential amplifier dc equivalent circuit is
drawn by reducing the input voltages v
1
and v
2
to zero as shown in fig. 3.

Fig. 3
The internal resistances of the input signals are denoted by R
S
because R
S1
=R
S2
. Since both
emitter biased sections of the different amplifier are symmetrical in all respects, therefore, the
operating point for only one section need to be determined. The same values of I
CQ
and V
CEQ
can
be used for second transistor Q
2
.
Applying KVL to the base emitter loop of the transistor Q
1
.

The value of R
E
sets up the emitter current in transistors Q
1
and Q
2
for a given value of V
EE
. The
emitter current in Q
1
and Q
2
are independent of collector resistance R
C
.
The voltage at the emitter of Q
1
is approximately equal to -V
BE
if the voltage drop across R is
negligible. Knowing the value of I
C
the voltage at the collector V
C
is given by
V
C
=V
CC
I
C
R
C

and V
CE
=V
C
V
E

=V
CC
I
C
R
C
+V
BE

V
CE
=V
CC
+V
BE
I
C
R
C
(E-2)
From the two equations V
CEQ
and I
CQ
can be determined. This dc analysis applicable for all types
of differential amplifier.
Example - 1
The following specifications are given for the dual input, balanced-output differential amplifier
of fig.1:
R
C
= 2.2 k, R
B
= 4.7 k, R
in 1
=R
in 2
= 50 , +V
CC
=10V, -V
EE
=-10 V,
dc
=100 and V
BE
=
0.715V.
Determine the operating points (I
CQ
and V
CEQ
) of the two transistors.
Solution:
The value of I
CQ
can be obtained from equation (E-1).


The voltage V
CEQ
can be obtained from equation (E-2).

The values of I
CQ
and V
CEQ
are same for both the transistors.
Dual Input, Balanced Output Difference Amplifier:
The circuit is shown in fig. 1 v
1
and v
2
are the two inputs, applied to the bases of Q
1
and Q
2

transistors. The output voltage is measured between the two collectors C
1
and C
2
, which are at
same dc potentials.

Fig. 1
A.C. Analysis :
In previous lecture dc analysis has been done to obtain the operatiing point of the two transistors.
To find the voltage gain A
d
and the input resistance R
i
of the differential amplifier, the ac
equivalent circuit is drawn using r-parameters as shown in fig. 2. The dc voltages are reduced to
zero and the ac equivalent of CE configuration is used.

Fig. 2
Since the two dc emitter currents are equal. Therefore, resistance r'
e1
and r'
e2
are also equal and
designated by r'
e
. This voltage across each collector resistance is shown 180 out of phase with
respect to the input voltages v
1
and v
2
. This is same as in CE configuration. The polarity of the
output voltage is shown in Figure. The collector C
2
is assumed to be more positive with respect
to collector C
1
even though both are negative with respect to to ground.
Applying KVL in two loops 1 & 2.

Substituting current relations,

Again, assuming R
S1
/ b and R
S2
/ b are very small in comparison with R
E
and r
e
' and therefore
neglecting these terms,

Solving these two equations, i
e1
and i
e2
can be calculated.

The output voltage V
O
is given by
V
O
=V
C2
- V
C1

=-R
C
i
C2
- (-R
C
i
C1
)
=R
C
(i
C1
- i
C2
)
=R
C
(i
e1
- i
e2
)
Substituting i
e1
, & i
e2
in the above expression

Thus a differential amplifier amplifies the difference between two input signals. Defining the
difference of input signals as v
d
=v
1
v
2
the voltage gain of the dual input balanced output
differential amplifier can be given by
(E-2)
Differential Input Resistance:
Differential input resistance is defined as the equivalent resistance that would be measured at
either input terminal with the other terminal grounded. This means that the input resistance R
i1

seen from the input signal source v
1
is determined with the signal source v
2
set at zero. Similarly,
the input signal v
1
is set at zero to determine the input resistance R
i2
seen from the input signal
source v
2
. Resistance R
S1
and R
S2
are ignored because they are very small.

Substituting i
e1
,

Similarly,

The factor of 2 arises because the r
e
' of each transistor is in series.
To get very high input impedance with differential amplifier is to use Darlington transistors.
Another ways is to use FET.
Output Resistance:
Output resistance is defined as the equivalent resistance that would be measured at output
terminal with respect to ground. Therefore, the output resistance R
O1
measured between collector
C
1
and ground is equal to that of the collector resistance R
C
. Similarly the output resistance R
O2

measured at C
2
with respect to ground is equal to that of the collector resistor R
C
.
R
O1
=R
O2
=R
C
(E-5)
The current gain of the differential amplifier is undefined. Like CE amplifier the differential
amplifier is a small signal amplifier. It is generally used as a voltage amplifier and not as current
or power amplifier.
Example - 1
The following specifications are given for the dual input, balanced-output differential amplifier:
R
C
= 2.2 k, R
B
= 4.7 k, R
in 1
=R
in 2
= 50, +V
CC
=10V, -V
EE
=-10 V,
dc
=100 and V
BE
=
0.715V.
a. Determine the voltage gain.
b. Determine the input resistance
c. Determine the output resistance.
Solution:
(a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The
operating point of the two transistors obtained in lecture-1 are given below
I
CQ
=0.988 mA
V
CEQ
=8.54V
The ac emitter resistance

Therefore, substituting the known values in voltage gain equation (E-2), we obtain

b). The input resistance seen from each input source is given by (E-3) and (E-4):

(c) The output resistance seen looking back into the circuit from each of the two output terminals
is given by (E-5)
R
o1
=R
o2
= 2.2 k
Example - 2
For the dual input, balanced output differential amplifier of Example-1:
a. Determine the output voltage (v
o
) if v
in 1
=50mV peak to peak (pp) at 1 kHz and
v
in 2
=20 mV pp at 1 kHz.
b. What is the maximum peal to peak output voltage without clipping?
Solution:
(a) In Example-1 we have determined the voltage gain of the dual input, balanced output
differential amplifier. Substituting this voltage gain (A
d
=86.96) and given values of input
voltages in (E-1), we get

(b) Note that in case of dual input, balanced output difference amplifier, the output voltage v
o
is
measured across the collector. Therefore, to calculate the maximum peak to peak output voltage,
we need to determine the voltage drop across each collector resistor:

Substituting I
C
=I
CQ
=0.988 mA, we get

This means that the maximum change in voltage across each collector resistor is 2.17 (ideally)
or 4.34 V
PP
. In other words, the maximum peak to peak output voltage with out clipping is (2)
(4.34) =8.68 V
PP
.
A dual input, balanced output difference amplifier circuit is shown in fig. 1.

Fig. 1
Inverting & Non inverting Inputs:
In differential amplifier the output voltage v
O
is given by
V
O
=A
d
(v
1
v
2
)
When v
2
=0, v
O
=A
d
v
1

& when v
1
=0, v
O
=- A
d
v
2

Therefore the input voltage v
1
is called the non inventing input because a positive voltage v
1

acting alone produces a positive output voltage v
O
. Similarly, the positive voltage v
2
acting alone
produces a negative output voltage hence v
2
is called inverting input. Consequently B
1
is called
noninverting input terminal and B
2
is called inverting input terminal.
Common mode Gain:
A common mode signal is one that drives both inputs of a differential amplifier equally. The
common mode signal is interference, static and other kinds of undesirable pickup etc.
The connecting wires on the input bases act like small antennas. If a differential amplifier is
operating in an environment with lot of electromagnetic interference, each base picks up an
unwanted interference voltage. If both the transistors were matched in all respects then the
balanced output would be theoretically zero. This is the important characteristic of a differential
amplifier. It discriminates against common mode input signals. In other words, it refuses to
amplify the common mode signals.
The practical effectiveness of rejecting the common signal depends on the degree of matching
between the two CE stages forming the differential amplifier. In other words, more closely are
the currents in the input transistors, the better is the common mode signal rejection e.g. If v
1
and
v
2
are the two input signals, then the output of a practical op-amp cannot be described by simply
v
0
=A
d
(v
1
v
2
)
In practical differential amplifier, the output depends not only on difference signal but also upon
the common mode signal (average).
v
d
=(v
1
v
d
)
and v
C
= (v
1
+v
2
)
The output voltage, therefore can be expressed as
v
O
=A
1
v
1
+A
2
v
2

Where A
1
& A
2
are the voltage amplification from input 1(2) to output under the condition that
input 2 (1) is grounded.

The voltage gain for the difference signal is A
d
and for the common mode signal is A
C
.
The ability of a differential amplifier to reject a common mode signal is expressed by its
common mode rejection ratio (CMRR). It is the ratio of differential gain A
d
to the common mode
gain A
C
.

Date sheet always specify CMRR in decibels CMRR =20 log CMRR.
Therefore, the differential amplifier should be designed so that r is large compared with the ratio
of the common mode signal to the difference signal. If r =1000, v
C
=1mV, v
d
=1 m V, then

It is equal to first term. Hence for an amplifier with r =1000, a 1m V difference of potential
between two inputs gives the same output as 1mV signal applied with the same polarity to both
inputs.
Dual Input, Unbalanced Output Differential Amplifier:
In this case, two input signals are given however the output is measured at only one of the two-
collector w.r.t. ground as shown in fig. 2. The output is referred to as an unbalanced output
because the collector at which the output voltage is measured is at some finite dc potential with
respect to ground..

Fig. 2
In other words, there is some dc voltage at the output terminal without any input signal applied.
DC analysis is exactly same as that of first case.

AC Analysis:
The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at
the output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is
normally followed by a level translator circuit.
Differential amplifier with swamping resistors:
By using external resistors R'
E
in series with each emitter, the dependence of voltage gain on
variations of r'
e
can be reduced. It also increases the linearity range of the differential amplifier.
Fig. 3, shows the differential amplifier with swamping resistor R'
E
. The value of R'
E
is usually
large enough to swamp the effect of r'
e
.

Fig. 3

Dual Input, Unbalanced Output Differential Amplifier:
In this case, two input signals are given however the output is measured at only one of the two-
collector w.r.t. ground as shown in fig. 2. The output is referred to as an unbalanced output
because the collector at which the output voltage is measured is at some finite dc potential with
respect to ground..

Fig. 2
In other words, there is some dc voltage at the output terminal without any input signal applied.
DC analysis is exactly same as that of first case.

AC Analysis:
The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at
the output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is
normally followed by a level translator circuit.
Differential amplifier with swamping resistors:
By using external resistors R'
E
in series with each emitter, the dependence of voltage gain on
variations of r'
e
can be reduced. It also increases the linearity range of the differential amplifier.
Fig. 3, shows the differential amplifier with swamping resistor R'
E
. The value of R'
E
is usually
large enough to swamp the effect of r'
e
.

Fig. 3


Example-1
Consider example-1 of lecture-2. The specifications are given again for the dual input,
unbalanced-output differential amplifier: R
C
= 2.2 k, R
B
= 4.7 k, R
in1
=R
in2
= 50, +V
CC
=
10V, -V
EE
=-10 V,
dc
=100 and V
BE
=0.715V.
Determine the voltage gain, input resistance and the output resistance.
Solution:
Since the component values remain unchanged and the biasing arrangement is same, the I
CQ
and
V
CEQ
values as well as input and output resistance values for the dual input, unbalanced output
configuration must be the same as those for the dual input, balanced output configuration.
Thus, I
CQ
=0.988 mA
V
CEQ
=8.54 V
R
i1
=R
i2
=5.06 k
R
o
= 2.2 k
The voltage gain of the dual input, unbalanced output differential amplifier is given by

Example-2
Repeat Example-1 for single input, balanced output differential amplifier.
Solution:
Because the same biasing arrangement and same component values are used in both
configurations, the results obtained in Example-1 for the dual input, balanced output
configuration are also valid for the single input, balanced output configuration.
That is,
I
CQ
=0.988 mA
V
CEQ
=8.54 V
V
d
=86.96
R
i
= 5.06 k
R
o1
=R
o2
= 2.2 k
Constant Current Bias:
In the dc analysis of differential amplifier, we have seen that the emitter current I
E
depends upon
the value of b
dc
. To make operating point stable I
E
current should be constant irrespective value
of b
dc
.
For constant I
E
, R
E
should be very large. This also increases the value of CMRR but if R
E
value
is increased to very large value, I
E
(quiescent operating current) decreases. To maintain same
value of I
E
, the emitter supply V
EE
must be increased. To get very high value of resistance R
E

and constant I
E
, current, current bias is used.

Figure 5.1
Fig. 1, shows the dual input balanced output differential amplifier using a constant current bias.
The resistance R
E
is replace by constant current transistor Q
3
. The dc collector current in Q
3
is
established by R
1
, R
2
, & R
E
.
Applying the voltage divider rule, the voltage at the base of Q
3
is

Because the two halves of the differential amplifiers are symmetrical, each has half of the current
I
C3
.

The collector current, I
C3
in transistor Q
3
is fixed because no signal is injected into either the
emitter or the base of Q
3
.
Besides supplying constant emitter current, the constant current bias also provides a very high
source resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all
the performance equations obtained for differential amplifier using emitter bias are also valid.
As seen in I
E
expressions, the current depends upon V
BE3
. If temperature changes, V
BE
changes
and current I
E
also changes. To improve thermal stability, a diode is placed in series with
resistance R
1
as shown in fig. 2.

Fig. 2
This helps to hold the current I
E3
constant even though the temperature changes. Applying KVL
to the base circuit of Q
3
.

Therefore, the current I
E3
is constant and independent of temperature because of the added diode
D. Without D the current would vary with temperature because V
BE3
decreases approximately by
2mV/ C. The diode has same temperature dependence and hence the two variations cancel each
other and I
E3
does not vary appreciably with temperature. Since the cut in voltage V
D
of diode
approximately the same value as the base to emitter voltage V
BE3
of a transistor the above
condition cannot be satisfied with one diode. Hence two diodes are used in series for V
D
. In this
case the common mode gain reduces to zero.
Some times zener diode may be used in place of diodes and
resistance as shown in fig. 3. Zeners are available over a wide
range of voltages and can have matching temperature
coefficient
The voltage at the base of transistor Q
B
is


Fig. 3
The value of R
2
is selected so that I
2
1.2 I
Z(min)
where I
Z
is the minimum current required to
cause the zener diode to conduct in the reverse region, that is to block the rated voltage V
Z
.

Current Mirror:
The circuit in which the output current is forced to equal the input current is said to be a current
mirror circuit. Thus in a current mirror circuit, the output current is a mirror image of the input
current. The current mirror circuit is shown in fig. 4.

Fig. 4
Once the current I
2
is set up, the current I
C3
is automatically established to be nearly equal to I
2
.
The current mirror is a special case of constant current bias and the current mirror bias requires
of constant current bias and therefore can be used to set up currents in differential amplifier
stages. The current mirror bias requires fewer components than constant current bias circuits.
Since Q3 and Q4 are identical transistors the current and voltage are approximately same

For satisfactory operation two identical transistors are necessary.
Example - 1
Design a zener constant current bias circuit as
shown in fig. 5 according to the following
specifications.
(a). Emitter current -I
E
=5 mA
(b). Zener diode with V
z
=4.7 V and I
z
=53
mA.
(c).
ac
=
dc
=100, V
BE
=0.715V
(d). Supply voltage - V
EE
=- 9 V.
Solution:
From fig. 6 using KVL we get


Fig. 5
Practically we use R
E
= 820 k

Practically we use R
2
= 68
The designed component values are:
R
E
= 860
R
2
= 68

Fig. 6
Example - 2
Design the dual-input balanced output differential amplifier using the diode constant current bias
to meet the following specifications.
1. supply voltage =12 V.
2. Emitter current I
E
in each differential amplifier transistor =1.5 mA.
3. Voltage gain 60.
Solution:
The voltage at the base of transistor Q
3
is

Assuming that the transistor Q
3
has the same
characteristics as diode D
1
and D
2
that is V
D

=V
BE3
, then

Practically we take R
E
= 240 .

Practically we take R
2
= 3.6 k.

To obtain the differential gain of 60, the
required value of the collector resistor is

The following fig. 7 shows the dual input,
balanced output differential amplifier with
the designed component values as R
C
=1K,
R
E
= 240 , and R
2
= 3.6K.

Fig. 7
The operation amplifier:
An operational amplifier is a direct coupled high gain amplifier consisting of one or more
differential (OPAMP) amplifiers and followed by a level translator and an output stage. An
operational amplifier is available as a single integrated circuit package.
The block diagram of OPAMP is shown in fig. 1.

Fig. 1
The input stage is a dual input balanced output differential amplifier. This stage provides most of
the voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The
intermediate stage of OPAMP is another differential amplifier which is driven by the output of
the first stage. This is usually dual input unbalanced output.
Because direct coupling is used, the dc voltage level at the output of intermediate stage is well
above ground potential. Therefore level shifting circuit is used to shift the dc level at the output
downward to zero with respect to ground. The output stage is generally a push pull
complementary amplifier. The output stage increases the output voltage swing and raises the
current supplying capability of the OPAMP. It also provides low output resistance.
Level Translator:
Because of the direct coupling the dc level at the emitter
rises from stages to stage. This increase in dc level tends
to shift the operating point of the succeeding stages and
therefore limits the output voltage swing and may even
distort the output signal.
To shift the output dc level to zero, level translator
circuits are used. An emitter follower with voltage
divider is the simplest form of level translator as shown
in fig. 2.
Thus a dc voltage at the base of Q produces 0V dc at the
output. It is decided by R
1
and R
2
. Instead of voltage
divider emitter follower either with diode current bias or
current mirror bias as shown in fig. 3 may be used to get

Fig. 2











Fig. 3
Fig. 4, shows a complete OPAMP circuit having input different amplifiers with balanced output,
intermediate stage with unbalanced output, level shifter and an output amplifier.
better results.
In this case, level shifter, which is common collector
amplifier, shifts the level by 0.7V. If this shift is not
sufficient, the output may be taken at the junction of two
resistors in the emitter leg.

Fig. 4
Example-1:
For the cascaded differential amplifier shown in fig. 5, determine:
The collector current and collector to emitter voltage for each transistor.
The overall voltage gain.
The input resistance.
The output resistance.
Assume that for the transistors used h
FE
=100 and V
BE
=0.715V

Fig. 5
Solution:
(a). To determine the collector current and collector to emitter voltage of transistors Q
1
and Q
2
,
we assume that the inverting and non-inverting inputs are grounded. The collector currents (I
C

I
E
) in Q
1
and Q
2
are obtained as below:

That is, I
C1
=I
C2
=0.988 mA.
Now, we can calculate the voltage between collector and emitter for Q
1
and Q
2
using the
collector current as follows:
V
C1
=V
CC
=-R
C1
I
C1
=10 (2.2k) (0.988 mA) = 7.83 V = V
C2

Since the voltage at the emitter of Q
1
and Q
2
is -0.715 V,
V
CE1
=V
CE2
=V
C1
-V
E1
=7.83 +0715 =8.545 V
Next, we will determine the collector current in Q
3
and Q
4
by writing the Kirchhoff's voltage
equation for the base emitter loop of the transistor Q
3
:
V
CC
R
C2
I
C2
=V
BE3
- R'
E
I
C3
- R
E2
(2 I
E3
) +V
BE
=0
10 (2.2k) (0.988mA) - 0.715 - (100) (I
E3
) (30k) I
E3
+10=0
10 - 2.17 - 0.715 +10 - (30.1k) I
E3
=0

Hence the voltage at the collector of Q
3
and Q
4
is
V
C3
=V
C4
=V
CC
R
C3
I
C3
=10 (1.2k) (0.569 mA)
=9.32 V
Therefore,
V
CE3
=V
VCE4
=V
C3
V
E3
=9.32 7.12 =2.2 V
Thus, for Q
1
and Q
2
:
I
CQ
=0.988 mA
V
CEQ
=8.545 V
and for Q
3
and Q
4
:
I
CQ
=0.569 mA
V
CEQ
=2.2 V
[Note that the output terminal (V
C4
) is at 9.32 V and not at zero volts.]
(b). First, we calculate the ac emitter resistance r'
e
of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

Where
R
i2
=input resistance of the second stage

The second stage is dual input, unbalanced output differential amplifier with swamping resistor
R'
E
, the voltage gain of which is

Hence the overall voltage gain is
A
d
=(A
d1
) (A
d2
) =(80.78) (4.17) =336.85
Thus we can obtain a higher voltage gain by cascading differential amplifier stages.
(c).The input resistance of the cascaded differential amplifier is the same as the input resistance
of the first stage, that is
R
i
= 2
ac
(r
e1
) = (200) (25.3) = 5.06 k
(d). The output resistance of the cascaded differential amplifier is the same as the output
resistance of the last stage. Hence,
R
O
=R
C
=1.2 k
Example-2:
For the circuit show in fig. 6, it is given that =100, V
BE
=0715V. Determine
The dc conditions for each state
The overall voltage gain
The maximum peak to peak output voltage swing.

Fig. 6
Solution:
(a). The base currents of transistors are neglected and V
BE
drops of all transistors are assumed
same.

From the dc equivalent circuit,

and

b) The overall voltage gain of the amplifier can be obtained as below:

Therefore, voltage gain of second stage

The input impedance of second stage is

The effective load resistance for first stage is

Therefore, the voltage gain of first stage is

The overall voltge gain is A
V
=A
V1
A
V2


(c). The maximum peak to peak output votage swing =Vopp =2 (V
C7
- V
E7
)
=2 x (5.52 - 3.325)
=4.39 V
The symbolic diagram of an OPAMP is shown in fig. 1.

741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.
Parameters of OPAMP:
The various important parameters of OPAMP are follows:
1.Input Offset Voltage:
Input offset voltage is defined as the
voltage that must be applied between
the two input terminals of an OPAMP
to null or zero the output fig. 2, shows
that two dc voltages are applied to
input terminals to make the output
zero.
V
io
=V
dc1
V
dc2

V
dc1
and V
dc2
are dc voltages and R
S

represents the source resistance. V
io
is
the difference of V
dc1
and V
dc2
. It may
be positive or negative. For a 741C
OPAMP the maximum value of V
io
is

Fig. 2
6mV. It means a voltage 6 mV is
required to one of the input to reduce
the output offset voltage to zero. The
smaller the input offset voltage the
better the differential amplifier,
because its transistors are more
closely matched.
2. Input offset Current:
The input offset current I
io
is the difference between the currents into inverting and non-inverting
terminals of a balanced amplifier.
I
io
=| I
B1
I
B2
|
The I
io
for the 741C is 200nA maximum. As the matching between two input terminals is
improved, the difference between I
B1
and I
B2
becomes smaller, i.e. the I
io
value decreases
further.For a precision OPAMP 741C, I
io
is 6 nA
3.Input Bias Current:
The input bias current I
B
is the average of the current entering the input terminals of a balanced
amplifier i.e.
I
B
=(I
B1
+I
B2
) / 2
For 741C I
B(max)
=700 nA and for precision 741C I
B
=7 nA
4. Differential Input Resistance: (R
i
)
R
i
is the equivalent resistance that can be measured at either the inverting or non-inverting input
terminal with the other terminal grounded. For the 741C the input resistance is relatively high 2
M. For some OPAMP it may be up to 1000 G ohm.
5. Input Capacitance: (C
i
)
C
i
is the equivalent capacitance that can be measured at either the inverting and noninverting
terminal with the other terminal connected to ground. A typical value of C
i
is 1.4 pf for the 741C.
6. Offset Voltage Adjustment Range:
741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this
purpose. It can be done by connecting 10 K ohm pot between 1 and 5 as shown in fig. 3.

Fig. 3
By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to
zero volts. Thus the offset voltage adjustment range is the range through which the input offset
voltage can be adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is
15 mV.
Parameters of OPAMP:
7. Input Voltage Range :
Input voltage range is the range of a common mode input signal for which a differential amplifier
remains linear. It is used to determine the degree of matching between the inverting and
noninverting input terminals. For the 741C, the range of the input common mode voltage is
13V maximum. This means that the common mode voltage applied at both input terminals can
be as high as +13V or as low as 13V.
8. Common Mode Rejection Ratio (CMRR).
CMRR is defined as the ratio of the differential voltage gain A
d
to the common mode voltage
gain A
CM

CMRR =A
d
/ A
CM
.
For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the
matching between two input terminals and the smaller is the output common mode voltage.
9. Supply voltage Rejection Ratio: (SVRR)
SVRR is the ratio of the change in the input offset voltage to the corresponding change in power
supply voltages. This is expressed in m V / V or in decibels, SVRR can be defined as
SVRR =D V
io
/ D V
Where D V is the change in the input supply voltage and D V
io
is the corresponding change in
the offset voltage.
For the 741C, SVRR =150 V / V.
For 741C, SVRR is measured for both supply magnitudes increasing or decreasing
simultaneously, with R
3
10K. For same OPAMPS, SVRR is separately specified as positive
SVRR and negative SVRR.
10. Large Signal Voltage Gain:
Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of
the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage gain is
commonly called large signal voltage gain. For 741C is voltage gain is 200,000 typically.
11. Output voltage Swing:
The ac output compliance PP is the maximum unclipped peak to peak output voltage that an
OPAMP can produce. Since the quiescent output is ideally zero, the ac output voltage can swing
positive or negative. This also indicates the values of positive and negative saturation voltages of
the OPAMP. The output voltage never exceeds these limits for a given supply voltages +V
CC
and
V
EE
. For a 741C it is 13 V.
12. Output Resistance: (R
O
)
R
O
is the equivalent resistance that can be measured between the output terminal of the OPAMP
and the ground. It is 75 ohm for the 741C OPAMP.
Example - 1
Determine the output voltage in each of the following cases for the open loop differential
amplifier of fig. 4:
a. v
in 1
=5 m V dc, v
in 2
=-7 V
dc

b. v
in 1
=10 mV rms, v
in 2
=20 mV rms

Fig. 4
Specifications of the OPAMP are given below:
A =200,000, R
i
= 2 M , R O = 75, + V
CC
=+15 V, - V
EE
=- 15 V, and output voltage swing
=14V.
Solution:
(a). The output voltage of an OPAMP is given by

Remember that v
o
=2.4 V dc with the assumption that the dc output voltage is zero when the
input signals are zero.
(b). The output voltage equation is valid for both ac and dc input signals. The output voltage is
given by

Thus the theoretical value of output voltage v
o
=-2000 V rms. However, the OPAMP saturates at
14 V. Therefore, the actual output waveform will be clipped as shown fig. 5. This non-
sinusoidal waveform is unacceptable in amplifier applications.

Fig. 5
13. Output Short circuit Current :
In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its
output impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power
device and so its output current is limited. The 741C can supply a maximum short circuit output
current of only 25mA.
14. Supply Current :
I
S
is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current
is 2.8 m A.
15. Power Consumption:
Power consumption (PC) is the amount of quiescent power (v
in
=0V) that must be consumed by
the OPAMP in order to operate properly. The amount of power consumed by the 741C is 85 m
W.
Parameters of OPAMP:
16. Gain Bandwidth Product:
The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is
reduced to 1. From open loop gain vs frequency graph At 1 MHz shown in. fig. 6, It can be
found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain
is 100, 000 and cut off frequency is 10Hz.

Fig. 6
17. Slew Rate:
Slew rate is defined as the maximum rate of change of output voltage per unit of time under large
signal conditions and is expressed in volts / m secs.

To understand this, consider a charging current of a capacitor shown in fig. 7.


Fig. 6
If 'i' is more, capacitor charges quickly. If 'i' is limited to I
max
, then rate of change is also limited.
Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in
the input frequency with input amplitude constant. The slew rate changes with change in voltage
gain and is normally specified at unity gain.
If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the
slew rate is low 0.5 V / m S. which limits its use in higher frequency applications.
18. Input Offset Voltage and Current Drift:
It is also called average temperature coefficient of input offset voltage or input offset current.
The input offset voltage drift is the ratio of the change in input offset voltage to change in
temperature and expressed in m V / C. Input offset voltage drift =( D V
io
/ D T).
Similarly, input offset current drift is the ratio of the change in input offset current to the change
in temperature. Input offset current drift =( D I
io
/ D T).
For 741C,
D V
io
/ D T =0.5 m V / C.
D I
io
/ D T =12 pA / C.
Example - 1
A 100 PF capacitor has a maximum charging current of 150 A. What is the slew rate?
Solution:
C =100 PF=100 x 10
-12
F
I =150 A =150 x 10
-6
A

Slew rate is 1.5 V / s.
Example - 2
An operational amplifier has a slew rate of 2 V / s. If the peak output is 12 V, what is the power
bandwidth?
Solution:
The slew rate of an operational amplifier is

As for output free of distribution, the slews determines the maximum frequency of operation
fmax for a desired output swing.
so
So bandwidth =26.5 kHz.
Example - 3
For the given circuit in fig. 1. I
in(off)
=20 nA. If V
in(off)
=0, what is the differential input voltage?.
If A =10
5
, what does the output offset voltage equal?

Fig. 1
Solutin:
I
in(off)
=20 nA
V
in(off)
=0
(i) The differential input voltage =I
in(off)
x 1k =20 nA x 1 k =20 V
(ii) If A =10
5
then the output offset voltage V
in(off)
=20 V x 10
5
=2 volt
Output offset voltage =2 volts.
Example - 4
R1 = 100, R
f
=8.2 k, R
C
=10 k. Assume that the amplifier is nulled at 25C. If V
in
is 20 mV
peak sine wave at 100 Hz. Calculate E
r
, and V
o
values at 45C for the circuit shown in fig. 2.

Fig. 2
Solution:

The change in temperature T = 45 - 25 =20C.

Error voltage =51.44 mV

Output voltage is 1640 mV peak ac signal which rides either on a +51.44 mV or -51.44 mV dc
level.
Example - 5
Design an input offset voltage compensating network for the operational amplifier A 715 for
the circuit shown in fig. 3. Draw the complete circuit diagram.

Fig. 3
Solution:
From data sheet we get v
in
=5 mV for the operational amplifier A 715.
V =| V
CC
| =| - V
EE
| =15 V
Now,

If we select R
C
= 10, the value of R
b
should be
R
b
=(3000) R
C
=30000 = 304
Since R >R
max
, let R
S
=10 R
max
where R
max
=R
a
/ 4. Therefore,

If a 124 potentiometer is not available, we may prefer to use to the next lower value avilable,
such as 104, so that the value of R
a
will be larger than R
b
by a factor of 10. If we select a 10 k
potentiometer a s the R
a
value, R
b
is 12 times larger than R
a
, Thus
R
a
= 10 k potentiometer
R
b
= 30 k
R
c
= 10.
The final circuit, which also includes the pin connections for the A 715, shown in fig. 4.

Fig. 4
The ideal OPAMP :
An ideal OPAMP would exhibit the following electrical characteristic.
1. Infinite voltage gain A
d

2. Infinite input resistance R
i
, so that almost any signal source can drive it and there
is no loading of the input source.
3. Zero output resistance R
O
, so that output can drive an infinite number of other
devices.
4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be
amplified without attenuation.
6. Infinite common mode rejection ratio so that the output common mode noise
voltage is zero.
7. Infinite slew rate, so that output voltage changes occur simultaneously with input
voltage changes.
There are practical OPAMPs that can be made to approximate some of these characters using a
negative feedback arrangement.
Equivalent Circuit of an OPAMP:
Fig. 5, shows an equivalent circuit of an OPAMP. v
1
and v
2
are the two input voltage voltages. R
i

is the input impedance of OPAMP. A
d
V
d
is an equivalent Thevenin voltage source and R
O
is the
Thevenin equivalent impedance looking back into the terminal of an OPAMP.

Fig. 5
This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in
observing the effects of standard feedback arrangements
v
O
=A
d
(v
1
v
2
) =A
d
v
d
.
This equation indicates that the output voltage v
O
is directly proportional to the algebraic
difference between the two input voltages. In other words the OPAMP amplifies the difference
between the two input voltages. It does not amplify the input voltages themselves. The polarity
of the output voltage depends on the polarity of the difference voltage v
d
.
Ideal Voltage Transfer Curve:
The graphic representation of the output equation is shown in fig. 6 in which the output voltage
v
O
is plotted against differential input voltage v
d
, keeping gain A
d
constant.

Fig. 6
The output voltage cannot exceed the positive and negative saturation voltages. These saturation
voltages are specified for given values of supply voltages. This means that the output voltage is
directly proportional to the input difference voltage only until it reaches the saturation voltages
and thereafter the output voltage remains constant.
Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is
assumed to be zero. If the curve is drawn to scale, the curve would be almost vertical because of
very large values of A
d
.
Open loop OPAMP Configuration:
In the case of amplifiers the term open loop indicates that no connection, exists between input
and output terminals of any type. That is, the output signal is not fedback in any form as part of
the input signal.
In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open
loop OPAMP configurations.
The Differential Amplifier:
Fig. 1, shows the open loop differential amplifier in which input signals v
in1
and v
in2
are applied
to the positive and negative input terminals.

Fig. 1
Since the OPAMP amplifies the difference the between the two input signals, this configuration
is called the differential amplifier. The OPAMP amplifies both ac and dc input signals. The
source resistance R
in1
and R
in2
are normally negligible compared to the input resistance R
i
.
Therefore voltage drop across these resistances can be assumed to be zero.
Therefore
v
1
=v
in1
and v
2
=v
in2
.
v
o
=A
d
(v
in1
v
in2
)
where, A
d
is the open loop gain.
The Inverting Amplifier:
If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is
called inverting amplifier.This configuration is shown in fig. 2.
v
1
=0, v
2
=v
in
.
v
o
=-A
d
v
in


Fig. 2
The negative sign indicates that the output voltage is out of phase with respect to input 180 or
is of opposite polarity. Thus the input signal is amplified and inverted also.
The non-inverting amplifier:
In this configuration, the input voltage is applied to non-inverting terminals and inverting
terminal is ground as shown in fig. 3.
v
1
=+v
in
v
2
=0
v
o
=+A
d
v
in

This means that the input voltage is amplified by A
d
and there is no phase reversal at the output.

Fig. 3
In all there configurations any input signal slightly greater than zero drive the output to
saturation level. This is because of very high gain. Thus when operated in open-loop, the output
of the OPAMP is either negative or positive saturation or switches between positive and negative
saturation levels. Therefore open loop op-amp is not used in linear applications.
Closed Loop Amplifier:
The gain of the OPAMP can be controlled if fedback is introduced in the circuit. That is, an
output signal is fedback to the input either directly or via another network. If the signal fedback
is of opposite or out phase by 180 with respect to the input signal, the feedback is called
negative fedback.
An amplifier with negative fedback has a self-correcting ability of change in output voltage
caused by changes in environmental conditions. It is also known as degenerative fedback
because it reduces the output voltage and,in tern,reduces the voltage gain.
If the signal is fedback in phase with the input signal, the feedback is called positive feedback. In
positive feedback the feedback signal aids the input signal. It is also known as regenerative
feedback. Positive feedback is necessary in oscillator circuits.
The negative fedback stabilizes the gain, increases the bandwidth and changes, the input and
output resistances. Other benefits are reduced distortion and reduced offset output voltage. It also
reduces the effect of temperature and supply voltage variation on the output of an op-amp.
A closed loop amplifier can be represented by two blocks one for an OPAMP and other for a
feedback circuits. There are four following ways to connect these blocks. These connections are
shown in fig. 4.
These connections are classified according to whether the voltage or current is feedback to the
input in series or in parallel:
Voltage series feedback
Voltage shunt feedback
Current series feedback
Current shunt feedback

Fig. 4
In all these circuits of fig. 4, the signal direction is from input to output for OPAMP and output
to input for feedback circuit. Only first two, feedback in circuits are important.
Voltage series feedback:
It is also called non-inverting voltage feedback circuit. With this type of feedback, the input
signal drives the non-inverting input of an amplifier; a fraction of the output voltage is then fed
back to the inverting input. The op-amp is represented by its symbol including its large signal
voltage gain A
d
or A, and the feedback circuit is composed of two resistors R
1
and R
f
. as shown
in fig. 5


Fig. 5

The feedback voltage always opposes the input voltage, (or is out of phase by 180 with respect
to input voltage), hence the feedback is said to be negative.
The closed loop voltage gain is given by

The product A and B is called loop gain. The gain loop gain is very large such that AB >>1

This shows that overall voltage gain of the circuit equals the reciprocal of B, the feedback gain.
It means that closed loop gain is no longer dependent on the gain of the op-amp, but depends on
the feedback of the voltage divider. The feedback gain B can be precisely controlled and it is
independent of the amplifier.
Physically, what is happening in the circuit? The gain is approximately constant, even though
differential voltage gain may change. Suppose A increases for some reasons (temperature
change). Then the output voltage will try to increase. This means that more voltage is fedback to
the inverting input, causing v
d
voltage to decrease. This almost completely offset the attempted
increases in output voltage.
Similarly, if A decreases, The output voltage decreases. It reduces the feedback voltage v
f
and
hence, v
d
voltage increases. Thus the output voltage increases almost to same level.
Different Input voltage is ideally zero.
Again considering the voltage equation,
v
O
=A
d
v
d

or v
d
=v
O
/ A
d

Since A
d
is very large (ideally infinite)
\ v
d
0.
and v
1
=v
2
(ideal).
This says, that the voltage at non-inverting input terminal of an op-amp is approximately equal to
that at the inverting input terminal provided that A
d
is very large. This concept is useful in the
analysis of closed loop OPAMP circuits. For example, ideal closed loop voltage again can be
obtained using the results

Input Resistance with Feedback:
fig. 1, shows a voltage series feedback with the OPAMP equivalent circuit.

Fig. 1
In this circuit R
i
is the input resistance (open loop) of the OPAMP and R
if
is the input resistance
of the feedback amplifier. The input resistance with feedback is defined as

Since AB is much larger than 1, which means that R
if
is much larger that R
i
. Thus R
if
approaches
infinity and therefore, this amplifier approximates an ideal voltage amplifier.
Output Resistance with Feedback:
Output resistance is the resistance determined looking back into the feedback amplifier from the
output terminal. To find output resistance with feedback R
f
, input v
in
is reduced to zero, an
external voltage V
o
is applied as shown in fig. 2.

Fig. 2
The output resistance (R
of
) is defined as

This shows that the output resistance of the voltage series feedback amplifier is ( 1 / 1+AB )
times the output resistance R
o
of the op-amp. It is very small because (1+AB) is very large. It
approaches to zero for an ideal voltage amplifier.
Reduced Non-linear Distortion:
The final stage of an OPAMP has non-linear distortion when the signal swings over most of the
ac load line. Large swings in current cause the r'
e
of a transistor to change during the cycle. In
other words, the open loop gain varies throughout the cycle of when a large signal is being
applied. It is this changing voltage gain that is a source of the non-linear distortion.
Noninverting voltage feedback reduces non-linear distortion because the feedback stabilizes the
closed loop voltage gain, making it almost independent of the changes in open loop voltage gain.
As long as loop gain, is much greater than 1, the output voltage equals 1/B times the input
voltage. This implies that output will be a more faithful reproduction of the input .
Consider, under large signal conditions, the open loop OPAMP circuit produces a distortion
voltage, designated v
dist
. It can be represented by connecting a source v
dist
in series with Av
d
.
Without negative feedback all the distortion voltage v
dist
appears at the output. But with negative
feedback, a fraction of v
dist
is feedback to inverting input. This is amplified and arrives at the
output with inverted phase almost completely canceling the original distortion produced by the
output stage.

The first term is the amplified output voltage. The second term in the distortion that appears at
the final output. The distortion voltage is very much, reduced because AB>>1
Bandwidth with Feedback:
The bandwidth of an amplifier is defined as the band of frequencies for which the gain remains
constant. Fig. 3, shows the open loop gain vs frequency curve of 741C OPAMP. From this curve
for a gain of 2 x 10
5
the bandwidth is approximately 5Hz. On the other hand, the bandwidth is
approximately 1MHz when the gain is unity.

Fig. 3
The frequency at which gain equals 1 is known as the unity gain bandwidth. It is the maximum
frequency the OPAMP can be used for.
Furthermore, the gain bandwidth product obtained from the open loop gain vs frequency curve is
equal to the unity gain bandwidth of the OPAMP.
Since the gain bandwidth product is constant obviously the higher the gain the smaller the
bandwidth and vice versa. If negative feedback is used gain decrease from A to A / (1+AB).
Therefore the closed loop bandwidth increases by (1+AB).
Bandwidth with feedback =(1+A B) x (B.W. without feedback)
f
f
=f
o
(1+A B)
Output Offset Voltage:
In an OPAMP even if the input voltage is
zero an output voltage can exist. There are
three cause of this unwanted offset
voltage.
1. Input offset voltage.
2. Input bias voltage.
3. Input offset current.
Fig. 4, shows a feedback amplifier with an
output offset voltage source in series with
the open loop output AV
d
. The actual
output offset voltage with negative
feedback is smaller. The reasoning is
similar to that given for distortion. Some
of the output offset voltage is fed back to
the inverting input. After amplification an
out of phase voltage arrives at the output
canceling most of the original output offset
voltage.

When loop gain AB is much greater than
1, the closed loop output offset voltage is
much smaller than the open loop output
offset voltage.

Fig. 4
Voltage Follower:
The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When
the non-inverting amplifier gives unity gain, it is called voltage follower because the output
voltage is equal to the input voltage and in phase with the input voltage. In other words the
output voltage follows the input voltage.
To obtain voltage follower, R
1
is open circuited and R
f
is shorted in a negative feedback
amplifier of fig. 4. The resultant circuit is shown in fig. 5.
v
out
=Av
d
=A (v
1
v
2
)
v
1
=v
in

v
2
=v
out

v
1
=v
2
if A >>1
v
out
=v
in
.
The gain of the feedback circuit (B) is 1. Therefore
A
f
=1 / B =1

Fig. 5
Voltage shunt Feedback:
Fig. 1, shows the voltage shunt feedback amplifier using OPAMP.

Fig. 1
The input voltage drives the inverting terminal, and the amplified as well as inverted output
signal is also applied to the inverting input via the feedback resistor R
f
. This arrangement forms a
negative feedback because any increase in the output signal results in a feedback signal into the
inverting input signal causing a decrease in the output signal. The non-inverting terminal is
grounded. Resistor R
1
is connected in series with the source.
The closed loop voltage gain can be obtained by, writing Kirchoff's current equation at the input
node V
2
.

The negative sign in equation indicates that the input and output signals are out of phase by 180.
Therefore it is called inverting amplifier. The gain can be selected by selecting R
f
and R
1
(even <
1).
Inverting Input at Virtual Ground:
In the fig. 1, shown earlier, the noninverting terminal is grounded and the- input signal is applied
to the inverting terminal via resistor R
1
. The difference input voltage v
d
is ideally zero, (v
d
=v
O
/
A) is the voltage at the inverting terminals (v
2
) is approximately equal to that of the noninverting
terminal (v
1
). In other words, the inverting terminal voltage (v
1
) is approximately at ground
potential. Therefore, it is said to be at virtual ground.

Input Resistance with Feedback:
To find the input resistance Miller
equivalent of the feedback resistor
R
f
, is obtained, i.e. R
f
is splitted
into its two Miller components as
shown in fig. 2. Therefore, input
resistance with feedback R
if
is then


Fig. 2
Output Resistance with Feedback:
The output resistance with
feedback R
of
is the resistance
measured at the output terminal of
the feedback amplifier. The output
resistance can be obtained using
Thevenin's equivalent
circuit,shown in fig. 3.
i
O
=i
a
+i
b

Since R
O
is very small as compared
to R
f
+(R
1
|| R
2
)
Therefore,i.e. i
O
=i
a

v
O
=R
O
i
O
+A v
d
.
v
d
=v
i
v
2
=0 - B v
O



Fig. 3
Similarly, the bandwidth increases
by (1+AB) and total output offset
voltage reduces by (1+AB).
Example - 1
(a).An inverting amplifier is implemented with R
1
=1K and R
f
=100 K. Find the percentge
change in the closed loop gain A is the open loop gain a changes from 2 x 10
5
V / V to 5 x
10
4
V/V.
(b) Repeat, but for a non-inverting amplifier with R
1
=1K at R
f
=99 K.
Solution: (a). Inverting amplifier

Here R
f
=100 K
R
1
=1K
When,

(b) Non-inverting amplifier

Here R
f
=99 K
R
1
=1K


Example - 2
An inverting amplifier shown in fig. 4 with R
1
= 10 and R
2
= 1M is driven by a source v
1
=
0.1 V. Find the closed loop gain A, the percentage division of A from the ideal value - R
2
/ R
1
,
and the inverting input voltage V
N
for the cases A =100 V/V, 10
5
and 10
5
V/V.
Solution:
we have
when A =10
3
,





Fig. 4

Example - 3
Find V
N
, V
1
and V
O
for the circuit shown in fig. 5.
Solution:
Applying KCL at N

or 2V
N
+V
N
=V
O
.

Now V
O
- V
i
=6 as point A and N are virtually
shorted.
V
O
- V
N
=6 V
Therefore, V
O
=V
N
+6 V

Therefore, V
N
=V
i
=3 V.

Fig. 5


OSCILLATOR
Oscillators:
An oscillator may be described as a source of alternating voltage. It is different than amplifier.
An amplifier delivers an output signal whose waveform corresponds to the input signal but
whose power level is higher. The additional power content in the output signal is supplied by the
DC power source used to bias the active device.
The amplifier can therefore be described as an energy converter, it accepts energy from the DC
power supply and converts it to energy at the signal frequency. The process of energy conversion
is controlled by the input signal, Thus if there is no input signal, no energy conversion takes
place and there is no output signal.
The oscillator, on the other hand, requires no external signal to initiate or maintain the energy
conversion process. Instead an output signals is produced as long as source of DC power is
connected. Fig. 1, shows the block diagram of an amplifier and an oscillator.

Fig. 1
Oscillators may be classified in terms of their output waveform, frequency range, components, or
circuit configuration.
If the output waveform is sinusoidal, it is called harmonic oscillator otherwise it is called
relaxation oscillator, which include square, triangular and saw tooth waveforms.
Oscillators employ both active and passive components. The active components provide energy
conversion mechanism. Typical active devices are transistor, FET etc.
Passive components normally determine the frequency of oscillation. They also influence
stability, which is a measure of the change in output frequency (drift) with time, temperature or
other factors. Passive devices may include resistors, inductors, capacitors, transformers, and
resonant crystals.
Capacitors used in oscillators circuits should be of high quality. Because of low losses and
excellent stability, silver mica or ceramic capacitors are generally preferred.
An elementary sinusoidal oscillator is shown in fig. 2. The inductor and capacitors are reactive
elements i.e. they are capable of storing energy. The capacitor stores energy in its electric
field.Whenever there is voltage across its plates,and the inductor stores energy in its magnetic
field whenever current flows through it. Both C and L are assumed to be loss less. Energy can be
introduced into the circuit by charging the capacitor with a voltage V as shown in fig. 2. As long
as the switch S is open, C cannot discharge and so i=0 and V=0.

Fig. 2
Now S is closed at t =t
o
, This means V rises from 0 to V, J ust before closing inductor current
was zero and inductor current cannot be changed instantaneously. Current increases from zero
value sinusoidally and is given by

The capacitor losses its charge and energy is simply transferred from capacitor to inductor
magnetic field. The total energy is still same. At t =t
1
, all the charge has been removed from the
capacitor plates and voltage reduces to zero and at current reaches to its maximum value. The
current for t>t
1
charges C in the opposite direction and current decreases. Thus LC oscillation
takes places. Both voltage and current are sinusoidal though no sinusoidal input was applied. The
frequency of oscillation is
The circuit discussed is not a practical oscillator because even if loss less components were
available, one could not extract energy with out introducing an equivalent resistance. This would
result in damped oscillations as shown in fig. 3.

Fig. 3
These oscillations decay to zero as soon as the energy in the tank is consumed. If we remove too
much power from the circuit, the energy may be completely consumed before the first cycle of
oscillations can take place yielding the over damped response.
It is possible to supply energy to the tank to make up for all losses (coil losses plus energy
removed), thereby maintaining oscillations of constant amplitude.
Since energy lost may be related to a positive resistance, it follows that the circuit would gain
energy if an equivalent negative resistance were available. The negative resistance, supplies
whatever energy the circuit lose due to positive resistance. Certain devices exhibit negative
resistance characteristics, an increasing current for a decreasing voltage. The energy supplied by
the negative resistance to the circuit, actually comes from DC source that is necessary to bias the
device in its negative resistance region.
Another technique for producing oscillation is to use positive feedback considers an amplifier
with an input signal v
in
and output v
O
as shown in fig. 4.

Fig. 4
The amplifier is inverting amplifier and may be transistorized, or FET or OPAMP. The output is
180 out of phase with input signal v
O
=-A v
in
.(A is negative)
Now a feedback circuit is added. The output voltage is fed to the feed back circuit. The output of
the feedback circuit is again 180 phase shifted and also gets attenuated. Thus the output from
the feedback network is in phase with input signal v
in
and it can also be made equal to input
signal.
If this is so, V
f
can be connected directly and externally applied signal can be removed and the
circuit will continue to generate an output signal. The amplifier still has an input but the input is
derived from the output amplifier. The output essentially feeds on itself and is continuously
regenerated. This is positive feedback. The over all amplification from v
in
to v
f
is 1 and the total
phase shift is zero. Thus the loop gain A is equal to unity.

When this criterion is satisfied then the closed loop gain is infinite. i.e. an output is produced
without any external input.
v
O
=A v
error

=A (v in +v f )
=A (v
in
+ v
O
)
or (1-A )v
O
=A v
in

or
When A = 1, v
O
/ v
in
=
The criterion A = 1 is satisfied only at one frequency.This is known as backhausen criterion.
The frequency at which a sinusoidal oscillator will operate is the frequency for which the total
phase shift introduced, as the signal proceeds form the input terminals, through the amplifier and
feed back network and back again to the input is precisely zero or an integral multiple of 2p.
Thus the frequency of oscillation is determined by the condition that the loop phase shift is zero.
Oscillation will not be sustained, if at the oscillator frequency, A <1 or A >1. Fig. 5, show the
output for two different contions A < 1 and A >1.

Fig. 5
If A is less than unity then A v
in
is less than v
in
, and the output signal will die out, when the
externally applied source is removed. If A>1 then A b v
in
is greater than v
in
and the output
voltage builds up gradually. If A = 1, only then output voltage is sine wave under steady state
conditions.
In a practical oscillator, it is not necessary to supply a signal to start the oscillations. Instead,
oscillations are self-starting and begin as soon as power is applied. This is possible because of
electrical noise present in all passive components.
Therefore, as soon as the power is applied, there is already some energy in the circuit at f
o
, the
frequency for which the circuit is designed to oscillate. This energy is very small and is mixed
with all the other frequency components also present, but it is there. Only at this frequency the
loop gain is slightly greater than unity and the loop phase shift is zero. At all other frequency the
Barkhausen criterion is not satisfied. The magnitude of the frequency component f
o
is made
slightly higher each time it goes around the loop. Soon the f
o
component is much larger than all
other components and ultimately its amplitude is limited by the circuits own non-lineareties
(reduction of gain at high current levels, saturation or cut off). Thus the loop gain reduces to
unity and steady stage is reached. If it does not, then the clipping may occur.
Practically, A is made slightly greater than unity. So that due to disturbance the output does not
change but if A = 1 and due to some reasons if A decreases slightly than the oscillation may
die out and oscillator stop functioning. In conclusion, all practical oscillations involve:
An active device to supply loop gain or negative resistance.
A frequency selective network to determine the frequency of oscillation.
Some type of non-linearity to limit amplitude of oscillations.
Example - 1
The gain of certain amplifier as a function of frequency is A (j) = -16 x 10
6
/ j. A feedback
path connected around it has (j ) = 10
3
/ (20 x 10
3
+ j )
2
. Will the system oscillate? If so, at
what frequency ?
Solution:
The loop gain is
To determine, if the system will oscillate, we will first determine the frequency, if any, at which
the phase angle of equals to 0 or a multiple of 360. Using phasor algebra, we have

This expression will equal -360 if ,

Thus, the phase shift around the loop is -360 at = 2000 rad/s. We must now check to see if the
gain magnitude |A | = 1 at = 2 x 10
3
. The gain magnitude is

Substituting = 2 x 10
3
, we find

Thus, the Barkhausen criterion is satisfied at = 2 x 10
3
rad/s and oscillation occurs at that
frequency (2 x 10
3
/ 2 = 318 .3 Hz).
Transistor Phase Shift Oscillator:
At low frequencies (around 100 kHz or less), resistors and capacitors are usually employed to
determine the frequency of oscillation. Fig. 1 shows transistorized phase shift oscillator circuit
employing RC network. If the phase shift through the common emitter amplifier is 180, then the
oscillation may occur at the frequency where the RC network produces an additional 180 phase
shift.
Since a transistor is used as the active element, the output across R of the feedback network is
shunted by the relatively low input resistance of the transistor, because input diode is a forward
biased diode

Fig. 1
Hence, instead of employing voltage series feedback, voltage shunt feedback is used for a
transistor phase shift oscillator. The load resistance R
L
is also connected via coupling capacitor.
The equivalent circuit using h-parameter is shown in fig. 2.

Fig. 2
For the circuit, the load resistance R
L
may be lumped with R
C
and the effective load resistance
becomes R'
L
(=R
C
|| R
L
). The two h-parameters of the CE transistor amplifier, h
oe
and h
re
are
neglected.
The capacitor C offers some impedance at the frequency of oscillation and, therefore, it is kept as
it is, while the coupling capacitor behaves like ac short. The input resistance of the transistor is
R
i
h
ie
. Therefore the resistance R
3
is selected such that R=R
3
+R
i
=R
3
+h
ie
. This choice makes the
three R C selections alike and simplifies the calculation. The effect of biasing resistor R
1
, R
2
, &
R
E
on the circuit operation is neglected.
Since this is a voltage shunt feedback, therefore instead of finding V
R
/V
O
, we should find the
current gain of the feedback loop.
The simplified equivalent circuit is shown in fig. 3.

Fig. 3
Applying KVL,

Since I
3
and I
b
must be in phase to satisfy Barkhausen criterion, therefore

Also initially I
3
>I
b
, therefore, for oscillation to start,

Therefore, the two conditions must be satisfied for oscillation to start and sustain.
Exampl - 1
(a). Show that the OPAMP phase shifter shown in fig. 4
.
(b) Cascade two identical phase shifters of the type sown in fig. 4. Complete the loop with an
inverting amplifier. Show that the system will oscillate at the frequency f = 1 / 2RC provided
that the amplifier gain exceeds unity.
(c) Show that the circuit produces two quadrature sinusoids (sine wave differing in phase by
90).

Fig. 4
Solution:
(a)The voltage the non-inverting terminal input of the OPAM is given by

Since the differential input voltage of OPAMP is negligible small, therefore, the voltage at the
inverting terminal is also given by

The input impedance of the OPAMP is very large, therefore,

or V
i
- 2V
2
=-V
O

Substituting v
2
in above equation, we get,

Substituting X
C
, we get

Therefore,
and the phase angle between V
O
and V
i
is given by

The magnitude of V
O
/ V
i
is unity for all frequencies and the phase shift provided by this circuit
is 0 for R =0 and 180 for R > infinity.
(b). If two such phase shifters are connected in cascade and an inverting amplifier with gain is
connected in the feedback loop, then the net loop gain becomes
Loop gain = Gain of phase shifter 1 x Gain of phase shifter 2 x
= 1 x 1x
=
Therefore, the oscillation takes place if gain =1, but it is kept >1 so that the losses taking place
in the amplifier can be compensated.
The total phase shift around the loop is given by
total phase shift =-2 tan
-1
(RC) - 2 tan
-1
(RC) + 180
Further, for oscillation to take place the net phase shift around the loop would be 0.Therefore,
-2 tan
-1
(RC) - 2 tan
-1
(RC) + 180 =0
or RC = 1
or f = 1 / 2R C
(c). The phase shift provided by amplifier in the feedback path is 180, therefore, the phase shift
provided by the phase shifters should also be 180 to have 360 or 0 phase shift. Thus ,the phase
shift provided by the individual shifter will be 90 as both are identical. Therefore, the sine wave
produces by two phase shifters are 90 apart and the circuit produces two quadrature sinusoids.
Wien Bridge Oscillator:
The Wien Bridge oscillator is a standard oscillator circuit for low to moderate frequencies, in the
range 5Hz to about 1MHz. It is mainly used in audio frequency generators.
The Wien Bridge oscillator uses a feedback circuit
called a lead lag network as shown in fig. 1.
At very low frequencies, the series capacitor looks
open to the input signal and there is no output signal.
At very high frequencies the shunt capacitor looks
shorted, and there is no output. In between these
extremes, the output voltage reaches a maximum
value. The frequency at which the output is
maximized is called the resonant frequency. At this
frequency, the feedback fraction reaches a maximum
value of 1/3.
At very low frequencies, the phase angle is positive,
and the circuit acts like a lead network. On the other
hand, at very high frequencies, the phase angle is
negative, and the circuit acts like a lag network. In
between, there is a resonant frequency f
r
at which the
phase angle equals 0.
The output of the lag lead network is

Fig. 1

The gain of the feedback circuit is given by

The phase angle between V
out
and V
in
is given by

These equations shows that maximum value of gain occurs at X
C
=R, and phase angle also
becomes 0. This represents the resonant frequency of load lag network. Fig. 2, shows the gain
and phase vs frequency.


Fig. 2
How Wien Bridge Oscillator Works:
Fig. 3, shows a Wien Bridge oscillator. The operational amplifier is used in a non-inverting
configuration, and the lead-lag network provides the feedback. Resistors R
f
and R
1
determine the
amplifier gain and are selected to make the loop gain equal to 1. If the feedback circuit
parameters are chosen properly, there will be some frequency at which there is zero phase shift
in the signal fed back to non inverting terminal. Because the amplifier is non inverting, it also
contributes zero phase shift, so the total phase shift around the loop is 0 at that frequency, as
required for oscillation.
The oscillator uses positive and negative feedback. The positive feedback helps the oscillations
to build up when the power is turn on. After the output signal reaches the desired level the
negative feedback reduces the loop gain is 1. The positive feedback is through the lead lag
network to the non-inverting input. Negative feedback is through the voltage divider to the
inverting input.

Fig. 3
At power up, the tungsten lamp has a low resistance, and therefore, negative feedback is less. For
this, reason, the loop gain AB is greater than 1, and oscillations can build up at the resonant
frequency f
r
. As the oscillations build up, the tungsten lamp heats up slightly and its resistance
increases. At the desired output level the tungsten lamp has a resistance R'. At this point

Since the lead lag network has a gain (=B) of 1/3, the loop gain AB equals unity and than the
output amplitude levels off and becomes constant. The frequency of oscillation can be adjusted
by selecting R and C as

The amplifier must have a closed loop cut off frequency well above the resonant frequency, f
r
.

Fig. 4
Fig. 4, shows another way to represent Wein Bridge oscillator. The lead lag network is the left
side of the bridge and the voltage divider is the right side. This ac bridge is called a Wein Bridge.
The error voltage is the output of the Wein Bridge. When the bridge approaches balance, the
error voltage approaches zero.
Example -1:
Design a Wien-bridge oscillator that oscillates at 25 kHz.
Solution:
Let C
1
=C
2
=0.001 F. Then, the frequency of oscillation is given by,

or,
Let R
1
= 10 K. Then,

or, R
f
= 20K
Tuned Oscillator:
A variety of oscillator circuits can be built using LC tuned circuits. A general form of tuned
oscillator circuit is shown in fig. 1. It is assumed that the active device used in the oscillator has
very high input resistance such as FET, or an operational amplifier.


Fig. 1 Fig. 2
Fig. 2 shows linear equivalent circuit of fig. 1 using an amplifier with an open circuit gain A
v

and output resistance R
O
. It is clear from the topology of the circuit that it is voltage series
feedback type circuit.
The loop gain of the circuit A can be obtained by considering the circuit to be a feedback
amplifier with output taken from terminals 2 and 3 and with input terminals 1 and 3. The load
impedance Z
L
consists of Z
2
in parallel with the series combination of Z
1
and Z
3
. The gain of the
the amplifier without feedback will be given by

The feedback circuit gain is given by

Therefore, the loop gain is given by

If the impedances are pure reactances (either inductive or capacitive), then Z
1
=jX
1
, Z
2
=jX
2
and
Z
3
=jX
3
. Then

For the loop gain to be real (zero phase shift around the loop),
X
1
+X
2
+X
3
=0
and
Therefore, the circuit will oscillate at the resonant frequency of the series combination of X
1
, X
2

and X
3
. Since A must be positive and at leat unity in magnitude, then X
1
and X
2
must have
the same sign (A
v
is positive).In other words, they must be the same kind of reactance, either
both inductive or both capacitive.
The Colpitts Oscillator:
Wein bridge oscillator is not suited to high frequencies (above 1MHz). The main problem is the
phase shift through the amplifier.
The alternative is an LC oscillator, a circuit that can be used for frequencies between 1MHz and
500MHz. The frequency range is beyond the frequency limit of most OPAMPs. With an
amplifier and LC tank circuit, we can feedback a signal with the right amplitude and phase is
feedback to sustain oscillations. Fig. 3, shows the circuit of colpitts oscillator.



Fig. 3 Fig. 4
The voltage divider bias sets up a quiescent operating point. The circuit then has a low frequency
voltage gain of r
c
/ r'
e
where r
c
is the ac resistance seen by the selector. Because of the base and
collector lag networks, the high frequency voltage gain is less then r
c
/ r'
e
.
Fig. 4, shows a simplified ac equivalent circuit. The circulating or loop current in the tank flows
through C
1
in series with C
2
. The voltage output equals the voltage across C
1
. The feedback
voltage v
f
appears across C
2
. This feedback voltage drives the base and sustains the oscillations
developed across the tank circuit provided there is enough voltage gain at the oscillation
frequency. Since the emitter is at ac ground the circuit is a CE connection.
Most LC oscillators use tank circuit with a Q greater than 10. The Q of the feedback circuit is
given by

Because of this, the approximate resonant frequency is

This is accurate and better than 1% when Q is greater than 1%. The capacitance C is the
equivalent capacitance the circulation current passes through. In the Colpitts tank the circulating
current flows through C
1
in series with C
2
.
Therefore C =C
1
C
2
/ (C
1
+C
2
)
The required starting condition for any oscillator is A > 1 at the resonant frequency or A > 1/ .
The voltage gain A in the expression is the gain at the oscillation frequency. The feedback gain
is given by
= v
f
/ v
out
X
C1
/ X
C2

Because same current flow through C
1
and C
2
, therefore
= C
1
/ C
2
; A >1/ v; A>C
1
/ C
2

This is a crude approximation because it ignores the impedance looking into the base. An exact
analysis would take the base impedance into account because it is in parallel with C
2
.
With small , the value of A is only slightly larger than 1/. and the operation is approximately
close A. When the power is switched on, the oscillations build up, and the signal swings over
more and more of ac load line. With this increased signal swing, the operation changes from
small signal to large signal. As this happen, the voltage gain decreases slightly. With light
feedback the value of A can decreases to 1 without excessive clapping.
With heavy feedback, the large feedback signal drives the base into saturation and cut off. This
charges capacitor C
3
producing negative dc clamping at the base and changing the operation
from class A to class C. The negative damping automatically adjusts the value of A to 1.
Example - 1
Design a Colpitts oscillator that will oscillate at 100 kHz.
Solution:
Let us choose R
1
=R
f
= 5 k and C = 0.001 F. From the frequency expression,

The quality factor (Q) of the LC circuit is given by:

Hartley Oscillator:
Fig. 5, shows Hartley oscillator when the LC tank is resonant, the circulating current flows
through L
1
in series with L
2
. Thus, the equivalent inductance is L =L
1
+L
2
.

Fig. 5
In the oscillator, the feedback voltage is developed by the inductive voltage divider, L
1
& L
2
.
Since the output voltage appears across L
1
and the feedback voltage across L
2
, the feedback
fraction is
= V / V
out
=X
L2
/ X
L1
=L
2
/ L
1

As usual, the loading effect of the base is ignored. For oscillations to start, the voltage gain must
be greater than 1/ . The frequency of oscillation is given by

Similarly, an opamp based Hartley oscillator circuit is shown in fig. 6.

Fig. 6
Crystal Oscillator:
Some crystals found in nature exhibit the piezoelectric effect i.e. when an ac voltage is applied
across them, they vibrate at the frequency of the applied voltage. Conversely, if they are
mechanically pressed, they generate an ac voltage. The main substances that produce this
piezoelectric effect are Quartz, Rochelle salts, and Tourmaline.
Rochelle salts have greatest piezoelectric activity, for a given ac voltage, they vibrate more than
quartz or tourmaline. Mechanically, they are the weakest they break easily. They are used in
microphones, phonograph pickups, headsets and loudspeakers.
Tourmaline shows the least piezoelectric activity but is a strongest of the three. It is also the most
expensive and used at very high frequencies.
Quartz is a compromise between the piezoelectric activity of Rochelle salts and the strength of
tourmaline. It is inexpensive and easily available in nature. It is most widely used for RF
oscillators and filters.
The natural shape of a quartz crystal is a hexagonal prism with pyramids at the ends. To get a
useable crystal out of this it is sliced in a rectangular slap form of thickness t. The number of
slabs we can get from a natural crystal depends on the size of the slabs and the angle of cut.

Fig. 1
For use in electronic circuits, the slab is mounted between two metal plates, as shown in fig. 1. In
this circuit the amount of crystal vibration depends upon the frequency of applied voltage. By
changing the frequency, one can find resonant frequencies at which the crystal vibrations reach a
maximum. Since the energy for the vibrations must be supplied by the ac source, the ac current is
maximized at each resonant frequency. Most of the time, the crystal is cut and mounted to
vibrate best at one of its resonant frequencies, usually the fundamental or lowest frequency.
Higher resonant frequencies, called overtones, are almost exact multiplies of the fundamental
frequency e.g. a crystal with a fundamental frequency of 1 MHz has a overtones of 2 MHz, 3
MHz and so on. The formula for the fundamental frequency of a crystal is
f =K / t.
where K is a constant that depends on the cut and other factors, t is the thickness of crystal, f is
inversely proportional to thickness t. The thinner the crystal, the more fragile it becomes and the
more likely it is to break because of vibrations. Quartz crystals may have fundamental frequency
up to 10 MHz. To get higher frequencies, a crystal is mounted to vibrate on overtones; we can
reach frequencies up to 100 MHz.
AC Equivalent Circuit:
When the mounted crystal is not vibrating, it is equivalent to a capacitance C
m
, because it has
two metal plates separated by dielectric, C
m
is known as mounting capacitance.

Fig. 2
When the crystal is vibrating, it acts like a tuned circuit. Fig. 2, shows the ac equivalent circuit of
a crystal vibrating at or near its fundamental frequency. Typical values are L is henrys, C in
fractions of a Pico farad, R in hundreds of ohms and C
m
in Pico farads
L
s
=3Hz, C
s
=0.05 pf, R
s
=2K, C
m
=10 pf.
The Q of the circuit is very very high. Compared with L-C tank circuit. For the given values, Q
comes out to be 3000. Because of very high Q, a crystal leads to oscillators with very stable
frequency values.
The series resonant frequency f
S
of a crystal is the sonant frequency of the LCR branch. At this
frequency, the branch current reaches a maximum value because L
s
resonant with C
S.


Above f
S
, the crystal behaves inductively. The parallel resonant frequency is the frequency at
which the circulating or loop current reaches a maximum value. Since this loop current must
flow through the series combination of C
S
and C
m
, the equivalent C
loop
is

Since C
loop
>C
S
, therefore, f
p
>f
S
.
Since C
m
>C
S
, therefore, C
m
|| C
S
is slightly
lesser than C
S
. Therefore f
P
is slightly greater
than f
S
. Because of the other circuit capacitances
that appear across C
m
the actual frequency will
lie between f
S
and f
P
. f
S
and f
P
are the upper and
lower limits of frequency. The impedance of the
crystal oscillator can be plotted as a function of
frequency as shown in fig. 3.
At frequency f
S
, the circuit behaves like
resistive circuit. At f
P
the impedance reaches to
maximum, beyond f
P
, the circuit is highly
capacitive.
The frequency of an oscillator tends to change
slightly with time. The drift is produced by
temperature, aging and other causes. In a crystal
oscillator the frequency drift with time is very
small, typically less than 1 part in 10
6
per day.
They can be used in electronic wristwatches. If
the drift is 1 part in 10
10
, a clock with this drift
will take 30 years to gain or lose 1 sec.

Fig. 3
Crystals can be manufactured with values of f
s
as low as 10 kHz; at these frequencies the crystal
is relatively thick. On the high frequency side, f
s
can be as high as 1- MHz; here the crystal is
very thin.
The temperature coefficient of crystals is usually small and can be made zero. When extreme
temperature stability is required, the crystal may be housed in an oven to maintain it at a constant
temperature. The high Q of the crystal also contributes to the relatively drift free oscillation of
crystal oscillators.
Example - 1
The parameters of the equivalent circuit of a crystal are given below:
L =0.4 H, C
S
= 0.06 pF, R = 5 k, C
m
=1.0 pF.
Determine the series and parallel resonant frequencies of the crystal.
Solution:
With reference to fig. 2, the admittance of the crystal Y is given by

where,

and
The resonant frequencies are obtained by putting B =0. Thus,

Consider the term C
S
R
2
/ L
S
=C
S
R / [L R]. In a crystal, the time constant (L / R) is very much
greater than C
S
R. Thus the ratio is very much less than 1. For the values given, this ratio is of
the order of10
-6
. Neglecting this term in comparison with 2, we get two roots as

where,
s
and
p
are the series and parallel resonant frequencies respectively. Substituting the
values, we get

s
= 6.45 M Hz. and
p
=6.64 MHz
Crystal Oscillators:
Fig. 4, shows a colpitts crystal oscillator.

Fi. 4
The capacitive voltage divider produces the feedback voltage for the base of transistor. The
crystal acts like an inductor that resonates with C
1
and C
2
. The oscillation frequency is between
the series and parallel resonant frequencies.
Example-2:
If the crystal of example-1 is used in the oscillator circuit as shown fig. 5, determine the values
of R for the circuit to oscillate.

Fig. 5
Solution:
The equivalent circuit of crystal (discussed earlier) shows that it has a parallel resonant f
r

frequency (
p
) at which the impedance becomes maximum. The amplified signal output of the
circuit is applied across the potential divider consisting of R and the crystal circuit. At the
resonant frequency the impedance of crystal becomes maximum (magnitude R) and thus the loop
gain will be greater than or equal to unity. At frequencies away from
p
the loop gain becomes
less than unity. The loop base shift is also zero around
p
. Thus both the conditions required for
sustained oscillations are satisfied and the circuit oscillates.
The value of G of the crystal at =
p
is given by

Thus the resistor R should be less than 5x10
6
.
Differential Amplifier:
The basic differential amplifier is shown in fig. 1.

Fig. 1
Since there are two inputs superposition theorem can be used to find the output voltage. When
V
b
=0, then the circuit becomes inverting amplifier, hence the output due to V
a
only is
V
o(a)
=-(R
f
/ R
1
) V
a

Similarly when, V
a
=0, the configuration is a inverting amplifier having a voltage divided
network at the noninverting input

Example - 1
Find v
out
and i
out
for the circuit shown in fig. 2. The input voltage is sinusoidal with amplitude of
0.5 V.

Fig. 2
Solution:
We begin by writing the KCL equations at both the +and terminals of the op-amp.
For the negative terminal,

Therefore,
15 v
-
=v
out

For the positive terminal,

This yields two equations in three unknowns, v
out
, v
+
and v
-
. The third equation is the
relationship between v
+
and v
-
for the ideal OPAMP,
v
+
=v
-

Solving these equations, we find
v
out
=10 v
in
= 5 sint V
Since 2 k resistor forms the load of the op-amp, then the current i
out
is given by

Example - 2
For the different amplifier shown in fig. 3, verify that


Fig. 3
Solution:
Since the differential input voltage of OPAMP is negligible, therefore,
v
1
=v
x

and v
2
=v
y

The input impedance of OPAMP is very large and, therefore, the input current of OPAMP is
negligible.
Thus
And
From equation (E-1)

or
From equation (E-2)

or
The OPAMP3 is working as differential amplifier, therefore,

Integrator:
A circuit in which the output voltage waveform is the integral of the input voltage waveform is
called integrator. Fig. 4, shows an integrator circuit using OPAMP.

Fig. 4
Here, the feedback element is a capacitor. The current drawn by OPAMP is zero and also the V
2

is virtually grounded.
Therefore, i
1
=i
f
and v
2
=v
1
=0

Integrating both sides with respect to time from 0 to t, we get
Differentator:
A circuit in which the output voltage waveform is the differentiation of input voltage is called
differentiator.as shown in fig. 1.



Fig. 1
The expression for the output voltage can be obtained from the Kirchoff's current equation
written at node v
2
.

Thus the output v
o
is equal to the RC times
the negative instantaneous rate of change
of the input voltage v
in
with time. A cosine
wave input produces sine output. fig. 1
also shows the output waveform for
different input voltages.
The input signal will be differentiated
properly if the time period T of the input
signal is larger than or equal to R
f
C.
T R
f
C
As the frequency changes, the gain
changes. Also at higher frequencies the
circuit is highly susceptible at high
frequency noise and noise gets amplified.
Both the high frequency noise and
problem can be corrected by additing, few
components. as shown in fig. 2.

Fig. 2
Voltage to current converter:
Fig. 3, shows a voltage to current converter in which load resistor R
L
is floating (not connected
to ground).
The input voltage is applied to the non-inverting input terminal and the feedback voltage across
R drives the inverting input terminal. This circuit is also called a current series negative
feedback, amplifier because the feedback voltage across R depends on the output current i
L
and
is in series with the input difference voltage v
d
.
Writing the voltage equation for the
input loop.
v
in
=v
d
+v
f

But v
d
since A is very large,therefore,
v
in
=v
f

v
in
=R i
in
i
in
=v
in
/ R.
and since input current is zero.
i
L
=i
in
=v
in
./ R
The value of load resistance does not
appear in this equation. Therefore, the
output current is independent of the
value of load resistance. Thus the input
voltage is converted into current, the
source must be capable of supplying this
load current.

Fig. 3
Grounded Load:
If the load has to be grounded, then the above circuit cannot be used. The modified circuit is
shown in fig. 4.
Since the collector and emitter currents are equal to a
close approximation and the input impedance of
OPAMP is very high,the load current also flows
through the feedback resistor R. On account of this,
there is still current feedback, which means that the
load current is stabilized.
Since v
d
=0

\ v
2
=v
1
=v
in
\ i
out
=(v
CC
v
in
) / R
Thus the load current becomes nearly equal to i
out
.
There is a limit to the output current that the circuit
can supply. The base current in the transistor equals
i
out
/ b
dc
. Since the op-amp has to supply this base
current i
out
/ b
dc
must be less than I
out
(max) of the op-

amp, typically 10 to 15mA.
There is also a limit on the output voltage, as the load
resistance increases, the load voltage increases and
then the transistor goes into saturation. Since the
emitter is at V
in
w. r. t. ground, the maximum load
voltage is slightly less than V
in
.
Fig. 4
In this circuit, because of negative feedback V
BE
is automatically adjusted. For instance, if the
load resistance decreases the load current tries to increase. This means that more voltage is
feedback to the inverting input, which decreases V
BE
just enough to almost completely nullify
the attempted increase in load current. From the output current expression it is clear that as V
in

increases the load current decreases.
Another circuit in which load current increases as V
in
increases is shown in fig. 5.
The current through the first
transistor is
i =v
in
/ R
This current produces a collector
voltage of v
C
=v
CC
i R =v
CC
v
in

Since this voltage drives the non-
inverting input of the second op-
amp. The inverting voltage is v
CC
-
v
in
to a close approximation. This
implies that the voltage across the
final R is
v
CC
- (v
CC
- v
in
) =v
in

and the output current .
i
out
=v
in
/ R
As before, this output current must
satisfy the condition,that I
out
/ b
dc

must be less than the I
out
(max) of the
OPAMP. Furthermore, the load
voltage cannot exceed v
CC
- v
in

because of transistor saturation,
therefore I
out
R must be less than
v
CC
- v
in
.This current source produces

Fig. 5
unidirectional load current. fig. 6,
shows a Howland current source,
that can produce a bi-directional
load current.

The maximum load current is V
CC
/ R. In this
circuit v in may be positive or negative.

Fig. 6
Current to voltage converter:
The circuit shown in fig. 1, is a current to voltage converter.

Fig. 1
Due to virtual ground the current through R is zero and the input current flows through R
f
.
Therefore,
v
out
=-R
f
* i
in

The lower limit on current measure with this circuit is set by the bias current of the inverting
input.
Example 1:
For the current to current converter shown in fig. 2, prove that


Fig. 2
Solution:
The current through R
1
can be obtained from the current divider circuit.

Since, the input impedance of OPAMP is very large, the input current of OPAMP is negligible.
Thus,