Fundamentals of VHDL Programming

Introduction:
VHDL (Very High Speed IC Hardware description Language is one of the
standard hardware description language used to design digital systems! VHDL can
"e used to design the lowest le#el (gate le#el of a digital system to the highest
le#el (VLSI module! VHDL though "eing a rigid language with a standard set of
rules allows the designer to use different methods of design gi#ing different
perspecti#es to the digital system!
$ther than VHDL there are many hardware description languages a#aila"le in
the mar%et for the digital designers such as Verilog& '()L& P'L'S*& C+PL& and etc
"ut VHDL and Verilog are the most widely used HDLs! ,he ma-or difference "etween
hardware description programming languages and others is the integration of time!
,iming specifications are used to incorporate propagation delays present in the
system!
,ypes of .epresentation:
VHDL representation can "e seen as te/t file descri"ing a digital system! ,he
digital system can "e represented in different forms such as a "eha#ioral model or a
structural model! *ost commonly %nown as le#els of a"straction& these le#els help
the designer to de#elop comple/ systems efficiently!
Behavioral Model:
(eha#ioral le#el descri"es the system the way it "eha#es instead of a lower
a"straction of its connections! (eha#ioral model descri"es the relationship
"etween the input and output signals! ,he description can "e a .egister
,ransfer Le#el (.,L or 'lgorithmic (set of instruction or simple (oolean
e0uations!
Register Transfer Level: .,L typically represents data flow within
the systems li%e data flow "etween registers! .,L is mostly used for design of
com"inational logics!
Algorithmic Level: In this method& specific instruction set of
statements define the se0uence of operations in the system! 'lgorithmic
le#el is mostly used for design of se0uential logics!
Structural Model:
Structural le#el descri"es the systems as gates or component "loc%
interconnected to perform the desired operations! Structural le#el is primarily
the graphical representation of the digital system and so it is closer to the
actual physical representation of the system!
VHDL Programming Structure:
)ntity and 'rchitecture are the two main "asic programming structures in
VHDL!
Entity: )ntity can "e seen as the "lac% "o/ #iew of the system! 1e define the
inputs and outputs of the system which we need to interface!
)ntity '2D3',) is
Port (': in std4logic5
(: in std4logic5
6: out std4logic5
)nd entity '2D3',)5
)ntity name '2D3',) is gi#en "y the programmer& each entity must ha#e a
name! ,here are certain naming con#entions which will "e e/plained later in the
tutorial!


Architecture: 'rchitecture defines what is in our "lac% "o/ that we
descri"ed using )2,I,6! 1e can use either "eha#ioral or structural models to
descri"e our system in the architecture! In 'rchitecture we will ha#e
interconnections& processes& components& etc!
'rchitecture '2D7 of '2D3',) is
88declarations
(egin
88statements
6 9: ' '2D (5
)nd architecture '2D75
)ntity name or architecture name is user defined! Identifiers can ha#e
uppercase alpha"ets& lowercase alpha"ets& and num"ers and underscore
(4!First letter of identifier must "e an alpha"et and identifier cannot end with
an underscore! In VHDL& %eywords and user identifiers are case insensiti#e!
VHDL is strongly typed language i!e! e#ery o"-ect must "e declared!
+nderstanding through e/amples:
Note:
7 )#ery statement should end with a semi8colon
; Statement followed "y 88 is a comment statement
(asic VHDL operations:
'2D gate:
88This is a comment line. Welcome to VHDL programming
88The next two lines are the libraries that are included
LIBRARY IEEE
!SE IEEE"ST#$L%&I'$(()*"ALL
--The andgate entity is defined. In this module and ! are defined as the
input ports of the
--half-adder and " is defined as the output port. The #eyword in and out
following the colon
-- defines it as input and output ports respecti$ely and these ports can
support std%logic data
--types defined by the library included abo$e
entity andgate is
+ort ('&(:in std4logic5
C:out std4logic5
end andgate5
architecture " of andgate is
,egin
--and is a basic VHDL operation. &' represents the signal assignment
C9:' and (5
end "5
2ow lets implement an $. gate!
%R gate:
LIBRARY IEEE
!SE IEEE"ST#$L%&I'$(()*"ALL
entity orgate is
+ort ('&(:in std4logic5
C:out std4logic5
end orgate5
architecture " of orgate is
,egin
C9:' or (5
end "5
Similarly you can try out other "asic gates li%e 2'2D& 2$.& <$.& 2$, and
get familiari=ed with the entity and architecture declaration!
*odels:
Implementation of Half 'dder using (eha#ioral and Structural *odels:
,he section of VHDL code "elow implements the half >adder!
Behavioral Modeling of -alf Adder
RTL:
LIBRARY IEEE
!SE IEEE"ST#$L%&I'$(()*"ALL
entity half4adder is
+ort (' &(:in std4logic5
S& C:out std4logic5
end half4adder5
architecture "eha#ioral of half4adder is
,egin
.. (um ( is calculated as xor !. The output is obtained after )ns delay. --(imilarly
carry " is obtained
88 after *ns might be used to specify the delays and it wor#s fine with simulation.
!ut you might want to ---use the gate delays which will be added by default with
the LT+, boards that you use for lab
S9:' /or ( after ?ns5
C9:' and ( after ?ns5
end a5
Algorithmic:
LIBRARY IEEE
!SE IEEE"ST#$L%&I'$(()*"ALL
entity half8adder is
+ort('& (:in std4logic5
S& C:out std4logic5
end half8adder5
architecture "eha#ior of half8adder is
,egin
---rocess statement can be used for se.uential statements and gi$e a more
powerful description of
--beha$ior. In the following line sum denotes the name of the process and /! are
the sensiti$ity list
--which defines when the process should be re-e$aluated
sum: process('&(
,egin
--If loop. (imilar to other programming languages
if(':(then
S9:@A@5
else
S9:(' or (5
end if5
end +rocess5
carry :+rocess('&(
,egin
case ' is
when @A@:BC9:'5
when @7@:BC9:(5
end case
end +rocess
end "eha#ior5
Structural A++roach:
LI!,,0 I+++1
2(+ I+++.(TD%L34I"%5567.LL1
entity half8adder is
+ort('& (:in std4logic5
S&C :out std4logic5
end half8adder5
entity andgate is
+ort(<& 6:in std4logic5
C:out std4logic5
end andgate5
architecture "eha#ioral of andgate is
,egin
C 9: < and 65
end "eha#ioral5
entity /orgate is
+ort(L& *:in std4logic5
2:out std4logic5
end /orgate5
architecture "eha#ioral of /orgate is
,egin
S9:L /or *5
end "eha#ioral5
architecture structural of half8adder is
--andgate is defined as a sub-bloc# of the entity half-adder
--"omponent declaration
com+onent andgate
+ort(<& 6:in std4logic5 C:out std4logic5
end component5
com+onent /orgate
+ort(L& *:in std4logic5 2:out std4logic5
end component5
,egin
88"omponent Instantiation
88-ort mapping of the input and output ports
'A:andgate port map( <:B'56:B(5C:BC5
<A:/orgate port map( L:B'5*:B(52:BC5
end structural5