Dept. of Mechatronics Engg.

EM 242:
DIGITAL LOGIC DESIGN
Assist. Prof. : Sarmad Shams
sarmadshams@yahoo.com
1
Week : 14
Ch: 8
Dept. of Mechatronics Engg.
1. Asynchronous Counters
1. 3-bits Asynchronous Counters
2. Decade Counters
3. The 74LS93A Asynchronous Counter
2. Synchronous Counters
1. 4-bits Synchronous Counters
2. BCD/Decade Counters
3. Up/Down Synchronous Counters
3. Cascaded Counters
4. Counter Decoding
5. Counter Application
Ch8 : Counters
2
As you know, the binary count sequence follows a
familiar pattern of 0s and 1s
LSB changes on every
number.
The next bit changes
on every other number.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The next bit changes on
every fourth number.
Counting in Binary
A counter can form the same pattern of 0s and 1s with
logic levels. The first stage in the counter represents the
least significant bit notice that these waveforms follow
the same pattern as counting in binary.
0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0
0 0 0 0 1 1 1 1 0
LSB
MSB
Counting in Binary
In an asynchronous counter, the clock is applied only to
the first stage. Subsequent stages derive the clock from
the previous stage.
The three-bit asynchronous counter shown is typical. It uses J-K
flip-flops in the toggle mode.
CLK
K
0
J
0
Q
0
Q
0
C C C
J
1
J
2
K
1
K
2
Q
1
Q
2
Q
1
HIGH
3-bit Asynchronous Counter
CLK
Q
0
Q
1
Q
2
1 2 3 4 5 6 7 8
1
0
1
0
1
0
1
0 0
1 0 1 0 0 1 0 1 0
0 0 1 1 0 1 1 0 0
Notice that the Q
0
output is triggered on the leading edge of
the clock signal. The following stage is triggered from Q
0
.
The leading edge of Q
0
is equivalent to the trailing edge of
Q
0
. The resulting sequence is that of an 3-bit binary up
counter.
3-bit Asynchronous Counter
CLK
K
0
J
0
Q
0
Q
0
C C C
J
1
J
2
K
1
K
2
Q
1
Q
2
Q
1
HIGH
Asynchronous counters are sometimes called ripple
counters, because the stages do not all change together.
For certain applications requiring high clock rates, this is
a major disadvantage.
Notice how delays
are cumulative as
each stage in a
counter is clocked
later than the
previous stage.
CLK
Q
0
Q
1
Q
2
1 2 3 4
Q
0
is delayed by 1 propagation delay, Q
2
by 2 delays and Q
3
by 3 delays.
Propagation Delay
This counter uses partial
decoding to recycle the count
sequence to zero after the
1001 state. The flip-flops are
trailing-edge triggered, so
clocks are derived from the Q
outputs. Other truncated
sequences can be obtained
using a similar technique.
Asynchronous Decade Counter
When Q
1
and Q
3
are HIGH together, the counter is cleared by a glitch on the CLR line.
1 2 3 4 5 6 7 8 9 10
Glitch
Glitch
CLK
Q
0
Q
1
Q
2
Q
3
CLR

Glitch
Glitch
Asynchronous Decade Counter
CLK
K
0
J
0
Q
0
C C C
J
1
J
2
K
1
K
2
Q
1
Q
2
HIGH
C
J
3
K
3
Q
3
CLR
(9) (12) (8) (11)
(1)
(14)
(2)
(3)
The 74LS93A has one independent toggle J-K flip-flop
driven by CLK A and three toggle J-K flip-flops that form
an asynchronous counter driven by CLK B.
CLK A
K
0
J
0
Q
0
C C C
J
1
J
2
K
1
K
2
Q
1
Q
2
C
J
3
K
3
Q
3
CLK B
The counter can be extended to form a 4-bit counter by connecting
Q
0
to the CLK B input. Two inputs are provided that clear the count.

RO (1)
RO (2)
All J and K inputs
are connected
internally HIGH
The 74LS93A Asynchronous Counter
Synchronous Counters
11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Decimal Binary BCD
0001
0001
0001
0001
0001
0001
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0000
0001
0010
0011
0100
0101
In a synchronous counter all flip-flops
are clocked together with a common clock
pulse. Synchronous counters overcome the
disadvantage of accumulated propagation
delays, but generally they require more
circuitry to control states changes.
synchronous counter has the same count
sequence asynchronous counter.
Synchronous Counters
Outputs Logic for inputs
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0
Q
2
Q
1
Q
0
J
2
= Q
0
Q
1
K
2
= Q
0
Q
1
J
1
= Q
0
K
1
= Q
0
J
0
= 1 K
0
= 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 1 1
0 0 0 0
1 1 1 1
Analysis of Synchronous Counters
K
0
J
0
Q
0
C C C
J
1
J
2
K
1
K
2
Q
0
Q
1
Q
0
Q
1
Q
2
CLK
HIGH
J
0
Q
0
C
K
0
Q
0
HIGH
CLK
FF0
J
1
Q
1
C
K
1
Q
1
FF1
J
2
Q
2
C
K
2
Q
2
FF2
J
3
Q
3
C
K
3
Q
3
FF3
Q
1
Q
0
Q
2
Q
1
Q
0 G
1
G
2
Q
0
Q
1
Q
2
Q
3
The 4-bit binary counter
has one more AND gate
than the 3-bit counter just
described. The shaded
areas show where the
AND gate outputs are
HIGH causing the next
FF to toggle.
A 4-bit Synchronous Binary Counter
With some additional logic, a binary counter can be
converted to a BCD synchronous decade counter. After
reaching the count 1001, the counter recycles to 0000,
This is called lower truncation..
This gate detects 1001, and causes FF3 to toggle on the next
clock pulse. FF0 toggles on every clock pulse. Thus, the count
starts over at 0000.
CLK
J
0
K
0
C
HIGH
FF0 FF1 FF2 FF3
Q
3
Q
0
Q
0
J
1
K
1
C
Q
1
Q
1
J
2
K
2
C
Q
2
Q
2
J
3
K
3
C
Q
3
Q
3
Q
0
Q
3
BCD Decade Counter
Waveforms for the decade counter:
1 2 3 4 5 6 7 8
1
0
1
0
1
0
1
0 0
1 0 1 0 0 1 0 1 0
0
0
1
1 0
1
1
0
0
9 10
0
0
0
0 1
1
0
0
0
1
0
0
0
0
0
0
0
These same waveforms can be obtained with an asynchronous
counter in IC form the 74LS90/74LS93. It is available in a dual
version the 74LS390, which can be cascaded. It is slower than
synchronous counters (max count frequency is 35 MHz), but is
simpler.
CLK
Q
0
Q
1
Q
2
Q
3
BCD Decade Counter
CTR DIV 16
(1)
(9)
(7)
(10)
C
(2)
(3) (4) (5) (6)
(14) (13) (12) (11)
TC = 15
(15)
The 74LS163 is a 4-bit IC synchronous counter with additional
features over a basic counter. It has parallel load, a CLR input, two
chip enables, and a ripple count output that signals when the count
has reached the terminal count.

Data inputs
Data outputs
CLR
LOAD
ENT
ENP
CLK
RCO
Q
0
Q
1
Q
2
Q
3
D
0
D
1
D
2
D
3
A 4-bit Synchronous Binary Counter
Data
inputs
Data
outputs
CLR
LOAD
ENT
ENP
CLK
RCO
Q
0
Q
1
Q
2
Q
3
D
0
D
1
D
2
D
3
Clear Preset
Count Inhibit
12 13 14 15 0 1 2
A 4-bit Synchronous Binary Counter
An up/down counter is capable of progressing in either
direction depending on a control input.
CLK
Q
0
Q
1
Q
2
K
0
J
0
C C C
J
1
J
2
K
1
K
2
HIGH
UP/DOWN
UP
DOWN
FF0 FF1 FF2
Q
0
.
UP

Q
0
.
DOWN

Q
0
Q
1
Q
2
Up/Down Synchronous Counters
The 74HC191 has the same
inputs and outputs but is a
synchronous up/down binary
counter.
(10) (15)
(4)
(5)
(11)
(14)
(1) (9)
(3) (2) (6) (7)
(12)
(13)
Data inputs
Data outputs
MAX/MIN
CLK
Q
0
Q
1
Q
2
Q
3
LOAD
CTEN
RCO
D/U
D
0
D
1
D
2
D
3
C
CTR DIV 10
74HC190
(10) (15)
(4)
(5)
(11)
(14)
(1) (9)
(3) (2) (6) (7)
(12)
(13)
Data inputs
Data outputs
MAX/MIN
CLK
Q
0
Q
1
Q
2
Q
3
LOAD
CTEN
RCO
D/U
D
0
D
1
D
2
D
3
C
CTR DIV 16
74HC191
The 74HC190 is a high speed
CMOS synchronous up/down
decade counter with parallel load
capability. It also has a active
LOW ripple clock output (RCO)
and a MAX/MIN output when the
terminal count is reached.
Up/Down Synchronous Counters
16

in
256

in
HIGH
CLK
Q
0
Q
1
Q
2
C
Counter 1 Counter 2
C
CTEN
CTEN
CTR DIV 16 CTR DIV 16
Q
3
Q
0
Q
1
Q
2
Q
3
TC TC
f
in
a) Each counter divides the frequency by 16. Thus the
modulus is 16
2
= 256.
Cascading is a method of achieving higher-modulus counters. For
synchronous IC counters, the next counter is enabled only when
the terminal count of the previous stage is reached.
a) What is the modulus of the cascaded DIV 16 counters?
b) If f
in
=100 kHz, what is f
out
?

f
out
b) The output frequency is 100 kHz/256 = 391 Hz
Cascaded counters
Cascaded Counters Truncated Sequences
22
The counter shown is Modulus 65,536 (2
16
)
Lets assume that a certain application requires a divide by 40,000 counter
(Mod 40000)
We have to delete the difference (65536-40000=25536) from the counter
to achieve Modulus 40000. This can be done by loading the hexa-decimal
value of 25536 i.e. 63C0. This is called Upper Truncation.
Decoding is the detection of a binary number and can be
done with an AND gate.
HIGH
CLK
1 1 1
LSB MSB
Decoded 4
Q Q
Q
0
1
2
QQ
2 1 0
Q
C
J
2
K
2
Q
2
Q
2
C
J
1
K
1
Q
1
Q
1
C
J
0
K
0
Q
0
Q
0
What number is decoded by
this gate?
Counter Decoding
The decade counter shown previously incorporates
partial decoding (looking at only the MSB and the
LSB) to detect 1001. This was possible because this is
the first occurrence of this combination in the sequence.
CLK
J
0
K
0
C
HIGH
FF0 FF1 FF2 FF3
Q
3
Q
0
Q
0
J
1
K
1
C
Q
1
Q
1
J
2
K
2
C
Q
2
Q
2
J
3
K
3
C
Q
3
Q
3
Detects 1001 by looking only at two bits
Partial Decoding
The divide-by-60 counter in the text also uses partial
decoding to clear the tens count when a 6 was detected.
CLR CTR DIV 6
HIGH CTEN
C
Q
3
CTR DIV 10
Q
2
Q
1
Q
0
CTEN TC = 9
RCO
C
CLK
units
CLR CLR
To next
counter
Q
3
Q
2
Q
1
Q
0
Decode 6
Decode 59
TC = 59
To ENABLE
of next CTR
tens
The divide characteristic illustrated here is a good way to obtain a
lower frequency using a counter. For example, the 60 Hz power line
can be converted to 1 Hz.
Resetting the Count with a Decoder
Counter Applications Digital Clock
26
Counter Applications Automobile Parking Control
27
Counter Applications Parallel to serial data conversion
28
Read Chapter 8
Section 8-1~3
Section 8-5~8