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Till now we have been looking into VLSI testing, only from the context where the circuit needs to be put
to a test mode for validating that it is free of faults. Following that, the circuits tested OK are shipped
to the customers with the assumption that they would not fail within their expected life time; this is
called off-line testing. In other words, in off-line testing, a circuit is tested once and for all, with the hope
that once the circuit is verified to be fault free it would not fail during its expected life-time. However,
this assumption does not hold for modern day ICs, based on deep sub-micron technology, because they
may develop failures even during operation within expected life time. To cater to this problem
sometimes redundant circuitry are kept on-chip which replace the faulty parts. To enable replacement
of faulty circuitry, the ICs are tested before each time they startup. If a fault is found, a part of the circuit
(having the fault) is replaced with a corresponding redundant circuit part (by re-adjusting connections).
Testing a circuit every time before they startup, is called Built-In-Self-Test (BIST). In this module we will
study details of BIST. Once BIST finds a fault, the readjustment in connections to replace the faulty part
with a fault free one is a design problem and would be not be discussed here.

2. Basic architecture of BIST


As discussed in the last section, BIST is basically same as off-line testing using ATE where the test pattern
generator and the test response analyzer are on-chip circuitry (instead of equipments). As equipments
are replaced by circuitry, so it is obvious that compressed implementations of test pattern generator
and response analyzer are to be designed. The basic architecture of BIST is shown in Figure 1.
As shown in Figure 1, BIST circuitry comprises the following modules (and the following functionalities)

1. Hardware Test Pattern Generator: This module generates the test patterns required to sensitize
the faults and propagate the effect to the outputs (of the CUT). As the test pattern generator is
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a circuit (not equipment) its area is limited. So storing and then generating test patterns
obtained by ATPG algorithms on the CUT (discussed in Module XI) using the hardware test
pattern generator is not feasible. In other words, the test pattern generator cannot be a
memory where all test patters obtained by running ATPG algorithms (or random pattern
generation algorithms) on the CUT are stored and applied during execution of the BIST. Instead,
the test pattern generator is basically a type of register which generates random patterns which
act as test patterns. The main emphasis of the register design is to have low area yet generate
as many different patterns (from 0 to 2^n , if there are n flip-flops in the register) as possible.

2. Input Mux: This multiplexer is to allow normal inputs to the circuit when it is operational and
test inputs from the pattern generator when BIST is executed. The control input of the
multiplexer is fed by a central test controller.

3. Output response compactor: Output response compacter performs lossy compression of the
outputs of the CUT. As in the case of off-line testing, in BIST the output of the CUT is to be
compared with the expected response (called golden signature); if CUT output does not match
the expected response, fault is detected. Similar to the situation for test pattern generator,
expected output responses cannot be stored explicitly in a memory and compared with the
responses of the CUT. So CUT response needs to be compacted such that comparisons with
expected responses (golden signatures) become simpler in terms of area of the memory that
stores the golden signatures.

4. ROM: Stores golden signature that needs to be compared with the compacted CUT
response.
5. Comparator: Hardware to compare compacted CUT response and golden signature (from ROM).
6. Test Controller: Circuit to control the BIST. Whenever an IC is powered up (signal start BIST is made
active) the test controller starts the BIST procedure. Once the test is over, the status line is made high if
fault is found. Following that, the controller connects normal inputs to the CUT via the multiplexer, thus
making it ready for operation.

Among the modules discussed above, the most important ones are the hardware test pattern
generator and the response compactor. The other ones are standard digital blocks [1]. In the next
two sections we will discuss these two blocks in details.
Hardware pattern generator
As discussed in the last sub-section, there are two main targets for the hardware pattern generator(i)
low area and (ii) pseudo-exhaustive pattern generation (i.e., generate as many different patterns from 0
to 2n as possible, if there are n flip-flops in the register). Linear feedback shift register (LFSR) pattern
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generator is most commonly used for test pattern generation in BIST because it satisfies the above two
conditions. There are basically two types of LFSRs, (i) standard LFSR and (ii) modular LFSR.
4. Hardware response compactor
As discussed in Section 2 of this module, expected output (i.e., golden response) of the CUT cannot be
sorted explicitly in a memory and compared with response obtained from the CUT. In other words, in
BIST, it is necessary to compress the large number of CUT responses to a manageable size that can be
stored in a memory and compared. In response compaction, sometimes it may happen that the
compacted response of the CUT under normal and failure conditions are same. This is called aliasing
during compaction.

The major problem in testing (and ATPG) of sequential circuits is difficulty in controlling secondary
inputs (i.e., outputs of flip-flops) and difficulty in observing secondary outputs (i.e., inputs of flip-flops).
In this lecture we will discuss various techniques to make the flip-flops controllable and observable,
which convert a sequential circuit into virtual combinational one. Following that ATPG for combinational
circuits would suffice for sequential circuits. However, for achieving this, additional circuitry, called
design for test (DFT), will be put on-chip, which would add to extra area overhead.
In the next section we will explore different schemes to control and observe the flip-flops.
2. Controllability and observability of flip-flops
2.1 Set and reset lines
One of the simplest way to directly control flip-flops is through set-reset lines. Set-reset lines can directly
make the output of a flip-flop to be 1/0 without any input and clock pulse. A D flip-flop with set-reset
lines is shown in Figure 1 and its functionality is shown in Table 1.

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From the truth table it may be observed that set (reset) lines makes the output 1(0) irrespective of
input D and clock pulse. However, both the set and reset lines cannot be made high simultaneously.
Also, when the D-flip-flop functions normally, both set and reset lines are kept low.

Now we will see how use of this type of flip-flop helps in testing the circuit given in exercise of last
lecture (Lecture 1, module 12). The circuit with a s-a-1 fault in the primary input line is shown in Figure 2
(a). Also, the flip-flop has set/reset lines. By D-algorithm, a test pattern would be: primary input =0,
secondary input (other input of XOR gate)=0 and fault effect at primary output = D. So in Step-1 (Figure
2 (b)), set =1 and reset =0 (and and primary input =X); this makes output of flip-flop (i.e., secondary
input) to be 1. In Step-2 (Figure 2 (c)), set =0, reset =0 and primary input =0; this sensitizes fault location
as D and its effect propagates to the input of the flip-flop as D . Also a positive clock pulse is applied
which transfers D to output of the flip-flop (primary output). These two steps complete ATPG (and
testing) of the fault.

So it may be observed that the fault which was un-testable by time frame expansion method becomes
testable using set/reset flip-flop. Further, one pattern is required to set/reset the flip-flops and another
pattern (at primary inputs) is required to sensitize and propagate the fault effect to a primary output.
So, unlike time frame expansion method where dseq+1 test patterns are required ( dseqpatterns to
initialize the flip-flops and one pattern to sensitize/propagate fault effects), in case of set/reset flip-flops
only two patters are required (one to set or reset the flops and one to sensitize/propagate fault effects).
This saving in number of test patterns (i.e., test time) is illustrated in the circuit example of Figure 10 of
the last lecture. The circuit (Figure 10 of Lecture 1, module 12) with set/reset flip flops is shown in Figure
3(a).
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(a) Circuit

(b)step1 flip flop set

( c) step2 test pattern applied fault effect propagated
Figure 3. Testing using set/reset flip-flops: illustration of saving in test patterns
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As discussed in the last lecture, three patterns were required to test the s-a-0 fault at net j:
(i) a =X, b =X, c =1 and clock pulse (ii) a =X, b =1, c =1 and clock pulse and (iii) a =1, b =1, c =X.
Also it is to be noted that dseq=2, for the circuit.

Now, by using the set/reset flip-flops, we will see only two patterns are required to test the
fault. By ATPG using D-algorithm, nets d and i are to be 1 for testing the fault. So both the flip-
flops are set by the pattern: a =X, b =X, c =X, set (F1)=1, reset (F1)=0, set (F2)=1 and reset (F2)=0;
this is shown in Figure 3(b). Finally, pattern a =1, b =1, c =X, set (F1)=0, reset (F1)=0, set (F2)=0
and reset (F2)=0 is applied to sensitize and propagate the effect of the fault to primary output;
this is shown in Figure 3(c).

So, only two patterns can test the fault. However the most important point is Irrespective of
the value of dseq, only two patterns are required to test a sequential circuit with set/reset flip-
flops. The gain can be easily understood because any practical circuit has more than thousands
of flip-flops. On the other hand, there is a big problem with the scheme that makes it impractical
to be applied in a practical system. An input output block diagram of the circuit of Figure 3 is
shown in Figure 4. It may be noted that it has 9 I/O pins (3 primary inputs + 1 primary output +2
x nffs set-reset lines, where nffs is the number of flip-flops and a clock). The largest number of
I/O pins supported in most complicated packages is about 1024. So, for a circuit with thousands
of flip-flops, this approach requires a package of thousands of I/O pins (for the 2 x nffs factor)
with makes it impractical.